High Performance Optical Interconnect Project

Project Plan

May 07-06

Client: Lockheed Martin

Advisors: Dr. Somani, Dr. Mina, Dr. Weber

Team Members: David Sheets, Jay Becker, Adam Fritz,

and Layth Al-Jalil

DISCLAIMER NOTICE!
DISCLAIMER: This document was developed as a part of the requirements of an electrical and
computer engineering course at Iowa State University, Ames, Iowa. This document does not constitute a
professional engineering design or a professional land surveying document. Although the information is
intended to be accurate, the associated students, faculty, and Iowa State University make no claims,
promises, or guarantees about the accuracy, completeness, quality, or adequacy of the information. The
user of this document shall ensure that any such use does not violate any laws with regard to professional
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document that is required to be under the responsible charge of a licensed engineer or surveyor. This
document is copyrighted by the students who produced this document and the associated faculty advisors.
No part may be reproduced without the written permission of the senior design course coordinator.

October 10, 2006

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Table of Contents
ITEM PAGE
1 Introduction............................................................................................................... 9
1.1 Executive Summary .......................................................................................... 9
1.2 Acknowledgement ............................................................................................. 9
1.3 Problem Statement.......................................................................................... 10
1.3.1 The Problem ............................................................................................ 10
1.3.2 The Solution............................................................................................. 11
1.3.2.1 Option 1: TDM Based Approach Using Aurora .................................. 12
1.3.2.2 Option 2: 10Gbit Ethernet (LAN PHY)................................................ 12
1.3.2.3 Option 3: 10Gbit Ethernet (10GBASE-LX4) ....................................... 12
1.3.2.4 Option 4: RapidIO .................................................................................. 13
1.4 Operating Environment .................................................................................... 13
1.4.1 Laboratory Operating Environment .................................................... 13
1.4.2 Deployment Operating Environment.................................................... 13
1.5 Intended User(s) and Use(s) ........................................................................... 13
1.5.1 Intended User(s) ...................................................................................... 13
1.5.2 Intended Use(s)........................................................................................ 14
1.6 Assumptions and Limitations ........................................................................ 14
1.6.1 Assumptions ............................................................................................ 14
1.6.2 Limitations............................................................................................... 14
1.7 Expected End Product...................................................................................... 15
1.7.1 Intellectual Properties ............................................................................... 15
1.7.2 System Hardware....................................................................................... 15
1.7.3 Software ...................................................................................................... 15
2. Proposed Approach and Statement of Work ........................................................ 17
2.1 Proposed Approach ........................................................................................ 17
2.1.1 Functional Requirements ....................................................................... 17
2.1.1.1 Topology............................................................................................... 17
2.1.1.2 Multiplexing......................................................................................... 18
2.1.1.3 Transmission ....................................................................................... 18
2.1.1.4 Processor / Memory Interface.............Error! Bookmark not defined.
2.1.1.5 Board / Fiber Optic Interface ............................................................ 18
2.1.1.6 COTS.................................................................................................... 18
2.1.1.7 Data Encoding ..................................................................................... 18
2.1.2 Constraint Considerations ..................................................................... 19
2.1.2.1 Topology............................................................................................... 19
2.1.2.2 Multiplexing......................................................................................... 19
2.1.2.3 Transmission ........................................................................................... 19
2.1.2.4 Processor / Memory Interface.............Error! Bookmark not defined.
2.1.2.5 Board / Fiber Optical Interface ............................................................. 20
2.1.3 Technology Considerations .................................................................... 20
2.1.3.1 Overview .............................................................................................. 20
2.1.3.2 Processor and memory module.............................................................. 20
2.1.3.2 Board / Fiber Optic Interconnect .......................................................... 20
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2.1.4 Technical Approach Considerations ..................................................... 21

2.1.5 Testing Requirements............................................................................. 21
2.1.6 Security Considerations.............................................................................. 21
2.1.6.1 Project Security.................................................................................... 22
2.1.6.1.1 Intellectual Properties ..................................................................... 22
2.1.6.1.2 Physical Hardware Properties ........................................................ 22
2.1.6.2 Product Security...................................................................................... 22
2.1.6.2.1 Electromagnetic Interference ...................................................... 22
2.1.6.2.2 TEMPEST Certification.................................................................. 23
2.1.6.3 Personnel Security ............................................................................... 23
2.1.7 Safety Considerations ................................................................................. 23
2.1.7.1 Optical Safety ....................................................................................... 23
2.1.7.2 General Electrical Safety........................................................................ 23
2.1.8 Intellectual Property Considerations ........................................................... 23
2.1.9 Commercialization Considerations .............................................................. 24
2.1.10 Possible risks and risk management (required)..................................... 24
2.1.11 Milestones and Evaluation .......................................................................... 25
2.1.12 Project Tracking Procedures ................................................................... 25
2.2 Statement of Work.......................................................................................... 26
2.2.1 Task No. 1 - Problem definition................................................................. 26
2.2.1.1 Task Objective: .................................................................................... 26
2.2.1.2 Task Approach:.................................................................................... 26
2.2.1.3 Task Expected Results:........................................................................ 26
2.2.1.4 Subtask No. 1a - Definition of Use...................................................... 26
2.2.1.5 Subtask No. 1b - Topological Definition ............................................ 27
2.2.1.6 Subtask No. 1c - Communication Definition ..................................... 27
2.2.1.7 Subtask No. 1d - Processor - Memory Definition.............................. 27
2.2.1.8 Subtask No. 1e - Research ................................................................... 28
2.2.2 Task No. 2 – Technology implementation considerations and selection 28
2.2.2.1 Task Objective: .................................................................................... 28
2.2.2.2 Task Approach:.................................................................................... 28
2.2.2.3 Task Expected Results:........................................................................ 28
2.2.2.4 Subtask No. 2a - Fiber Optic Hardware ............................................ 28
2.2.2.5 Subtask No. 2b - Processor / Memory Hardware ............................. 28
2.2.2.6 Subtask No. 2c - Signal Encoding....................................................... 29
2.2.2.7 Subtask No. 2d - Signal Multiplexing................................................. 29
2.2.2.8 Subtask No. 2e - System Topology...................................................... 29
2.2.3 Task No. 3 - Prototype Design ................................................................... 29
2.2.3.1 Task Objective: .................................................................................... 29
2.2.3.2 Task Approach:.................................................................................... 30
2.2.3.3 Task Expected Results:........................................................................ 30
2.2.4 Task No. 4 - Prototypes implementation................................................... 30
2.2.4.1 Task Objective: .................................................................................... 30
2.2.4.2 Task Approach:.................................................................................... 30
2.2.4.3 Task Expected Results:........................................................................ 31
2.2.5 Task No. 5 - Prototypes Testing................................................................. 31
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2.2.5.1 Task Objective: .................................................................................... 31

2.2.5.2 Task Approach:.................................................................................... 31
2.2.5.3 Task Expected Results:........................................................................ 31
2.2.6 Task No. 6 - End-product documentation ................................................ 31
2.2.6.1 Task Objective: .................................................................................... 31
2.2.6.2 Task Approach:.................................................................................... 31
2.2.6.3 Task Expected Results:........................................................................ 31
2.2.7 Task No. 7 - End-product demonstration ................................................. 32
2.2.7.1 Task Objective: .................................................................................... 32
2.2.7.2 Task Approach:.................................................................................... 32
2.2.7.3 Task Expected Results:........................................................................ 32
2.2.8 Task No. 8 - Project reporting ................................................................... 32
2.2.8.1 Task Objective: .................................................................................... 32
2.2.8.2 Task Approach:.................................................................................... 32
2.2.8.3 Task Expected Results:........................................................................ 32
3. Resources and Schedules..........................................Error! Bookmark not defined.
3.1 Resources ..........................................................Error! Bookmark not defined.
3.1.1 Personnel...................................................Error! Bookmark not defined.
3.1.2 Other Resources .......................................Error! Bookmark not defined.
3.1.3 Financial Requirements...........................Error! Bookmark not defined.
3.2 Schedules...........................................................Error! Bookmark not defined.
3.2.1 Project Schedule.......................................Error! Bookmark not defined.
3.2.2 Deliverables ..............................................Error! Bookmark not defined.
4. Closure Materials......................................................Error! Bookmark not defined.
4.1 Project team information:..................................Error! Bookmark not defined.
4.2 Closing Summary: ..............................................Error! Bookmark not defined.
4.3 References:...........................................................Error! Bookmark not defined.
4.4 Appendices........................................................Error! Bookmark not defined.
4.4.1 Appendix A: Planned System OverviewError! Bookmark not
defined.
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List of Tables
Table 1: Statement of Work..........................................................................................21
Table 2: Personnel Effort Requirements (hours)........................................................29
Table 3: Other Resource Requirements ......................................................................30
Table 4: Financial Resource Requirements.................................................................30
Table 5: Project Schedule..............................................................................................31
Table 6: Deliverables Schedule .....................................................................................32
Table 7: Project Team Information .............................................................................32
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List of Figures
Figure 1: Board level overview ......................................................................................15
Figure 2: System Topology .............................................................................................17
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List of Definitions
Aurora – A simple protocol used in signal transmission
Backplane – A stationary transmitting material, whose available connections may or may
not all be used

Board - A circuit card with processing, memory, and input/output capability.

CDMA – Code division multiple access
COTS – Commercial off-the-shelf
EMI – Electromagnetic interference
Ethernet – A family of networking technologies for local area networks
FPGA – Field programmable gate array – A reprogrammable chip used.
LAN – Local area network
LRU – Line replaceable unit (interconnected with cabling)
LRM – Line replaceable module (interconnected with a common backplane)
Modal distortion – A type of distortion where a signal spreads with respect to time
Moore's Law - the empirical observation that the transistor density of integrated circuits,
with respect to minimum component cost, doubles every 24 months, attributed to Gordon
E. Moore, a co-founder of Intel.
Multi mode fiber – Fiber optic cable that transmits lights through any of a number of
different paths down the length of the fiber
Multiplexing – combining multiple sources of information into one
Network - The interconnection of boards, constituent equipment, and functional
software. Synonymous with "system", however has the connotation of how the network
operates, not how the system is used.

Node – A point of connection to the Optical Interconnect

Parallel – Signals traveling in multiple wires
Protocol – a set of rules governing communication between electronic devices
RapidIO – a high-performance, packet-switched, interconnect technology
RF – Radio frequency
RISC – Reduced instruction set computer
Serial – Signals traveling in a single wire.
Single mode fiber – Fiber optic cable that transmits light through a single path
System - The interconnection of boards, constituent equipment, and functional software.
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Synonymous with "network", however has the connotation of how the system is used, not
how the network operates.

TDM – Time division multiplexing – Each component of the system gets a fraction of
the available time to transmit, and listens the rest of the time.
Transducer – A device that converts one type of energy into another
Wavelength – the distance between repeating units of a wave pattern
WDM – Wave division multiplexing – Signals travel at different wavelengths allowing
multiple transmissions as one time.

LAN PHY – A standard that defines Ethernet transmission between routers and switches.
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1 Introduction
The project will be introduced through an executive summary, coupled with
acknowledgements, problem statement and proposed solution, proposed operating
environment, intended user(s) and use(s), limitations and assumptions, end product
description, and other deliverables.

1.1 Executive Summary

The May07-06 Senior Design team has been tasked with developing an approach to
interconnect memory/processor nodes together with fiber optic communication. The end
product shall be a system of network interface cards (NIC) which transmit at 10Gbps and
are linked with fiber optic line, as well as a report summarizing performance results of
such a system. The NIC(s) shall be embedded into either a computer or an avionics unit.

The topology selected for this project will be a ring topology where each NIC is
connected either to de-centralized fiber optic switches that will direct the communication
“traffic” throughout the network or where the fiber optic switch is embedded on the NIC.
This will mean that there will not physically be a central switch which interconnects the
NIC(s), and therefore the , rather there will be a switch on board each NIC that will
monitor inbound and outbound communication. Additionally, the NIC(s) that will be
selected will ideally have on-board termination capabilities to terminate a signal that has
traversed the ring and is incident to the original transmitting node. This is important to
eliminate undesired signal activity on the fiber optic lines. In order to maintain efficient
and effective communication between processors, a time division multiplexing scheme
shall be used.

Finally, these interconnected processor boards will be integrated into existing avionics
equipment and interface with like boards integrated into other equipment. The purpose is
to provide a lightweight, EMI insensitive, high speed interconnect in place of heavier,
slower, and EMI sensitive cabling. The transmission rate for this solution 10Gbps.

1.2 Acknowledgement

The group recognizes the contribution of Drs. Somani, Mina, and Weber to the technical
understanding of fiber optic communication and processor networking. Specifically, Dr.
Weber has provided great insight into the problems of fiber optic communication; Dr.
Mina has provided great insight into the problem of moving information from an
electronic signal to a optic signal; and Dr. Somani has provided guidance toward the
approach that should be taken when building a network of processing nodes.

The group further recognizes Nathan VanderHorn, Michael Frederick, and Rashmi
Bahuguna, who are Ph.D. candidates working in the Dependable Computing and
Networking Laboratory. Also, Jason Boyd, masters student in electrical engineering, has
assisted the group in formulating the current design approach. Kevin Finck, senior in
Electrical Engineering at ISU, also has contributed to this project with suggestions.
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Rick Stevens has provided a general understanding on the needs of Lockheed Martin on
this project and Aaron Cortes, ISU Alumni, former student for Dr. Somani, and Lockheed
Martin employee, have both provided the necessary information for this team to continue
developing the architecture of this project.

1.3 Problem Statement

The aerospace industry is driving an effort to decentralize computer processing ability

within a platform or vehicle. As it has with efforts to leave older communication
standards such as ARINC 429 and MIL-STD-1553 behind and embrace newer 10/100
Base-T Ethernet and even Gigabit Ethernet for system interconnectivity, so has the
aerospace industry been driving toward leaving conventional interconnect hardware off
of new application in favor of fiber optic interconnection.

Increases in throughput demand on all communication systems stems from the sheer bulk
of information being transferred between elements of any given network. This project is
aimed towards avionics applications where the network is the interconnection of all the
computers on board.

The ability to transmit data also hinges on the flexibility of the data transfer scheme in
place. The drive toward 10Gb allows a system to operate a fraction of the total
throughput, not placing a scheduling and data transfer burden on the system. The other
facet of 10Gbps data transfer is the marketability of this concept. See Section 2.1.9.

1.3.1 The Problem

Computer processing is distributed throughout avionic platforms, and the ability of

processors to communicate greatly enhances the functionality of one’s platform. The
need arises to separate computer processing when:

• Electrical domain hardware cannot provide the reliable throughput of fiber optic
communication. However, most current avionics systems do not natively support
fiber optic traffic. Thus an interface must be devised.
• Moore’s Law fails to keep up with increases in processor ability. Modern avionics
software drives a demand for increasing processor speed, thus a mitigation strategy
involves increasing processor power by binding multiple processors to perform a
given operation.

There are problems with using conventional communication standards. Data protocols
and the hardware on which such is transmitted are interdependent and inseparable.
Current communication interconnect solutions include:

• MIL-STD-1553: Introduced on the first F-16 fighter aircraft in 1973, this standard
provides a throughput of 1 Megabit per second.
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• ARINC 429: Used widely in the avionics industry, the maximum transfer rate is 100
kilobits per second packaged in a 32 bit word.
• ETHERNET 10/100: This technology, originated for commercial networks, found a
patron in the aerospace industry where budgetary constraints drove the adoption of
COTS equipment in place of redefining military standards. Maximum throughput of
100 Megabits per second.
• GIGABIT ETHERNET: Uses twice as many signals as 10/100 Base T Ethernet, and
had ten times the throughput.

Today’s avionics marketplace wants to purchase solutions that allow for greater
throughput between hardware elements in a system. Currently, gigabit Ethernet is the
most commercially available "fast" solution for the problem of system interconnectivity.
However, the need to push more data faster between points in an avionics network
exasperates the engineering limits of transmitting data electronically.

• Moving data via conducting wire necessitates considering the effects of

electromagnetic interference, both caused by the wire and imposed onto the wire
externally.
• Greater data transmission rates require more wire and cable to be strung within a
platform, increasing the mass of the vehicle or platform.
• Complex serializing and deserializing schemes are introduced at high frequencies
where signals are multiplexed onto parallel lines for transmission at lower frequency
which, in affect, nets the desired transmission rate.
• The time cost for converting between fiber optics, electrical, and fiber optics is too
expensive for any effective 10Gbps system.
• Current avionics hardware generally does not support fiber optics. ARINC 429 is still
widely used in the industry as a point to point solution, despite its relatively low
throughput.

1.3.2 The Solution

Fiber optic standards provide a consumer-off-the-shelf (COTS) solution to the issue of

transferring data point to point within a platform. While fiber optic hardware and data
encoding are in principle dissimilar, for engineering ease, standards already exist for the
transmission of data on a fiber optic line.

Lockheed Martin has instructed the May07-06 Senior Design Group to compose a system
of at least two NIC(s) interconnected with fiber optic lines and a switch or switches to
facilitate a time division multiplexing scheme between NIC(s). This system shall be able
to potentially support four or more NIC(s).

This project will initially pursue the first option hereafter stated, but does not dismiss the
viability of the other options, or options not yet addressed.
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1.3.2.1 Option 1: TDM Base Approach Using 10Gb Ethernet NIC(s)

NIC to NIC transmission of 10Gbps shall be achieved by a single mode fiber optic cable
linking each node of the network to the next in a ring configuration. The optical signal
transmitted from any given board to the others shall be the same wavelength for every
board.

The multiplexing scheme used to divide time between the four processing boards will be
a TDM scheme. See Section 2.1.1.2.

The NIC card selection shall have Ethernet capability native to it, thus making the
conversation between PCI-X and Ethernet automatic.

This is the option that will be discussed in this document.

1.3.2.2 Option 3: 10Gbit Ethernet (LAN PHY)

LAN PHY is a standard that defines Ethernet transmission between routers and switches.
This solution is applicable over short distances between processing boards. The use of
Ethernet is chosen because of its error correction capabilities and industry wide
application.

Each board would be responsible for two parallel differential transmit signals and two
parallel differential receive signals. This standard does not indicate a multiplexing
scheme. Thus, a TDM approach would be employed where each board receives an equal
amount of time to transmit.

1.3.2.3 Option 4: 10Gbit Ethernet (10GBASE-LX4)

10GBASE-LX4 is a standard that defines Ethernet transmission over a single mode fiber
(up to 10 km) or multimode fiber (up to 300 m) employing a wavelength division
multiplexing scheme (WDM).

1.3.2.4 Option 2: TDM Based Approach Using Aurora

Board-to-board transmission of 10Gbit per second shall be achieved by serializing four

signals coming out of each board at 2.5Gbit per second. The optical signal transmitted
from any given board to the others shall be the same wavelength for every board. The
system envisioned by this project shall have four boards connected via single mode fiber
optic lines.

The multiplexing scheme used to divide time between the four processing boards will be
a TDM scheme. See Section 2.1.1.2.

Aurora is a simple serial data transfer protocol that uses 8-bit-to-10-bit encoding or 64-
bit-to-66-bit encoding. This 8-bit/10-bit encoding is done so that the clock signal is sent
 - 13 -

along with a packet so that the transmitter and receiver can synchronize clocks. This
format is also chosen because of ease of use.

1.3.2.5 Option 5: RapidIO

RapidIO is a system interconnect, and makes no assumption of what type of hardware is

being utilized. Like Aurora, it is uses 8-bit/10-bit encoding for clocking purposes.
RapidIO is a point to point form of communication, meaning there is no addressing done
so that a node will know if some signal is intended for it.

The multiplexing scheme employed would be either TDM or WDM.

1.4 Operating Environment

The operating environment drives the selection of parts, software, and topology; the
operating environment can be the platform on which the system operates, the ambient
conditions affecting the system, or the affect users may have on the system.

1.4.1 Laboratory Operating Environment

Development and testing of the system will require a lab environment where boards can
be integrated and removed from the network easily and controlled tests can be performed
to confirm system fidelity. The boards will be linked together and each board will sit as
an interface between two different computers.

1.4.2 Deployment Operating Environment

Lockheed Martin’s end use for this product will be to set a board in between LRU’s and
LRM’s within a given platform or vehicle and use the board to transfer slower electrical
data transmitted out of a given box into much faster fiber optic signals. The operating
environment of such a solution will be military aircraft and other military vehicles. Such
a system will likely be derived from the reports made during the project detailing the
performance of the system.

1.5 Intended User(s) and Use(s)

The intended user(s) and intended use(s) are interdependent but for the purpose of
analysis each should be considered independently. This is particularly true for passive
users who may not be aware they are using this system.

1.5.1 Intended User(s)

The intended user of this system is a pilot who is operating an airplane with avionic
equipment interconnected using this system. This user will not directly interface with the
hardware but will be directly affected by this equipment, both in the sense that system
latency will be decreased as a consequence of this system, and also that failure of the
 - 14 -

optical interconnect will at best mean reverting to older equipment and at worst mean
complete system failure.

The user with more direct interaction with the optic interconnect will be engineers at
Lockheed Martin and researchers/students at Iowa State University. Their interaction
with the optical interconnect will be to directly manipulate the interconnect and not
necessarily rely on the system to maintain system operability.

1.5.2 Intended Use(s)

The first and principle use of the interconnect is to link LRU’s and LRM’s together
within an avionics platform and to facilitate accelerated data transfer therein. Whereas
prior to the deployment of this interconnect an LRU may have to transmit at a slower
speed due to bus or transmission limitations, now there is an interconnect whose speed
greatly exceeds the processing speed and the transmission speed of most LRU’s. This
raises the limit on how fast an LRU can transmit.

Secondary to its use as a backbone between LRU’s, this system will also be used by
researchers at Iowa State and by engineers at Lockheed Martin as a means of testing the
viability of different hardware protocols, processor/memory configurations, and fiber
optic technologies as a means of solving interconnect problems in future avionic systems.

1.6 Assumptions and Limitations

This section encompasses project level constraints at the beginning of the project.

1.6.1 Assumptions

• Lockheed Martin will provide a budget of $5000 for purchase of COTS equipment.
• The processor/memory configuration will be solved by purchasing Xilinx Virtex II
boards, or equivalent. There will not be a requirement to develop a board from
scratch.
• This project will involve exactly four process/memory modules.
• Processor boards will be provided by either Iowa State University or by Lockheed
Martin.
• Interconnect equipment will be purchased by May07-06 Senior Design Team.
• Interconnect system will be plug and play compatible.
• Development of this system will be largely drawn from existing research being done
by the Dependable Computing and Networking Laboratory.

1.6.2 Limitations

• The duration of the project is 8 months.

• The budget for the project is $5000.
• While the final system will involve boards being directly integrated into LRU’s, this
project will have stand alone boards that are not integrated into a platform.
 - 15 -

• Students cannot commit to this project full time, thus causing some tasks to be
prolonged and done poorly. Poor work requires group oversight, and thus more time.
• There are approximately twenty multi-gigabit transceivers on the market today.
• There are approximately five processor/memory boards that support gigabit transfer
on the market which are within the budgetary constraints.

1.7 Expected End Product

The end product of this project can be broken into intellectual properties, hardware
system, and software.

1.7.1 Intellectual Properties

After the hardware system has been implemented, a report must be created to describe the
results of the experimentation. These results will be correlated with the design approach
and with data derived from alternative but equivalent fiber optic interface
implementations. This report, along with project documentation, will be furnished to the
customer, Lockheed Martin, as an end product of this senior design project.

1.7.2 System Hardware

This product will be comprised of a board that houses a processor, memory, and RF
transceivers. Sequentially next in the dataflow, a parallel to serial converter sits to take
information off the board and renders it into the 10Gbps rate specified and desired. Next
in the sequence, a laser transducer will sit to convert the serial RF signal brought out of
the converters into an optical signal. Fiber optic cabling will then interconnect one board
to another board.
Data received from
connection to the
10/100 PHY fiber optic cable
Ethernet network.
Data output to
the Processor Fast build in
RAM

RocketIO RocketIO
Processor Up to Laser single
Transceivers Transceivers 10 GHz
And logic mode
Use Ethernet Use Aurora converter
circuit transducer
Protocol Protocol

Virtex-II Pro FPGA

Where fast RAM,
configurable logic,
and Processors are.

10/100 PHY
Ethernet
Data Input From Data send to
Processor connection to the
External slower fiber optic cable
and larger RAM than build in network.
FPGA RAM

XC2VP30-FF1152
Board

Figure 1
 - 16 -

1.7.3 Software

Software driving this system shall be comprised of three layers:

• Driver level, to provide the board with configuration code.

• Operating system level, to manage tasks and instruct devices to operate.
• Higher level processing software, to process information being sent out of the fiber
optic interconnect.
 - 17 -

2. Proposed Approach and Statement of Work

The proposed approach and statement of work are interdependent and address different
aspects of how the solution will be reached. The proposed approach is a pre-design
process; the statement of work is a scheduling process.

2.1 Proposed Approach

The proposed approach shall be derived from 1.3.2.1 (Option 1 of Problem Statement).
This is a TDM based approach using a ring topology. This ensures decentralized control
of the fiber optic network where each NIC is self governed, using the same governance as
the any other NIC to which it is connected.

2.1.1 Functional Requirements

Functional requirements are driven by the overall requirement of a portable fiber optic
network the transfers data between nodes at ten gigabits per second.

2.1.1.1 Topology

The topology of the interconnect shall be for each NIC to sit in either a star or ring
configuration. A star, commonly used in Ethernet applications, would involve a central
switch that routes fiber optic data to an appropriate destination and no where else.

A ring architecture would literally be a connection of boards to form a circle where a

transmitted signal could potential come back on itself.

One board shall have control of the fiber optic line at a given time and the signal sent
shall appear at the receiver port of all four boards.

Figure 2: System Topology

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2.1.1.2 Multiplexing

The multiplexing scheme shall allow multiple boards to communicate over the same fiber
optic line. This system shall multiplex access to the line so that only one board is
communicating over the line at a given time.

The TDM scheme shall insure fairness, hence defined:

ƒ Fairness shall mean that no board shall have to wait to transmit while resources are
available and unused
ƒ Fairness shall mean that no board shall be considered a priority for transmission
ƒ Fairness shall mean that each board has equal access to resources.

The algorithm for the TDM scheme shall require that each NIC be synchronized and shall
broadcast the total amount of data a specific computer, housing the NIC, requires to
transmit. Each board will be made aware of all other computer's size requests and each
NIC shall use the same algorithm to schedule itself. Specifically, for a given time period,
each NIC will be allowed to broadcast on the ring for an amount of time proportional to
the amount of data that NIC needs to transmit relative to the total amount of data all NICs
wish to transmit. Larger time slices will be scheduled first, and every NIC will get access
the network in a periodic fashion.

2.1.1.3 Transmission

Node to node data transmission shall be done at 10 gigabits per second. There is no
restriction on whether this shall be done as a parallel or serial signal.

The medium of transmission shall be fiber optic line, either single-mode or multi-mode.

Optical transceiver shall be of sufficient power that every transceiver at every node can
be driven accurately by the optical signal.

2.1.1.4 Board / Fiber Optic Interface

Each board will render a differential RF signal that will drive a laser transducer. Such
shall then be transmitted down a fiber optic line for distribution between nodes.
Optimally, this shall be embedded on an NIC.

2.1.1.5 COTS

All equipment used to build this system shall be consumer-off-the-shelf equipment.

2.1.1.6 Data Encoding

Data transmitted between NIC(s) shall be encoded using Ethernet, Aurora, Fiber Channel,
or possibly RapidIO.
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2.1.2 Constraint Considerations

Constraints are generally a result of budget and time limitations, and technological
limitations.

2.1.2.1 Topology

Topology hinges on one node being able to transmit information to all other nodes
without significant propagation delay. As nodes are added to the topology, the power of
the fiber optic signal will degrade. Thus, there is an upper bound on nodes which is
dependant on the receiver chosen to transfer optical information into RF information.

With reference to a transmitting node, a node degrades the signal that appears at the next
farthest node. This is because each node requires some optical energy to be routed into
that node's transceiver to ascertain whether information being transmitted is valid for that
node.

2.1.2.2 Multiplexing

The initial implementation of TDM will involve giving each node a proportional amount
of time to transmit. This means that as nodes are added, each node will be given less time
to transmit. There is therefore a bound on each node as to the size of any information
packet it wishes to transmit.

Subsequent implementations of TDM will involve greater fairness, in that boards will be
allotted time based on the importance and length of the data to be transferred. However,
in any TDM architecture, only one node may transmit at a time. This neglects the
possibility that there may be n sets of i nodes that wish to communicate and there are no
nodes shared between n sets, which would then allow multiple transmission and
receptions simultaneously.

The current system will use one wavelength for data transfer. Thus, only one board may
transmit at a given time without employment of CDMA.

Code division multiple access is a viable option except the complexity of the solution is
outside the scope of Senior Design.

Waveform division multiplexing may be a preferable option if one wishes to let multiple
boards talk simultaneously. This as well is outside the scope of Senior Design.

2.1.2.3 Transmission

Transmission of 10Gbit/s signal requires hardware to sit between the board and the laser
transducer to serialize a parallel signal coming off the board unless the board generates a
10 GHz signal natively.
 - 20 -

Any laser transducer driven by RF shall be able to switch on faster than 0.05 ns and
switch off faster than 0.05 ns. This nets a maximum period for a bit as 0.1 ns, which is
the period of a signal whose frequency is 10 GHz.

2.1.2.5 Board / Fiber Optical Interface

Transmission distance through multi-mode fiber optics cannot exceed 300 meters for
desired 10Gbit/s transfer rate.

Transmission over significant distances using multi-mode fibers must utilize optical
wavelengths between 650 and 750 nm.

Use of multi-mode fiber introduces the prospect of added signal distortion due to modal
distortion.

2.1.2 Technology Considerations

Technology considerations are driven by trade study which organizes what is available
commercially. The prime effort is to find a board with fiber optic switching, laser
transceiver, and data encoding all embedded, reducing the system complexity to a board
embedded into a host computer, acting as a NIC between the host and other host
computers.

2.1.3.1 Overview

The technology to realize this system exists, thus there is no development work to be
done, only integration of parts. These parts are:

• Processor and memory module

• Parallel to serial converter at RF frequencies
• Laser transducer
• Fiber optic cable
• Power supply

2.1.3.2 Network Interface Card

This project will fiber optic NIC that us an FPGA with on chip memory, processing, and
I/O control. Locating these components on chip greatly enhances the speed by which
memory, processor, and the outside world interact.

2.1.3.2 Board / Fiber Optic Interconnect

RocketIO transceivers will conduct an RF signal to a parallel to serial converter. This

serializer must be able to operate at 10GHz. The output of the serializer will then be
transmitted to a laser transducer.
 - 21 -

2.1.3 Technical Approach Considerations

This project will adopt the attitude of having two separable and independent systems:
processor/memory board and the transducer/fiber interconnect between process/memory
nodes.

The process/memory board subsystems shall be:

• External board interface over Ethernet and RS-232

• Processing of information to be transmitted
• Processing of information received.

The transducer/fiber interconnect subsystems shall be:

• Board output to serializer input

• Serializer output to transducer input
• Fiber optic connection between transducers

2.1.4 Testing Requirements

Prior to prototype demonstration, all components (hardware and software) will be tested
thoroughly.

The testing procedure is as follows:

Step 1: A single board will have software loaded onto it which specifies how the FPGA
(specifically the on board processor) will buffer incoming information and how such
information will be transmitted off the board. This step will involve transmitting a file
into the system externally and transmitting such data out. Since this is a loopback test, the
information will come back into the card and processed like received data. Thus, the test
is to ensure data transmitted is the same as data received.

Step 2: Step 1 will be repeated except that between the transmitter and receiver port a
laser transducer will be placed to emit an optical signal out and to transfer optical
information into an RF signal.

Step 3: Step 2 will be repeated with the caveat that another board will be introduced and
monitored to measure the fidelity of information transferred between boards.

2.1.6 Security Considerations

Security will be proportional to the team's access to department laboratories and potential
operating environment.
 - 22 -

2.1.6.1 Project Security

Given the low budget of this Senior Design project, project security is an amalgamation
of various security procedures in place in the College of Engineering and in the Senior
Design Lab.

2.1.6.1.1 Intellectual Properties

All project documentation is stored electronically on student engineering accounts.

Access to these accounts requires a username and a password. Project documentation
may be on the person of any member of the Senior Design team at any given time, thus
ensuring the confidentiality of sensitive information requires added procedures.

• All confidential information furnished by Iowa State or the customer to the team shall
be stored on electronic media outside of network accessible computing.
• Non-confidential information shall be routinely inspected to insure confidential data
has not inadvertently been entered into such a document.
• Software shall be treated like documentation and stored in a like manner.

2.1.6.1.2 Physical Hardware Properties

Hardware, having a physical shape and location, shall utilize the Senior Design
laboratory as necessary to secure and lock those items which are a theft risk. Much of
integration work shall also be done in the Dependable Computing and Networking
Laboratory.

• Hardware not being used for integration shall be stored in the Senior Design Lab,
Town Engineering Building, Iowa State University. The room is monitored with
closed circuit television.
• Hardware currently being used may be left unattended in the DCNL lab but the
presence of closed circuit television in the room shall provide evidence of theft, if
occurring.

2.1.6.2 Product Security

The product itself has security issues which must be addressed. This product may process
or act as a conduit for classified or confidential information.

2.1.6.2.1 Electromagnetic Interference

Radio frequency electrical signals are provided to the laser transducer, which then
converts a 10 GHz signal into a THz (terahertz, or trillion hertz) signal. Given that the
optical THz signal is confined to a waveguide, the transmission of information off of the
waveguide is minimal. Any escaping optical signal is highly directionalized, minimizing
the possibility of being read, intentionally or accidentally.
 - 23 -

However, the electrical signal provided to the laser transducer, being at a much lower
frequency, will not be nearly as directionalized if emitted freely into the ambient
surroundings, and poses a severe data assurance issue. This data may be coupled into
some equipment and be read, intentionally or accidentally, by unauthorized persons.
Also, if data can be coupled off of the board providing the RF signal and the lines
carrying it, data can be coupled onto the board. Data coupled onto the board may be
interpreted as noise, or may be read, intentionally or accidentally, by unauthorized
persons.

2.1.6.2.2 TEMPEST Certification

TEMPEST is a US Military standard for minimizing electromagnetic interference

that may compromise classified or confidential information. TEMPEST is itself
classified, thus certification would require either members of this group to gain a
security clearance or would require the system to be sent to a TEMPEST lab for
certification.

2.1.6.3 Personnel Security

It may be necessary for persons of this group to gain a security clearance from the
Department of Defense. Permanent security clearances take up to a year to gain, but
temporary clearances can be issued on a basis of need. Most security clearances require
US citizenship.

2.1.7 Safety Considerations

This system is a low power application but has optical hazard risks.

2.1.7.1 Optical Safety

This product uses a laser transducer to generate a laser pulse which is intended to be
confined to a waveguide. However, without a waveguide, the laser transducer emits a
high intensity beam of light that, if incident on the eye(s) of a human being, can produce
immediate irritation and possible retina damage.

2.1.7.2 General Electrical Safety

As with all electronics, electricity will be provided to power the unit on. Given the low
voltage and current nature of this system, there is low risk of electrocution. However,
there is a danger of accidentally shorting components together and damaging the board.

2.1.8 Intellectual Property Considerations

The client uses the documentation of the project for future development and expansion.
Since the client is a private company and provides military products, confidentiality may
 - 24 -

be an issue from competitors and security - the client did not provide any consideration
and will contact to address this issue.

2.1.9 Commercialization Considerations

This product has the potential to be commercialized and used as the basis of
interconnectivity for avionics platforms. Driving all development is the concept of a
portable fiber optic LAN, which is not precisely correct to the client's intent but easily
captures the nature of the project. The end product is both the hardware necessary and the
ability to drop boards into avionic's LRU's and immediately have 10Gbps data transfer.

2.1.10 Possible risks and risk management

• Risk: The project extends two semesters, which may result in the absence of a team
member.
Management: Most task assignments have two team members. Also, information is
explained and distributed between team members.

• Risk: Lack of experience with fiber optics, embedded programming, and high speed
circuit design could result in incorrect decisions and require excess time to master.
Management: Allocate time for training on the technology being used. For example,
taking related courses to get familiar with the technology (Virtex-II Pro XC2VP30
based systems - as an Embedded Systems Design course at Iowa State University).
Get assistance from advisors and graduate students that have extensive experience
with these topics.

• Risk: The client is unavailable or provides unclear requirements that could result in
an unsatisfactory end product as well as extra time consumption.
Management: Maintain constant contact with client representative and be prepared
to discuss all aspects of the project in the presence of all team members and advisors.
Keep the client up to speed with additional design requirements and project updates
as they are encountered.

• Risk: Stolen, vandalized, or broken hardware/software materials.

Management: Similar hardware and software is available in department labs as well
as COTS materials that can be utilized. For design software, removable media storage
should be kept as a backup. Also, the access to software is guarded by student user
name and password maintained by the department of engineering at Iowa State
University.

• Risk: Failure to produce working end product prototype.

Management: Maintain well documented test strategy and analyze causes of failure.
Using a phase based design approach will help in the process of building a new
system based on tested parts or simpler versions. This eliminates the possibility of
starting from scratch.
 - 25 -

• Risk: Prototype fails to meet requirements. For example, having an inefficient

transmission scheme.
Management: Part of the project is to explore several available schemes and choose
the best possible one. The team will work promptly on this aspect of the project and
with the help of the advisors and graduate students, we will ensure the successful
completion of the project prototype.

• Risk: Client cancels the project which includes the allocated money.
Management: the department of electrical and computer engineering at Iowa State
University still has the basic resources to finish the project. Also, the team may rely
on the money allocated by the senior design course to finish the project.

2.1.11 Milestones and Evaluation

Criterion for passing a milestone follow the milestone definition. See Project Schedule,
section 3.X, for more information.

• Problem Definition: Seek customer input and co-develop a vision for an end product
which most comfortably fits a target need. Completion is defined when the team
(advisors and students) comes to an agreement with the customer as to how a fiber
optic interconnect will be made plug-and-play ready for any customer system
supporting standard Ethernet traffic.
• Technology Considerations and Selections: Develop competency in fiber optic
communication, networking protocols, and related knowledge areas. Team will
evaluate how to utilize COTS equipment in building a portable fiber optic LAN
within an avionics platform.
• End Product Design: This milestone is to be completed in parallel with prototyping.
Success is defined when an economical selection of COTS equipment can be
integrated to provide the solution to the customer's need and a schematic representing
such a solution is ready.
• End Product Prototype Implementation: This milestone is to be completed in parallel
with design. Success is defined when iterative prototyping drives toward a successful
design. Prototyping shall continue beyond the design phase to explore unaddressed
contingencies and to pursue more sophisticated design solutions.
• End Product Documentation: This milestone is to be completed in parallel with
design and prototyping, ending after the design and prototyping phases have
concluded. Success is defined when documentation accurately represents the
implemented design and communicates to an engineer or engineering manager, who
is a stranger to the project, exactly what the product does and how to use it.
• End Product Demonstration: Success is defined when the customer attends a product
demonstration and is satisfied.

2.1.12 Project Tracking Procedures

The project shall employ the following tactics to track progress:

 - 26 -

Regular meetings are scheduled between the team and the advisors for the purpose of
seeking technical and professional guidance as the project develops. Meetings are also
called for the team to coordinate work and review completed work.

Email is regularly used to submit progress reports to advisors and to Dr. Lamont and
Professor Patterson; this informal means of communication lends itself well to the group
giving instant feedback to a problem as it might arise.

Microsoft Project is utilized to form schedules and measure progress as milestones are
met or are missed.

2.2 Statement of Work

The project activities will be conducted according to the following Gantt chart, which
shows the main tasks:

2.2.1 Task No. 1 - Problem definition

This is chronologically next after the customer defines a need and a desired solution.

2.2.1.1 Task Objective:

Define the problem and propose a solution that meets the criterion provided by the client,
which is a fiber optic interconnect between memory/processor boards that can transmit
information at 10Gbps.

2.2.1.2 Task Approach:

This project requires technical knowledge and experience that have not been covered in
the teammates' coursework. Defining the problem in terms of use, topology,
communication, processing, and research will allow the team to approach the problem
piecemeal and build competency in an aspect of the project. This will yield a team of
experts instead of generalists and yet also leave every team member with a clear vision of
the problem to be solved.

2.2.1.3 Task Expected Results:

Gaining a clear vision of the problem at hand will result in a proposed plan that addresses
the major technical issues and provides a framework for the design of this project.

2.2.1.4 Subtask No. 1a - Definition of Use

Task Objective: Define the intended platform into which the customer wishes to deploy
this product. This drives a litany of functional requirements and is critical to
understanding the nature of the data being transmitted through this network.
 - 27 -

Task Approach: Frequent intercourse with the client to ascertain specific functional
requirements, consultation with advisors to clarify technical details, and research into
fields that teammates' lack proficiency shall assist in defining the ultimate use for this
network. Communication shall drive decision making as options are weighed and
discarded.

Task Expected Results: Clear, concise plan that defines the exact use for this network and
the exact way the team will proceed to develop a solution.

2.2.1.5 Subtask No. 1b - Topological Definition

Task Objective: Define the fiber optic topology of this network.

Task Approach: Research viable topologies (hub-and-spoke, ring, point to point),

measure feasibility, economy, and ease of implementation, and select that topology which
provides easiest method to deliver on the driving requirement of 10Gbps data transfer.

Task Expected Results: Understanding of how boards will be networked and what
encoding and multiplexing schemes work best with a given topology.

2.2.1.6 Subtask No. 1c - Communication Definition

Task Objective: Define the communication protocol for this network.

Task Approach: Research standardized communications protocols (Ethernet, RapidIO,

Aurora, etc.) and determine which system meets the customer's requirements, has the
least system latency, has built in synchronization mechanisms between boards with
unshared clock signals, and is the most feasible to implement in the time constraints of
this project.

Task Expected Results: Selection of a protocol that will be used to encode data for inter-
network transmission.

2.2.1.7 Subtask No. 1d - Processor - Memory Definition

Task Objective: Determine the processor and memory configuration for this system;
specifically, whether to purchase a processor/memory board or build a board with
selected processor/memory components.
Task Approach: Evaluate the budgetary constraints and project throughput requirements
to ascertain the most feasible approach to building or purchasing a board that acts as a
buffer between LRU's.

Task Expected Results: Selection of a processor/memory module that is either client

supplied or available for loan out of the Dependable Computing and Networking
Laboratory.
 - 28 -

2.2.1.8 Subtask No. 1e - Research

Task Objective: Build team competency in fiber optics and microcircuit programming.

Task Approach: Lump competency ramp-up into the design strategy and documentation
strategy by investigating technology and doing research as a parallel aside.

Task Expected Result: Cultivation of distinct skills by different members of the team that
will allow for specialization as prototyping and testing proceed.

2.2.2 Task No. 2 – Technology implementation considerations and selection

Selection of hardware is contingent upon the formatting chosen for board-to-board

communication.

2.2.2.1 Task Objective:

Within the confines of consumer off the shelf equipment, the team must define what
hardware is necessary to achieve a portable fiber optic network transmitting at 10Gbps.

2.2.2.2 Task Approach:

Concurrently with the problem definition, the team must start to consider what type of
technology can be used with the help from advisors and graduate students.

2.2.2.3 Task Expected Results:

The selection of a processor, memory, fiber optic technologies (cable, couplers,

transceivers), topology and message encoding will result.

2.2.2.4 Subtask No. 2a - Fiber Optic Hardware

Task Objective: Select fiber optic transceivers, waveguides, and couplers necessary to
interconnect processor/memory nodes.

Task Approach: The team will consult with Drs. Mina and Weber, authorities in the
realm of fiber optics, and will consult with Ph.D. candidates working in the Dependable
Computing and Networking Laboratory.

Task Expected Result: The team will use similar parts as are used in the DCNL.

2.2.2.5 Subtask No. 2b - Processor / Memory Hardware

Task Objective: Select a processor and memory module in order to integrate the
processor and different levels of memory into one board.
 - 29 -

Task Approach: Consult with the DCNL as to what is being used as a processor/memory
module. Board must be able to support transmission across a fiber optic line at 10 Gbps.

Task Expected Result: The team will use a Xilinx® Virtex™-II Pro FF1152 Kit, the same
as is used by the DCNL.

2.2.2.6 Subtask No. 2c - Signal Encoding

Task Objective: Identify how information passing between boards will be formatted.

Task Approach: Consult with the costumer as to what message format is used commonly
in their platforms.

Task Expected Result: The DCNL uses Aurora as the messaging format, but because of
the industry wide use of Ethernet, the team will likely select Ethernet.

2.2.2.7 Subtask No. 2d - Signal Multiplexing

Task Objective: Based on the topology of the fiber optic network, and whether the signal
will be transmitted in parallel or in serial, the scheme for signal transmission will be
selected from WDM, TDM, or CDM.

Task Approach: The team will identify whether board to board transmission requires a
parallel signal or a serial signal. This will drive towards a purely TDM approach, a TDM
- WDM hybrid, or a straight WDM approach. CDM is to be considered but due to
complexity and project brevity CDM will not be employed.

Task Expected Result: The team will elect to use a purely TDM approach.

2.2.2.8 Subtask No. 2e - System Topology

Task Objective: Identify the most flexible strategy for system topology, including hybrid
topologies that are not purely ring, hub and spoke, or point to point, but a combination
therein.

Task Approach: Consult with the customer as to where this product will be deployed and
what type of topology "fits" into their platform.

Task Expected Result: The project will develop a ring architecture, with the
understanding that the topology may change as the project is fleshed out.

2.2.3 Task No. 3 - Prototype Design

Prototype design shall come in parallel with prototype implementation and testing.

2.2.3.1 Task Objective:

 - 30 -

The design is both a plan and a concept. Completion of a plan, both schematically and
chronologically, will be completed in parallel to the prototype implementation.

2.2.3.2 Task Approach:

The design of a prototype system will be divided into five phases.

• Design a prototype that has one processor/memory board with RF signals looped back
between on-board ports. No fiber optic functionality integrated.
• Design a prototype that has one processor/memory board with fiber optic looped back
between on-board ports. This will necessitate fiber optic transceivers and couplers.
• Design a prototype that has multiple boards in a topology, connected by RF directly.
No fiber optic functionality integrated. One board shall be accessed externally by a
control computer.
• Design a prototype that has multiple boards in a topology, linked by fiber optic lines.
One board shall be accessed externally by a control computer.
• Implement a prototype that has multiple boards in a topology, linked by fiber optic
lines, each board accessed externally by a computer. This shall be as close to a real
system as this project will reach.

2.2.3.3 Task Expected Results:

Have the designs ready to for implementation in hardware and software.

2.2.4 Task No. 4 - Prototypes implementation

Prototype implementation shall come in parallel with prototype design and testing.

2.2.4.1 Task Objective:

Implement each phase system.

2.2.4.2 Task Approach:

The implementation of a prototype system will be divided into five phases.

• Implement a prototype that has one processor/memory board with RF signals looped
back between on-board ports. No fiber optic functionality integrated.
• Implement a prototype that has one processor/memory board with fiber optic looped
back between on-board ports. This will necessitate fiber optic transceivers and
couplers.
• Implement a prototype that has multiple boards in a topology, connected by RF
directly. No fiber optic functionality integrated. One board shall be accessed
externally by a control computer.
• Implement a prototype that has multiple boards in a topology, linked by fiber optic
lines. One board shall be accessed externally by a control computer.
 - 31 -

• Implement a prototype that has multiple boards in a topology, linked by fiber optic
lines, each board accessed externally by a computer. This shall be as close to a real
system as this project will reach.

2.2.4.3 Task Expected Results:

Have the Implementations constructed, downloaded, and able to run successfully.

2.2.5 Task No. 5 - Prototypes Testing

Prototype testing shall come in parallel with prototype implementation and design.

2.2.5.1 Task Objective:

Test each prototype phase for proper expected functions as the design and according to
client requirements.

2.2.5.2 Task Approach:

• Run the prototype and test correctness in packet transmission of data – the data
transmitted without errors.
• Measure how many packets are received successfully within specified number of data
packets and calculate how many had to be retransmitted to determine efficiency of
transmission.
• Also measure latency and rate data is available for transmission.

2.2.5.3 Task Expected Results:

Prototypes run successfully within the design and client requirements.

2.2.6 Task No. 6 - End-product documentation

Documentation is ongoing during design, implementation, and test.

2.2.6.1 Task Objective:

Document end product prototype design, implementation, and testing as well as, problem
definition and technology selection process for advisors and client.
2.2.6.2 Task Approach:

• Create design, implementation, and testing documents in all phases.

• Gather any other documents, notes, and references used in this project.
• Create end product document from previous phase’s documents and others as needed.

2.2.6.3 Task Expected Results:

 - 32 -

Have a final draft to be submitted to advisors and client.

2.2.7 Task No. 7 - End-product demonstration

This task must come at the conclusion of Tasks 1-6.

2.2.7.1 Task Objective:

Demonstrate end product to advisors and industrial review panel.

2.2.7.2 Task Approach:

• Prepare working demonstration of end product design.

• Prepare a power point presentation.

2.2.7.3 Task Expected Results:

Have the design presented to advisors and industrial review panel.

2.2.8 Task No. 8 - Project reporting

Reporting involves documenting the results of our tests and if the project met the client's
requirements.

2.2.8.1 Task Objective:

Prepare bounded project plan and submission to senior design course instructor.

2.2.8.2 Task Approach:

• Assign portion to review by team members of the unbounded project plan.

• Update the portions as necessary.
• Review the proposed project plan by advisors.
• Make changes according to advisors recommendations.
• Submit the plan to the instructor.

2.2.8.3 Task Expected Results:

Have the bounded project plan submitted to the instructor.
 - 33 -

3. Resources and Schedules

This section lists team resources and schedules for the tasks.

3.1 Resources

This section will approximate the resources that will be required in order to successfully
complete this project.

3.1.1 Personnel

The table below indicates the estimated amount of time spent on the following tasks by
each group member:

Task #1: Problem Definition

a) Determine deliverables
b) Define available resources
c) Define client requirements
Task #2: Technology considerations and selection
a) Understand technological concepts
b) Define available technologies
c) Technology selection for the project
Task #3: Prototype Design
a) Define factors to meet requirements
b) Selection of components
c) Finalize system design
d) Order components
Task #4: Prototype Implementation
a) Install hardware and software
b) Test functionality
Task #5: Prototype Testing
a) Implement tests and gather data
b) Compare test data to requirements
Task #6: End Product Documentation
a) Demonstration to advisors
b) Class demonstration
c) Industrial panel demonstration
Task #8: Project documentation and reporting
a) Project plan
b) Design report
c) Project poster
d) Final report

Table 2: Personnel Effort Requirements (hours)

Name David Sheets Adam Fritz Layth Al-Jalil Jay Becker Total
Task #1 a) 7 6 6 6 25
 - 34 -

b) 10 15 12.5 12.5 50
c) 12.5 12.5 10 15 50
a) 10 11 12 12 45
Task #2 b) 10 9 8 8 35
c) 9 9 14 13 45
a) 8 6 9 7 30
b) 10 10 10 10 40
Task #3
c) 10 7 7 6 30
d) 8 6 6 5 25
a) 5 5 15 15 40
Task #4
b) 13 16 7 4 40
a) 8 9 10 8 35
Task #5
b) 10 10 10 10 40
a) 1 1 1 1 4
Task #6 b) 1 1 1 1 4
c) 1 1 1 1 4
a) 12 11 9 8 40
b) 8 9 11 12 40
Task #7
c) 7 6 8 4 25
d) 10 8 6 6 30
Total 170.5 168.5 173.5 164.5 677

3.1.2 Financial Resources

The table below indicates the estimated financial resource requirements anticipated by
the team.

Table 3: Other Resource Requirements

Equipment and Misc. Resources
Item Team Hours Cost
Optical NICs 0 $4,000
Fiber cable 0 $50
2 PCs 0 Donated
Misc. hardware 0 $500
Poster Board 10 $50

3.2 Schedules

The following section illustrates using Gantt charts the approximate schedule to be
followed throughout the course of this project.

3.2.1 Project Schedule

This section details how long the project will take based on how long each task takes and
what tasks follow other tasks.

Table 5: Project Schedule

 - 35 -

3.2.2 Deliverables

This section shows when the project deliverables are due.

Table 6: Deliverables Schedule

 - 36 -

4. Closure Materials

This section includes client, faculty advisors, and group member information, as well as a
summary of the project and references to resources used in preparing the project plan.

4.1 Project team information:

The project client, advisors, and team consist of the following people:

Table 7: Project Team Information

Client
Rick Stevens
Lockheed Martin
Eagan, MN
651-456-3118
rick.c.stevens@lmco.com
 - 37 -

Faculty advisors
Dr. Arun Somani
Dept. Chair & Jerry R. Junkins Professor
Department of Electrical and computer engineering
Iowa State University
2211CooverHall
50011 Ames, IA
TEL: 515-294-0442
arun@iastate.edu

Dr. Mani Mina

Adjunct Assistant Professor
Department of Electrical and computer engineering
Iowa State University
341 Durham
50011 Ames, IA
TEL: 515-294-3918
mmina@iastate.edu
Technical advisors
Dr. Robert Weber
David C. Nicholas Professor
Department of Electrical and computer engineering
Iowa State University
301 Durham
50011 Ames, IA
TEL: 515-294-8723
weber@iastate.edu

Team members
David Sheets (EE/CprE)
8327 Wallace
Ames, IA 50010
319-651-3584
djsheets@iastate.edu

Adam Fritz (EE)

218 Ash Ave.
Ames IA 50014
515-450-1332
afritz@iastate.edu

Jay Becker (CprE/ComS)

4733 Toronto St. Apt. 306
Ames IA 50014
515-290-2669
coln.panic@gmail.com

Layth Hamid Al-Jalil (CprE)

P.O. Box 9097
Ames IA 50014
isuslal@iastate.edu
 - 38 -

4.2 Closing Summary:

The project's main task is to discover what commercially available 10Gbps optical
hardware has the best performance. The team will have to research bus technologies,
research optical technologies, find and purchase equipment that meets specification, and
measure performance of purchased equipment.

The proposed team approach is to utilize the knowledge of the group advisors and
graduate students to understand the concepts and technologies that are involved with the
project. Then, the team will start the design and implementation tasks which will require
increasing time commitments from the team. The expectation for the project’s end
product is a functional system that meets the client’s requirements.

4.3 References:

Stallings, William. High-Speed Networks and Internets, second edition. Prentice Hall,
Inc. Upper Saddle River, New Jersey. 2002.

Mynbaev, Djafar K. and Scheiner, Lowell L. Fiber-Optic Communications Technology.

Prentice Hall, Inc. Upper Saddle River, New Jersey. 2001.

Weber, Robert J. Introduction to Microwave Circuits. IEEE Press, New York, NY. 2001