CHAPTER 1

OVERVIEW

1.1 Introduction:

This Project report portrays a novel architecture of Universal Asynchronous

Receiver Transmitter. UARTs are used for asynchronous serial data communication
between remote embedded systems. The UART is for interfacing computers or
microprocessors to an asynchronous serial data channel. The receiver converts serial
start, data, parity and stop bits. The transmitter converts parallel data into serial form and
automatically adds start, parity and stop bits. The data word length can be 5, 6, 7 or 8
bits. Parity may be odd or even. Parity checking and generation can be inhibited. The stop
bits may be one or two or one and one-half when transmitting 5-bit code.
The Universal Asynchronous Receiver Transmitter (UART) is a popular and
widely-used device for data communication in the field of telecommunication. There are
different versions of UARTs in the industry. Some of them contain FIFOs for the
receiver/transmitter data buffering and some of them have the 9 Data bits mode (Start bit
+ 9 Data bits + Parity + Stop bits). This application note describes a fully configurable
UART optimized for and implemented in a variety of Lattice devices, which have
superior performance and architecture compared to existing semiconductor ASSPs
(application-specific standard products).
This UART reference design contains a receiver and a transmitter. The receiver
performs serial-to-parallel conversion on the asynchronous data frame received from the
serial data input SIN. The transmitter performs parallel-to- serial conversion on the 8-bit
data received from the CPU. In order to synchronize the asynchronous serial data and to
insure the data integrity, Start, Parity and Stop bits are added to the serial data. An
example of the UART frame format is shown in Figure 1 below.
The UART can be used in a wide range of applications including modems,
printers, peripherals and remote data acquisition systems. Utilizing the Intersil advanced
scaled SAJI IV CMOS process permits operation clock frequencies up to 8.0MHz (500K

1
Baud). Power requirements, by comparison, are reduced from 300mW to 10mW. Status
logic increases flexibility and simplifies the user interface.

Figure 1.1 Basic Application of UART

This design can also be instantiated many times to get multiple UARTs in the
same device. For easily embedding the design into a larger implementation, instead of
using tri-state buffers, the bi-directional data bus is separated into two buses, DIN and
DOUT. The transmitter and receiver both share a common internal Clk16X clock. This
internal clock which needs to be 16 times of the desired baud rate clock frequency is
obtained from the on-board clock through the MCLK input directly.
1.2 Features of UART:
• Inserts or extracts standard asynchronous communication bits (Start, Stop and
Parity) to or from the serial data
• Holding and shifting registers eliminate the need for precise synchronization
between the CPU and serial data
• Standard CPU Interface
• Separate interrupt lines for Data Received and Data Transmitted
• A common interrupt line for all internal UART Data and Error events. Interrupt
conditions include: receiver line errors, receiver buffer available, transmit buffer
empty and when a modem status flag change is detected
• Fully prioritized interrupt system control
• MODEM interface functions (CTS, RTS, DSR, DTR, RI and DCD)
• Fully programmable serial interface characteristics:
o 5, 6, 7 or 8-bit characters
o Even, odd, or no-parity bit generation and detection

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 • False Start bit detection
• Line break generation and detection
• Interactive control signaling and status reporting capabilities
• Separate input and output data buses for use as an embedded module in a larger
design
• Transmitter enabled by new data write to Transmit Holding Register
• Receiver synchronizes off the Start bit
• Receiver samples all incoming bits at the center of each bit
1.3 Compatibility:
This UART implementation supports a higher operating speed and lower access
time compared to the function.
1. The Programmable Clock and Baud Rate Generator is not implemented. The
UART internal clock Clk16X runs at 16x of the receiver/transmitter baud clock.
Users can create this clock from the on-board system clock (via the on-chip PLL
when implementing in ispMACH 5000VG devices or via a separate Divide-by-N
clock divisor when implementing in other Lattice CPLD devices) to obtain the
desired baud clock frequency with the PLD. The associated control registers
(Divisor Latch) are also not implemented.
2. The External Crystal Oscillator connections (XTAL1 and XTAL2) are not
supported. Alternatively, an external user-specified MCLK clock drives the
transmitter and receiver clock input either directly or through the PLL (ispMACH
5000VG devices only).
3. The auxiliary user-defined output pins are not supported, because the user can
modify the reference design, and output any internal signals in the Lattice ISP™
PLD device.
4. The user-accessible Scratchpad register is not supported because all Lattice ISP
CPLDs have the built-in User Electronic Signature (UES) register feature.
5. The bidirectional bus D[7:0] is divided into an input bus DIN[7:0] and another
output bus DOUT[7:0]. In case the design is used in a larger CPLD design as an
embedded module, the DOUT[7:0] should directly drive from the output data
multiplexer and not be tri-stated.

3
 CHAPTER 2
INTRODUCTION TO VHDL

2.1 Introduction:
VHDL is an acronym for VHIC Hard ware Description Language. VHSIC is an
acronym for very high speed integrated circuits. Digital circuit design has evolved
rapidly over last 25 years. The earliest digital circuits were designed with vacuum tubes
and transistors. The integrated circuits were then invented were then invented where logic
gates were placed on a single chip. The fist integrated circuit (IC) chips were SSI (Small-
Scale Integrated) chips where the gate count was very small. As technologies became
sophisticated, designers were able to place circuits with hundreds of gates on a chip.
These chips were called MSI (Medium Scale Integrated) chips. With the advent of LSI
(Large Scale Integrated), designers could put thousands of gates on a single chip. At this
point, design process started getting very complicated and designers felt the need to
automate these processes. Computer Aided Design (CAD) techniques began to evolve.
Chip designers began to use circuit logic simulation techniques to verify the functionality
of building blocks of the order of about 100 transistors. The circuits were still tested on
the breadboard and the layout was done on paper or by hand on a graphic computer
terminal.

With the advent of VLSI (Very Large Scale Integrated) technology designers
could design single chip with more than 1, 00,000 transistors. Because of complexity of
the circuits, it was not possible to verify these circuits on a breadboard. Computer-aided
techniques became critical for verification and design of VLSI digital circuits. Computer
programs to do automatic placement and design of VLSI digital circuits layout also
became popular. The designers were now building gate-level digital circuits manually on
graphic terminals. They would build small building blocks and then derive high blocks
from them. This process would continue until they had built the top-level block. Logic
simulators came into existence to verify the functionality of the circuits before they were
fabricated on a chip.

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2.2 Emergence of HDL’s:
For along time, programming languages such as FORTRAIN, PASCAL and C
were being used to describe computer programmings that were sequential in nature.
Similarly, in the digital field, designers felt a need for a standard language to describe
digital circuits.

Thus, hardware description languages (HDLs) came into the existence. HDLS
allowed the designers to model the concurrency of the processors found in hardware
elements. Hardware Description Languages such as VHDL and Verilog HDL became
popular. Verilog HDL originated in 1983 at gateway design automation.

Even though HDLs were popular for large verification, designers had to manually
translate the HDL based design into a schematic circuit with interconnection between
gates. The advent of logic synthesis in the late 1980’s changed the design methodology
radically. Design circuits could be described at a register transfer language by the use of
HDL. The designers have to specify how the data flows between the registers and how
the design processes the data.

The detail of gates and their interconnections to complement the circuit where
automatically extracted by logical synthesis tools from the RTL description. Thus logic
synthesis pushed the HDLs into the forefront of digital design. Designers no longer had
to manually place gates to build digital circuits. They could describe complex circuits at
an abstract level in terms of functionality and data flow by designing those circuits in
HDLs. Logic synthesis tools would implement the specified functionality in terms of
gates and gate interconnections.

HDLs also began to be used for system level design. HDLs were used for
simulation of system boards, interconnection buses, FPGAs (Field Programmable Gate
Arrays) and PALS (Programmable Logic Arrays). A common approach is to design each
IC chip using an HDL and then verify system functionality via simulation.

5
2.3 Need for VHDL:

Typical design flow:

Typical design for designing VLSI IC circuits is shown in figure below.
Unshaded blocks show the level of design representation, shaded blocks show processes
in the design flow.

In any design, specifications are written first. Specifications describe abstractly

the functionality, interface, and overall architecture of the digital circuit to be designed.
At this point, the architects do not need to think about how they will implement this
circuit. A behavioral description is then created to analyze the design in terms of
functionality performance compliance to standards and other high level issues.
Behavioral description can be written with HDLs.

The behavioral description is manually converted to an RTL description in a HDL

. The designer has to describe the data flow that will implement the desired digital circuit.
From this point onwards the design process is done with assistance of Computer Aided
Design (CAD) tools.

Now the functionality and correctness of the behavioral description is verified.

This is called functional simulation. Logic synthesis tools convert the TL description to
gate- level net list. A gate- level net list is a description of the circuit in terms of gates and
connections between them.

6
Design Specification

Behavioral

RTL Description

Functional Description

Logic Synthesis

Gate-level Net list

Logical Verification

Floor Planning
Automatic
Place And Route

Physical Layout

Layout Verification

Implementation

Figure 2.1 typical design flow

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2.4 Popularity of VHDL:
A design engineer in electronic industry uses hardware description language to
keep pace with the productivity of the competitors. With VHDL we can quickly describe
and synthesis circuits of several thousand gates. In addition, provides the capabilities
described as follows.

Power and flexibility:

VHDL has powerful language constructs with which to write succinct code
descriptions of complex control logic. It also has multiple levels of design description for
controlling design implementation. It supports design libraries and creation of reusable
components. It provides design hierarchies to create modular designs. It is one language
for design and simulation.

Device independent device:

VHDL permits to create design without having to first choose a device for
implementation. With one design description, we can target much devices architecture,
without being familiar with it; we can optimize our design for resource utilization or
performance. It permits multiple style of design description.

Portability:
VHDL portability permits to simulate the same design description that we have
synthesized. Simulating a large design description before synthesizing can have
considerable time. As VHDL is a standard, design description can be taken from one
simulator to another, one synthesis tool to another, one platform to another- means design
description can be used in multiple projects.

ASIC migration:
The efficiency that VHDL generates, allows our product to hit the market quickly
if it has been synthesized on a CPLD or FPGA. When production volume reaches
appropriate level, VHDL facilitates the development of Application Specific Integrated
Circuit. Sometimes, the exact code used with the CPLD can be used with the ASIC and
because VHDL is well-defined language, we can assure that our ASIC vendors will
deliver a device with expected functionality.

8
Quick time-to-market and low cost:
VHDL and programmable logic pair well together facilitates a speedy design
process. VHDL permits designs to be described quickly. Programmable logic eliminates
NRE expenses and facilitates quick design iterations. Synthesis makes it all possible
VHDL and programmable logic combine as a powerful vehicle to bring the product in the
market in record time.

2.5 Using VHDL for design synthesis:

The design process can be explained in six steps:
1 Define the design requirements.
2 Describe the design in VHDL (formulate and code the design).
3 Simulate the source code.
4 Synthesize, optimize, and fit the design onto a suitable device.
5 Simulate the post- layout (fit) design mode.
6 Program the device.

Design requirements:
Before launching into writing code for our design, we must have a clear idea of
design objectives and requirements. That is, the function of the design, required setup and
clock- to- output times, maximum frequency of operation and critical paths.

Description of design in VHDL:

(Formulate and design) Having an idea of design requirements, we have to write
an effective code that is realized, through synthesis, to the logic implementation we
intended. Code the design after upon a design methodology, we would code the referring
to the block, data flow, and state diagrams such that the code is syntactically and
semantically correct.

9
 VHDL
Design

Synthesis Software

Net list or
Equations

Filter or Place & Route Routines

Post Report
Layout File:
Test Device
Simulation Resource
Bench or Programming
Model Summary
Other File
(VHDL or Static
Other) Timing

Simulation Software (VHDL or other)

Waveform Data File

Figure 2.2 design requirements in vhdl

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Simulate the source code:
With source code simulation, can be detected early in the design cycle, allowing
us to make corrections with the least possible impact to the schedule. This is more
efficient for large designs, for which synthesis and place and route can take a couple of
hours.

Synthesis:
It is a process by which net list or equations are created from design description,
which may be abstracted. VHDL synthesis software tools convert VHDL description to
technology- specific net lists or set of equations.

Behavioral
Description

Device
Architecture
Selection Flattering of hierarchy
Transformation

Operator inferencing and

Module generation

User applied Device-specific

Directives Optimization

Optimized equations or net list for used

With a filter or place

Figure 2.3 synthesize, optimize and fitting design

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Simulate the post layout design model:
A post layout simulation will enable us to verify, not only the functionality of our
design, but also the timing, such as setup, clock- to- output, and register- to- register
times. If we are unable to meet our design objectives, then we need to either re-
synthesize, and/or fit our design to a new logic device.

Program the device:

After completing the design description synthesizing, fitting, and successfully
simulating our design, we are ready to program our device and continue work on the reset
of our system design. The synthesis, optimization, and fitting software will produce a file
for use in programming the device.

2.6 Writing the test bench:

A test bench is model that is used to exercise and verify the correctness of
hardware model. The expressive power of VHDL language provides us with capability of
writing test bench models in the language. A test bench has three main purposes:

1. To generate stimulus for simulation.

2. To apply this stimulus to the entity under test and collect the output responses.
3. To compare output responses.

2.7 VHDL terms:

The important terms that will be used in VHDL language are:

Entity:

All designs are expressed in terms of entities. An entity is the most building

blocks in a design. The upper most level of design is the top-level entity. If the design is

hierarchical, then the top-level descriptions contained in it. These lower-level

descriptions will be lower-level entities contained in the top level entity description.

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Architecture:

All entities that can be simulated have an architecture description. The

architecture describes the behavior of the entity. A single entity can have multiple

architectures. One architecture might be behavioral. While another might be a structural

description of the design.

Configuration:

A configuration statement is used to bind a component instance to an entity

architecture pair. A Configuration can be considered as a parts list for a design. It

describes which behavior to use for each entity, much like a part in the design.

Packages:

A package is a collection of commonly used data types and subprograms used in a

design. Think of a package as a tool that contains tools used to build designs.

Bus:

The term bus usually brings to mind in a group of signals of particular method of

communication used in a design of hardware. In VHDL a bus is a special kind of signal

that may have its drivers turned off.

Driver:

The driver is a source on signal. If a signal is driven by two tri-state inverters,

when both inverters are active the signal will have two drivers.

Attributes:

An attribute is a data that is attached to VHDL objects are predefined data about

VHDL objects. Examples are the current drive capability of a buffer or the maximum

operating temperature of the device.

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Generic:

A generic is VHDL’s term for a parameter that passes information to an entity.

For instance, if an entity is a gate level model with a rise and fall delay, values for the rise

and fall delays could be passed into the entity with the generics.

Process:

A process is the basic unit of execution in VHDL. All operations that are
performed in a simulation of VHDL description are broken into a single or multiple
processes.

Data types:
In this section we will examine the object types used in VHDL. The types allowed
in VHDL consist of everything from scalar numeric types, to composite arrays and
records, to file types.

Object types:

A VHDL object consists of one of the following:

Signal represents inter connection wires that component instantiation ports together.
Variable is used for local storage of temporary data, visible only inside a process.
Constant names specific values.

Signal:
Signal objects are used to connect entities together to form models. Signals are the
means for communication of dynamic data between entities. A signal declaration looks
like this:

SIGNAL signal _name: signal _type [:=initial _value];

The keyword SIGNAL is followed by one or more signal names. Each signal name will
create a new signal. Separating the signal names from the signal type is a colon. The
signal type specifies the data of the information that the signal will contain an initial
value specifies so that the signal value may be initialized.

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Variables:
Variables are used for local storage in the process statements and subprograms.
As opposed to signals which have their values scheduled, all assignments to variables
occur immediately. A variable declaration looks as follows:
VARIABLE variable_name (variable_name): variable type [:=value];

Constants:
Constant objects are names assigned to specific values of a type. Constants allow
the designer the capability to have a better documented model, and a model that is easy to
update. For instance, if a model requires a fixed value in a number of instances, a
constant should be used. By using a constant the designer can change the value of the
constant and recompile, and all of the instances of the constant value will be up updated
to reflect the new value of the constant.
A constant also provides a better documented model by providing more meaning
to the value being described. For instance, instead of using the value 3.1414 directly in
the model, the designer should create a constant as follows:
CONSTANT P1: REAL: =3.1414;

2.8 Data types:

All of the objectives that we have been discussing until now the signal, the
variable, and the constant can be declared using a type specification to specify the
characteristics of the object. VHDL contains a wide range of types that can be used to
simple or complex objects. A type declaration looks like this:

TYPE type _name IS type _marks;

A type _mark construct encompasses a wide range of methods for specifying a

type. It can be anything for enumeration of all of the values of the type to a complex
record structure. In the next few sections, type marks will be examined.

15
Scalar types:
Scalar types describe objects that can hold, at most one value at a time. Scalar
types encompass these four classes of types:

I. Integer types
II. Real types
III. Enumerated types
IV. Physical types.

Integer types:
Integer types are exactly like mathematical integers. All of the normal predefined
mathematical functions like add, subtract, multiply and divide apply to the integer types.

ARCHITECTURE test OF test IS

BEGIN
PROCESS (X)
VARIABLE a: INTEGER;
VARIABLE b: int _ type;
BEGIN
A: =1; OK1
A: =-1; OK2
A: =1.0; Okerror3
End process;
End rest;

Real types:
Real types are used to declare objects that emulate mathematical real numbers.
They can be used to represent numbers out of the range of integer values as well as
fractional values.

Enumerated types:
An enumerated type is a very powerful tool for abstract modeling. A designer can
use an enumerated type to represent exactly the values required for a specific operation.

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 TYPES

FILES ACCESS COMPOSITE

ARRAY RECORD

SCALAR

ENUMERATE REAL INTEGER PHYSICAL

Figure 2.4 data types

Physical types:
Physical types are used to represent physical quantities such as distance, current,
time etc.

Composite types:
Composite types consist of array and record types. Array types are groups of
elements of the same type, while record types allow the grouping of elements of different
types. Arrays are useful for modeling liner structures such as RAM s and ROM s, while
records are useful for modeling data packets instructions etc.

17
Array types:

Array types group none or more elements of the same type together as a single
object. Each element of the array can be accessed by one more array indices.
In an array, all elements are of the same type. The following example shows a type
declaration for single dimensional array of bits.
TYPE data _bus IS ARRAY (0to31) OF bit; This declaration declares a data
type called data _bus that is an array of 32 bits. Each elements of the array is the same as
the next. Each element of the array can be accessed by an array index.
Record types:
Record types group objects of many types together as a single object. Each object
of the record can be accessed by its field name. Record elements of a record can be of the
same type or declaration types.
An example of a record type declaration is as follows:
TYPE optype IS (add, sub, mul, div, jmp)
TYPE instruction IS
RECORD
Opcode: optype;
Src: INTEGER;
Dst: INTEGER;
END RECORD;
The first line declares the enumerated type optype, which will be used as one of the
record field types. The second line starts the declaration of the record. The record type
declaration begins with the key word RECORD and ends with the clause ENDRECORD.
All of the declarations between these two keywords are field declaration for the record.
Access types:
Most hardware design engineers using VHDL will probably never use access
types directly (a hardware designer may use the text I/O package, which use access types,

18
thereby an indirect use of access types), but access types provide very powerful
programming language like PASCAL or C. It is an address, or handle to a specific object.

File types:
A file type allows declaration of objects that have a type FILE. A file object type
is actually a subset of the variable object type.
File type declaration:
A file type declaration specifies the name of the file type and the base type of the
file. An example of a file type declaration is as follows:
TYPE integer_ file IS FILE OF INTEGER;
This declaration specifies a file type whose name is integer_ file and is as type
INTEGER.

Subtypes:
Subtype declarations are used to define subsets of a type. The subject can contain
the entire range of the base type, but does not necessarily need to. Sub type is defined as
follows:
TYPEINTEGER IS –2,147,483,647 TO +2,147,483,647;
SUBTYPE NATURAL IS INTEGER RANGE 0 TO +2,147,483,647;

After the keyword SUBTYPE is the name of the new being created. The keyword
IS followed by the base type of the subtype. In this example, the base type is the
INTEGER. An optional on the base type is also specified. So, why would a designer want
to create a sub type? There are two main reasons for doing so: To add constraints for
selected signal assignment statements or case statements and create a resolved sub type.

2.9 Behavioral modeling:

The signal assignment statement is the most basic form of behavioral modeling n
VHDL. An example follows: a<b; this statement is read as follows:

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 A gets the value of B. The effect of this statement is that the current value of the
signal B will be assigned to signal A. This statement will be executed whenever signal B
changes value. Signal B is in the sensitivity list of this statement.

Transport versus internal delay:

In VHDL there are two types of delays that can be used for modeling behaviors.
Inertial delay is the most commonly used, while transport delay is used where a wire
delay model is required.

Inertial delay:
Inertial delay is the default is VHDL. If no delay type is specified, then inertial
delay is used. Inertial delay is the default because in most cases it behaves similar to the
actual device. In an inertial delay model, the output signal of the device has inertia, which
must be overcome in order for the signal to change value. The inertia value is equal to
delay through the device. If there are any spikes, pluses etc., that have periods where a
signal value is maintained for less than the delay through the device, the output signal
value will not change. If a signal value is maintained at a particular value for longer than
the delay through the device, the inertia is overcome and the device will change to the
new state.
Transport delay:

Transport delay is not the default in VHDL and must be specified. It represents
a wire delay in which any pulse, no matter how small, it propagated to the output signal
delayed by the delay value specified. Transport delay is especially useful for modeling
delay line devices wire delays on a PC board, and path delays on an ASIC.

Inertial delay buffer waweform:

If we look at the same buffer circuit, replace the inertial delay waveforms with the
transport delay waveforms, we get the result shown in the above figurethe same
waveform is input to signal A, but the output from signal B quire different. With
transport delay, the spike are not allowed, but the events are ordered before propagation.

20
2.10 Sequential statements:
Sequential statements are statements that execut serially, one after the other. Most
programming languages such as C and PASCAL support this type behavior.

Process statement:
In architecture for an entity,all statements are concurrent. There is a statement
called the process statement that contains only sequential statements. The process
statement can exit in architecture and define regions in the architecture where all
statements are sequential. A process statement has a declaration section and a statement
part. In the declaration section,types, variables, constants, subprograms, etc., can be
declared. The statement IF THEN ELSE statements, LOOP statements etc.

Senstivity list:
The process statement can have an explicit sensitivity lst. This list defines the
signals that will cause the statement inside the process statement to execute whenever one
or more elements of the list change value.

Sequential statements:
Sequential statements exist inside the boundares of process statements, as wellas
in subprograms.
The sequential statements that we will discuss are:
IF
CASE
LOOP
ASSERT
WAIT

2.11 Sub program and packages:

Sub programs:
Sub program consist of procedures and functions. A procedure can return more than
one argument, while a function always returns just one. In a function, all parameters and
in out parameter.

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Function:
The most common use for a function is to return a value in an expression;
however, there are two more classes of use available in VHDL. The first is a conversion
function and the second is a resolution function. Conversion functions are used to convert
from one type to another. Resolution functions are used to resolve bus contention on a
multiply driven signal.

Procedure:
The procedure can have any number of in, out and in out parameters. A
procedure call is a considered a statement of its own, while a function usually exists as
part of an expression. The most usual case of procedure is when more than one value if
returned.Procedures have basically the same syntax and rules as functions. A procedure
declaration begins with the keyword PROCEDURE, followed by the procedure name, the
procedure argument list will most likely have a direction associated with each parameter,
while the function argument list does not. In a procedure, some of the arguments can be
mode IN, OUT or INOUT, while in a function all arguments mode IN by default and can
be only of mode IN.

Package:
The primary purpose of a package is to encapsulate elements that can be shared
(globally) among two or more design units. A package is a common storage area used to
hold a data to be shared among number4 of entries. Declaring data inside of a package
consists of two parts: a package declare section and a package body. The package
declaration defines the interface for the package, much the same way that entity designs
the interface for a model. The package body specifies the actual behavior of the package
in the same method that the architecture state does for a model.

Configuration:
Configurations are a primary design unit used to bind components instances to
entities. For structural models, configurations can be thought of as the parts list for the
model. For component instances, the configuration will specify from much architecture

22
for an entity architecture combination is compiled into the library, a simulatable object is
created.
Syntax:
Configuration config _ name OF entity_ name IS
FOR arch1
FOR com1:com_name USE WORK.Arch_name
END FOR;
END CONFIGURATON;

2.12 System software:

The Active VHDL provides integrated VHDL tools over wide range of
applications. The active VHDL framework is based on a standard MFC-like GUI
interface. Each window can be dock able, overlapped or application-like. The main parts
of the Active-VHDL are:

Design browser
HDL editor
Console window
Waveform window

In Active-VHDL one can specify the contents or the design he is creating, one can:

Create new components-this will create new files containing the specified entities Add
existing file-existing VHDLnetlist generated by ALDEC’S ACTIVE CAD and be
imported.
Create blank design-none of components will be added to the design. Active-
VHDL provides a dialog that allows user to choose the type of the port. Chose the STD
LOGIC option for single ports and STD-LOGIC-VECTOR for buses. This will cause the
generated template to have IEEE library and packages declarations. The design browser
is window showing the design contents. As a result of the prious operations you will
receive the following:

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Editing code:
The HDL editor is a text editor with VHDL keywords coloring and standard editing
features.

Language assistant helps choosing the appropriate the options from the tools menu. We
have the following templates in the language assistant.
Templates:
• Language templates
• Simulation templates
• Synthesis templates
• Training
• Tutorial
• User templates

The edit requires some additional packages to be included. For example, the following
line has to be added after the USE IEEE.STD_LOGIC_1164.ALL.
Use IEEE.std_logic_unsigned.ALL;

Simulation:
To begin a simulation, we have to first initialize the simulator using the initialize
simulation option from the simulation menu. AFTER the simulator has been initialized,
we have to open a new waveform window. Signal for simulation can be added using the
drag and drop feature.

Library manager:
Each VHDL source file is compiled to the specified library. The default library for
the design files has the same name as the design name and is displayed on the files tab of
the design browser window, in the hierarchy tree.VHDL files can be compiled to any
existing, which can be selected using the file properties dialog. To change the default
library for the compilation output, we have to switch over to the compile tab. Since the
VHDL language supports packages, each of then can be compiled to a different library.
We can use libraries and their contents using the library manager window, which is

24
opened when the library manager option is selected from the view menu.The following
window shows the library manager item.

Orca Functional components library for luc.

Primitive Post P&R timing simulation library for C.

Qlogic_functional Functional component library for Qui.

Qlprims Post P&R timing simulation library.

Simprim Functional components library for xilinx.

Std Standard VHDL library.

Synopsis training Library containing packages with usef.

Unisim Functional components library for xilinx.

Xu Functional components library for Xilinx.

25
 CHAPTER 3
INTRODUCTION TO UART

3.1 Introduction:
The Universal Asynchronous Receiver/Transmitter (UART) controller is the key
component of the serial communications subsystem of a computer. The UART takes
bytes of data and transmits the individual bits in a sequential fashion. At the destination, a
second UART re-assembles the bits into complete bytes.

Serial transmission is commonly used with modems and for non-networked

communication between computers, terminals and other devices.

There are two primary forms of serial transmission: Synchronous and

Asynchronous.

Synchronous serial transmission:

Synchronous serial transmission requires that the sender and receiver share a
clock with one another, or that the sender provide a strobe or other timing signal so that
the receiver knows when to “read” the next bit of the data. In most forms of serial
Synchronous communication, if there is no data available at a given instant to transmit, a
fill character must be sent instead so that data is always being transmitted. Synchronous
communication is usually more efficient because only data bits are transmitted between
sender and receiver, and synchronous communication can be more costly if extra wiring
and circuits are required to share a clock signal between the sender and receiver.A form
of Synchronous transmission is used with printers and fixed disk devices in that the data
is sent on one set of wires while a clock or strobe is sent on a different wire. Printers and
fixed disk devices are not normally serial devices because most fixed disk interface
standards send an entire word of data for each clock or strobe signal by using a separate
wire for each bit of the word. In the PC industry, these are known as Parallel devices.The
standard serial communications hardware in the PC does not support Synchronous
operations. This mode is described here for comparison purposes only.

26
Asynchronous serial transmission:
Asynchronous transmission allows data to be transmitted without the sender
having to send a clock signal to the receiver. Instead, the sender and receiver must agree
on timing parameters in advance and special bits are added to each word which are used
to synchronize the sending and receiving units.

When a word is given to the UART for Asynchronous transmissions, a bit called
the "Start Bit" is added to the beginning of each word that is to be transmitted. The Start
Bit is used to alert the receiver that a word of data is about to be sent, and to force the
clock in the receiver into synchronization with the clock in the transmitter. These two
clocks must be accurate enough to not have the frequency drift by more than 10% during
the transmission of the remaining bits in the word. (This requirement was set in the days
of mechanical tele-printers and is easily met by modern electronic equipment) .

After the Start Bit, the individual bits of the word of data are sent, with the Least
Significant Bit (LSB) being sent first. Each bit in the transmission is transmitted for
exactly the same amount of time as all of the other bits, and the receiver “looks” at the
wire at approximately halfway through the period assigned to each bit to determine if the
bit is a 1 or a 0. For example, if it takes two seconds to send each bit, the receiver will
examine the signal to determine if it is a 1 or a 0 after one second has passed, then it will
wait two seconds and then examine the value of the next bit, and so on.

The sender does not know when the receiver has “looked” at the value of the bit.
The sender only knows when the clock says to begin transmitting the next bit of the
word. When the entire data word has been sent, the transmitter may add a Parity Bit that
the transmitter generates. The Parity Bit may be used by the receiver to perform simple
error checking. Then at least one Stop Bit is sent by the transmitter.

When the receiver has received all of the bits in the data word, it may check for
the Parity Bits (both sender and receiver must agree on whether a Parity Bit is to be
used), and then the receiver looks for a Stop Bit. If the Stop Bit does not appear when it is
supposed to, the UART considers the entire word to be garbled and will report a Framing

27
Error to the host processor when the data word is read. The usual cause of a Framing
Error is that the sender and receiver clocks were not running at the same speed, or that the
signal was interrupted.

Regardless of whether the data was received correctly or not, the UART
automatically discards the Start, Parity and Stop bits. If the sender and receiver are
configured identically, these bits are not passed to the host. If another word is ready for
transmission, the Start Bit for the new word can be sent as soon as the Stop Bit for the
previous word has been sent.

Because asynchronous data is “self synchronizing”, if there is no data to transmit,

the transmission line can be idle.

Figure 3.1: Block Diagram of UART

28
3.2 Transmitter module:
The serial transmitter section consists of an 8-bit Transmitter Hold Register
(THR) and Transmitter Shift Register (TSR). There are two ways to indicate the status of
THR: an independent TxRDY output pin or the THRE flag in the Line Status Register
(LSR). When the THR is empty, pin TxRDYn will be low active, and the THR empty
flag in LSR will be set to logic 1. Only when the THR is empty, can a write operation be
performed to transfer the data from CPU to THR without trashing the previous data.
After the data is loaded in THR, the THR empty flag in LSR will be reset to logic 0, and
pin TxRDYn will go inactive high.

The serial data transmission will be automatically enabled after the data is loaded
into THR. First a Start bit (logic 0) is transmitted and the data in THR is parallel loaded
to TSR automatically. Then the Data bits will be shifted out of TSR with certain word
lengths defined in Line Control Register (LCR) followed by the Parity bit if parity is
enabled. Finally, the Stop bit (logic 1) is generated to indicate the end of the frame. This
serial data frame (Start bit + Data bits + Parity bit + Stop bit) will be transmitted at the
rate of 1/16 of Clk16X frequency. After a frame is fully transmitted, another frame will
be transmitted immediately if THR is not empty (due to a THR write occurring during the
first frame of transmission). This automatic sequencing cause the frames to be
transmitted back-to-back which increases the transmission bandwidth. When no
transmission is taking place, the SOUT pin is held in the high state.

The transmitter block is responsible for the transmission of serial data from
UART. It takes 8-bit data from the transmit register and sends it to output in serial form.
The data is accompanied by start and stop bits. An optional parity bit also may be used
for error detection. The state machine for transmitter is shown in Fig. 3.2. The transmitter
stays in IDLE state unless transmit enable (tx_enable) is made as ‘1’. The data
transmission starts with tx_enable = 1. As mandated by the protocol, a ‘0’ is transmitted
to indicate start of transmission or start bit. This is done in START state. Then data bits 0
to 7 are transmitted in states DATA0 to DATA7. If parity is enabled in configuration
register, the data is attached with a parity in PARITY state. Then transmitter enters STOP

29
state and sends a ‘1’. This indicates the completion of transmission. Then the transmitter
enters the IDLE state and waits for next data transmission.

Figure 3.2 : state machine for transmitter

3.3 Receiver module:

The serial receiver section also contains an 8-bit Receiver Buffer Register (RBR)
and Receiver Shift Register (RSR). The status of RBR can be provided by either
independent pin RxRDYn or the Receiver Data available flag (DR) in LSR.

Since the serial frame is asynchronous to the receiving clock, a high to low
transition of SIN pin will be treated as the Start bit of a frame. However, in order to avoid
receiving a incorrect data due to SIN signal noise, the False Start Bit Detection feature is
implemented in the design which requires the Start bit to be low at least 50% of the
receiv- ing baud rate clock cycle. Since the internal clock Clk16X is 16 times the
receiving/transmitting baud rate clock fre- quency, the Start bit needs to be low at least 8
Clk16X clocks to be considered as a valid Start bit.

30
 Once a valid 8 Clk16X clocks Start bit is received, the Data bits and Parity bit
will be sampled every 16 Clk16X clocks (the receiving baud rate). If the Start bit is
exactly 16 Clk16X clocks long, each of the following bits will be sampled at the center of
the bit itself. LSR will be updated to show the received frame status when any of the line
errors (Overrun error, Parity error, Framing error, Break) is detected.

Whenever the Framing error is detected, the UART assumes that the error was
due to the Start bit of the following frame and tries to resynchronize it. To do this, it
samples the Start bit twice based on the Clk16X clock. If both sam- ples of the SIN are
low, the UART will take in the following frame’s Data bits after the 8 Clk16X clocks
Start bit is sampled. The resynchronization will not occur for the Framing error caused by
the Break. When the data is available in RBR, the RxRDYn will be low active, and the
Receiver Data available flag (DR) in LSR will be set to logic 1 to inform the CPU that
the data is ready to be read.

UART receiver handles the reception of data from RS232 port. The main
functions of receiver block are to convert the serial data to parallel data, check the
correctness of data from parity and store the received data in receive register in register
block. UART receiver state machine is shown in Fig. 4-7. The receiver is in IDLE state
by default. When the serial data pin goes low, indicating the start bit, the state machine
enters DATA0 state. The data is received; one bit at a time from LSB to MSB in states
DATA0 to DATA7. If parity is enabled, the state machine checks the parity bit received
against the parity obtained from received data. If the data received is fine, the data_rx
(data_rx_done) bit is set to ‘1’ and the receiver goes back to IDLE state again.

Start bit detection:

The receiver uses a 16X clock timing. The start bit could have occurred as much
as one clock cycle before it was detected, as indicated by the shaded portion (A). The
center of the start bit is defined as clock count 7 1/2. If the receiver clock is a
symmetrical square wave, the center of the start bit will be located within 1/2 clock
cycle, 1/32 bit or 3.125% giving a receiver margin of 46.875%. The receiver begins
searching for the next start bit at the center of the first stop bit.

31
Figure 3.4: state machine for receiver

3.4 Register block:

The register block contains 4 registers namely transmit register, receive register,
configuration register and clock division register. The bit assignments are shown in Fig.
3.4. These register are programmed by external host processor.

32
 In order for the UART to properly operate in a system, it must be configured for
the desired form of operation. The user must decide how the device will be used in the
system, and know the communications protocol of the device it will be communicating
with. For example, in a system communicating with a modem we would need to utilize
the modem control lines. When using the UART in a local area network these modem
control lines may be of no use to us.

The UART is initialized and configured by writing a series of control words from
the CPU to various control registers in the device. These registers include the UART
Control Register (UCR), the Baud Rate Selector Register (BRSR), and the Modem
Control Register (MCR).

UCR: Defines the format of characters being transmitted. The format of the
characters includes the number of data bits, parity control, and the number of stop bits.

BRSR: Used in setting up the internal baud rate generator in the UART for a
specific baud rate. It will also be used to specify what the CO output is to be.

33
 MCR: Defines which interrupts will be enabled, and will also set the modem
control output lines (RTS and DTR).

In addition, the MCR allows the user to select one of four modes of
communications (normal mode, echo mode, transmit break, and loop test mode).

3.4.1 UART Control register:

The UART Control Register (UCR) is a write-only register. Writing a command
word to the UCR configures the transmission and reception circuitry. The command word
essentially describes the format of characters that are to be transmitted or received. The
format of these characters are made up of (1) a specific word length, (2) parity
information, and (3) a selected number of stop bits, used to indicate transmission of that
character is completed.

D0 – Stop Bit Select. This bit is used to select the number of stop bits that the
82C52 will insert into a character to be transmitted, and the number to look for in
received characters. The stop bit(s) denote where the end of a character occurs. The
external device must be configured with the same number of stop bits. The setting(s) for
this bit are as follows:

0 – If this bit is set to zero, then a single stop bit will be generated and
checked for.
1– Setting this bit to a one will cause either of two configurations.
If we select a character length of 5 data bits, the UART will generate 1.5 stop bits
during transmission, and will look for a single stop bit when receiving data. If a character
length of 6, 7, or 8 data bits is selected, then two (2) stop bits will be generated and
checked for.

D3, D2 and D1 – Parity Control. These three bits are used to control the
generation and checking of the parity bit. The UART can be configured to perform this
function one of seven ways. These are:

000 – Even parity is generated for transmitting data, and will be checked for when
receiving data.

34
 001 – Odd parity is generated for transmitting data, and checked for during data
reception.
010 – Even parity is generated for data transmission, and odd parity will be
checked for during data reception.
011 – Odd parity is generated for data transmission, and even parity will be
checked for during data reception.
100 –Even parity is generated for data transmission, however, the 82C52 will do
no parity checking on data that has been received.
101 – Odd parity is generated for data transmission. The UART will not check
parity on data received.
11X – The generation of a parity bit is disabled. Also, the UART will not check
for parity on incoming data. D1 is not used therefore, it can be either a 0 or a 1.

3.4.2 Baud rate select register:

The Baud Rate Select Register (BRSR) is a write-only register used to set the
internal UART baud rate generator to the desired data transfer rate. Essentially, this baud
rate will depend upon the clock speed of the crystal being used with the device. However,
to provide more flexibility, the UART provides two separate counters for selecting a
divide ratio to fit the user’s needs.

These two counters are the Pre-scaler, and the Divisor select. The Pre-scaler
allows the input clock rate to be divided by one of four values: 1, 3, 4, and 5. this new
data rate can then be further divided by using the values available with the Divisor select.
This final clock speed will be 16 times the actual baud rate used by the UART.

The 16X clock speed can be output to the CO pin of the device through the CO
Select function of the BRSR. If CO select is not selected, the output of the CO pin will
reflect the crystal frequency input by the part on the IX pin. Note, this output (CO) is a
buffered version of the IX input or 16X baud rate.

35
3.4.3 Modem control register:
The Modem Control Register (MCR) is a general purpose register controlling
various operation parameters within the device. These parameters include: (1) setting
modem control lines RTS and DTR, (2) Enabling the interrupt structure of the device, (3)
enabling the receiver on the device, and (4) selecting one of four operating modes in the
device.

Figure 3.5: MCR Mode Selection

D0 – Request to Send. This bit allows the user to set the state of the RTS output
pin. This pin is used as a modem control line in the RS-232C interface protocol. It is
important to remember that the RTS output pin is active low.

0 – Setting this bit to a zero causes a one (1) to be output on the RTS pin. In effect, this is
setting the pin to its logical false state.

36
1 – If this bit is set to a one, the RTS pin will be forced to a zero (0). This puts the RTS
signal in its logical true state.

D1 – Data Terminal Ready. This is a modem control line for an RS-232C- like
interface. It is an output pin and is also active low.

0 – A zero in bit D1 causes DTR pin to be put in a logical false state. The DTR pin
outputs a one (1).

1 – By writing a one to this bit, the 82C52 DTR output pin is set to its logical true state
(zero).

D2 – Interrupt Enable (INTEN). This bit is an overall control for the INTR pin
on the 82C52. With it, all 82C52 interrupts to the processor can either be enabled or
disabled. When D2 is reset to disable interrupts, no status changes including modem
status changes can cause an interrupt to the processor.

0 – Interrupts are disabled. The INTR pin will be held in a false state (low) so that no
interrupt requests to the processor are generated.

1 – Interrupts are enabled. Interrupts will be discussed in more detail later.

D4 and D3 – Mode Select. These two bits allow the user to select one of the four
possible operating modes for the UART are:

00 – Normal mode - The 82C52 is configured for normal full or half duplex
communications. Data will not be looped back in any form or fashion between the serial
data input pin and the serial data output pin (see Figure 6A).

01 – Transmit break - Selecting this mode of operation will cause the transmitter to
transmit break characters only. A break character is composed of all logical zeros for the
start, data, parity, and stop bits.

37
10 – Echo mode - When this is selected, the 82C52 will retransmit data received on the
SDI pin out to the SDO pin. In this mode of operation, any data written to the Transmitter
Buffer Register will not be sent out on the SDO pin.

11 – Loop Test mode - If this mode is selected, the data that normally would be
transmitted is internally routed back to the receiver circuitry. The transmitted data will
not appear at the SDO pin. Also, data that is received on the SDI pin will be ignored by
the device. This mode of operation is useful for performing self test(s) on the device.

Figure 3.6: Modes of Operation

3.4.4 Status register:

In addition to the various Control registers, the UART has two read only status
registers that can be accessed by the CPU to determine the status of the device at any
given time. These are the UART Status Register (USR), and the Modem Status Register

38
(MSR). The registers are used for keeping track of any changes in (1) the modem lines on
the device (2) the status of data transmission or reception, and (3) whether any error(s)
were detected in received data.

The USR deals with the different types of data errors, the status of data
transmission, as well as data waiting to be read. The MSR, on the other hand, reflects the
status of the various modem control lines in the device (i.e. CTS and DSR). Normally, in
an interrupt-driven system, after an interrupt occurs, the user’s software would check the
status register(s) to determine what caused the interrupt. The software then should deal
with the various types of interrupts in an appropriate manner.

The UART Status Register (USR) contains information pertaining to the status of
the UART operation. The information that is kept in the USR includes: data reception
error information, modem status, and the status of data transmission. This register will
normally be the first UART register read when servicing an UART interrupt, or when
polling the device.

3.4.5 Transmit/receive buffer register:

In addition to the control and status registers, the UART has two buffer registers
that allow for the actual serial communications to be performed. These registers are used
for sending characters out to the SDO pin, and for reading data from the SDI pin.

Re4ceiver buffer register:

The Receiver Buffer Register (RBR) is a read-only register which contains the character
received via the SDI pin. When data is received by the UART, it is read serially into the
Receiver Register from the SDI pin, and then transferred to the RBR for the CPU’s
access. This double buffering allows for higher transmission rates without loss of data.
However, should additional characters are received by the UART before this register is
read, then the Receiver Register will be overwritten with the subsequent characters. This
will cause the Overrun Error (OE) flag to be asserted. The RBR is 8-bits long and can
accept data lengths of 5 to 8-bits. The data will be right justified in the register. When
Selecting data lengths of less than 8-bits, the UART will insert zeros (0) into the RBR for

39
the unused (most significant) bits. For example, if the UART is configured for 6 data bits,
and the character 31H is received, the RBR will look as follows when read:

Figure 3.7: Received DATA

Figure 3.8 : RBR Format DATA

Transmitter buffer register:
The Transmitter Buffer Register (TBR) is a write only register used for sending
characters out through the SDO pin. Characters to be transmitted should only be written
to this register when it is empty. This condition can be checked for by reading the UART
Status Register (USR) TBRE bit, or waiting for an interrupt to signal this condition. Like
the Receiver circuitry, the Transmitter also uses double buffering. Here, we are taking
advantage of the double buffering to increase throughput with the UART. The user would
first write a character to the TBR. From here it is shifted (in parallel) into a second
register known as the Transmit Register. After this transfer has been completed, the
TBRE bit is set.

The character shifted into the Transmit Register is then shifted serially out onto
the SDO pin. Meanwhile, because the TBR is empty, another character can be written by
the CPU to the TBR. In effect, the transmitter circuitry is then performing two operations

40
simultaneously. This double buffering technique allows continuous data flow
transmission.

The Transmit Buffer Register is also 8-bits wide. Because we can specify data
lengths as being from 5 to 8-bits wide, the 82C52 right justifies the data when it is written
to the TBR, and fills the unused bits with zero’s. In other words, unused (most
significant) bits are truncated. For example, if we set up the device so that 6 data bits are
specified and we write the character 71H (01110001 b) to the TBR, we will effectively be
transmitting the character:

Figure 3.9 : Transmitted DATA

Figure 3.10: TBR DATA Format

3.5 Parity generator:

Parity generator generates even or odd parity for the input data bits. By default,
even parity is generated. Odd parity needs to be enabled by setting bit (3) of
configuration register to ‘1’.

Parity is a form of error detection commonly used in serial communications. In

parity checking, the sending device generates and sends an extra bit with each character

41
transmitted. The state of this bit (0 or 1) is determined by (1) the number of 1 bit in the
character transmitted, and (2) by whether parity was defined to be even or odd. With even
parity, the parity bit is generated such that the number of one’ bits in the character
(including the parity bit) is an even number. For example, if a word has 5-bits that are
ones, the parity bit must be set to a one so that the total number of ‘one’ bits is an even
number. If a character being sent has 6-bits set to a one, the parity bit will be zero. This
still gives an even number of one bits in the character.

Conversely, in odd parity, the parity bit is generated such that the total number of
1 bit (including the parity bit) is an odd number. For a character having 5 one bits, the
parity bit generated is a zero. For a character having 6 one bits, the parity bit is set to one.

The Parity error caused by an invalid parity bit being detected in a character
received. The condition occurs when (A) even parity is specified and an odd number of
‘one’ bits are detected in the character, or (B) odd parity is specified and an even number
of ‘one’ bits are detected. For example, if the character 6EH (01101110 b) is received by
the device, and the parity bit read in is a 1, a parity error would be flagged if parity was
defined to be ODD. Should parity be set to EVEN and the parity bit is a 1 for this same
character, a parity error will not be flagged.

3.6 Clock divider:

The clock divider block is useful in setting the required baud rate in UART.
Based on value of input clock frequency and required baud rate, appropriate value of
clock division is used.

Clock division value = (Input clock frequency) / (Required baud rate)

42
 CHAPTER 4

FPGA IMPLEMENTATION

4.1 FPGA Implementation flow diagram:

Initially the market research should be carried out which covers the previous
version of the design and the current requirements on the design. Based on this survey,

43
the specification and the architecture must be identified. Then the RTL modelling should
be carried out in VHDL with respect to the identified architecture.

Once the RTL modelling is done, it should be simulated and verified for all the
cases. The functional verification should meet the intended architecture and should pass
all the test cases.

Once the functional verification is clear, the RTL model will be taken to the
synthesis process. Three operations will be carried out in the synthesis process such as

Translate
Map
Place and Route

The developed RTL model will be translated to the mathematical equation format
which will be in the understandable format of the tool. These translated equations will be
then mapped to the library that is, mapped to the hardware. Once the mapping is done,
the gates were placed and routed. Before these processes, the constraints can be given in
order to optimize the design. Finally the BIT MAP file will be generated that has the
design information in the binary format which will be dumped in the FPGA board.

4.2 Introduction to FPGA:

FPGA stands for Field Programmable Gate Array which has the array of logic
module, I /O module and routing tracks (programmable interconnect). FPGA can be
configured by end user to implement specific circuitry. Speed is up to 100 MHz but at
present speed is in GHz.

Main applications are DSP, FPGA based computers, logic emulation, ASIC and
ASSP. FPGA can be programmed mainly on SRAM (Static Random Access Memory). It
is Volatile and main advantage of using SRAM programming technology is re-
configurability. Issues in FPGA technology are complexity of logic element, clock
support, IO support and interconnections (Routing).

44
 In this work, design of a UART is made using VHDL and is synthesized on
FPGA family of Spartan 3E through XILINX ISE Tool. This process includes following:

Translate
Map
Place and Route

4.3 FPGA flow:

The basic implementation of design on FPGA has the following steps.
Design Entry
Logic Optimization
Technology Mapping
Placement
Routing
Programming Unit
Configured FPGA

Above shows the basic steps involved in implementation. The initial design entry
of may be VHDL, schematic or Boolean expression. The optimization of the Boolean
expression will be carried out by considering area or speed.

Figure 4.2 Logic Block

45
 In technology mapping, the transformation of optimized Boolean expression to
FPGA logic blocks, that is said to be as Slices. Here area and delay optimization will be
taken place. During placement the algorithms are used to place each block in FPGA
array. Assigning the FPGA wire segments, which are programmable, to establish
connections among FPGA blocks through routing. The configuration of final chip is
made in programming unit.

4.4 Synthesis result:

The developed UART, is simulated and verified their functionality. Once the
functional verification is done, the RTL model is taken to the synthesis process using the
Xilinx ISE tool. In synthesis process, the RTL model will be converted to the gate level
netlist mapped to a specific technology library. Here in this Spartan 3E family, many
different devices were available in the Xilinx ISE tool.

46
4.4.1DEVICE UTILIZATION SUMMARY:

This device utilization includes the following.

• Logic Utilization
• Logic Distribution
• Total Gate count for the Design
The device utilization summery is shown above in which its gives the details of
number of devices used from the available devices and also represented in %. Hence as
the result of the synthesis process, the device utilization in the used device and package is
shown above.

47
4.4.2 TIMING SUMMARY:

Speed Grade: -4
Minimum period: 5.953ns (Maximum Frequency: 167.983MHz)
Minimum input arrival time before clock: 4.537ns
Maximum output required time after clock: 5.919ns
Maximum combinational path delay: No path found

In timing summery, details regarding time period and frequency is shown are
approximate while synthesize. After place and routing is over, we get the exact timing
summery. Hence the maximum operating frequency of this synthesized design is given as
167.983MHz and the minimum period as 5.953ns. Here, OFFSET IN is the minimum
input arrival time before clock and OFFSET OUT is maximum output required time after
clock.

4.4.3 RTL SCHEMATIC:

The RTL (Register Transfer Logic) can be viewed as black box after synthesize of
design is made. It shows the inputs and outputs of the system. By double-clicking on the
diagram we can see gates, flip-flops and MUX.

48
 IN O
P U
U TP
TS U
TS

Figure 4.3: UART SCHEMATIC WITH BASIC INPUTS AND OUTPUT

Here in the above schematic, that is, in the top level schematic shows all the
inputs and final output of UART design.

Figure 4.4: BLOCKS INSIDE THE DEVELOPED TOP LEVEL UART DESIGN

49
 The internal blocks available inside the design includes parity generator, clock
divider, register block, transmitter and Receiver which were clearly shown in the above
schematic level diagram. Inside each block the gate level circuit will be generated with
respect to the modelled HDL code.

CHAPTER 5

RESULTS AND CONCLUSIONS

5.1 Simulation outputs of UART

50
 Figure 3.1 UART top level waveforms

Fig. 3.1 shows UART top level waveforms. The waveforms show serial data
output from the UART on sout. Since the data is feedback, the same data can also be seen
on sin. Here transmitter, receiver and parity are enabled as shown.

5.2 UART Transmitter:

51
 Figure 3.2 UART transmitter waveforms

Figure 3.2 shows the waveforms of the UART transmitter. The present_state
indicates the current state of the state machine. It traverses from IDLE to STOP state. The
data input can be seen on din and corresponding serial output is given on sout. Since
parity_en = 1, parity bit is appended to data.

5.3 UART Receiver:

Figure 3.3 UART receiver waveforms

Fig. 3.3 shows the receiver waveforms. The state transitions are similar to
transmitter. The serial data input comes on sin and output data is dout. The data is
sampled when data_rx_done = ‘1’.
5.4 UART Register block:

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 Figure 3.4 Waveforms for register block

Figure 3.4 shows the waveforms of the register block. As per our test bench, different
values are written to transmit register (tx_reg), receive register (rx_reg), configuration
register (config_reg) and clock division register (clock_div_reg).

5.5 Parity generator:

Figure 3.5 Waveforms of pariy generator

Fig. 3.5 shows the waveforms of parity generator. Depending on the odd_even_parity,
odd (if odd_even_parity = ‘1’) or even (if odd_even_parity=’0’) parity is generated. The
parity_rx bit corresponds to receiver data (din_rx) and parity_tx corresponds to
transmitter data (din_tx).

5.6 Clock divider:

Fig. 3.6 shows the waveforms of clock divider. Depending on the clock division
value (clock_div_value), the input clock is divided as shown in below waveform.

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 Figure 3.6 Waveforms of clock divider

5.7 Conclusion
The receiver interfaces to the data bus dout [7:0] with the Read signal. The
controller can generate a read strobe if data ready is true. The receiver is double buffered,
allowing data to be held in the buffer register rbr [7:0] while data is shifted in serially into
the receiver shift register rsr [7:0]. This provides the controller flexibility with bus read
operations. The receiver detects the character frame and strips the start and stop bits. The
no_bits_rcvd variable controls the word size.

The clkdiv[3:0] register is used to control the time at which the data is decoded.
The receiver uses the 16x local clock and decodes the value of start, data, and stop nits in
the center of the data cells. To do this, the start bit initializes a count operation using
clkdiv[3:0]. After detecting the low going edge on the start bit, the receiver counts the
16x clock to 8 and decodes, or samples the value of the signal. The clkdiv[3:0] register is
then reset to 0, and subsequently counts the 16x clock to 16. This provides center
sampling for the data and stop bits.
Three error detection signals are commonly used in UARTs. Parity Error indicates
whether an even or odd number of "1s" are present in a data work. Overrun Error

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indicates whether the receive buffer register is overwritten by the receive shift register
prior to the controller reading the receiver buffer register. Overrun Error is not
implemented in the VHDL source.

The transmitter interfaces to the data bus with the transmitter buffer register
empty (tbre) and the wrn signals. The controller can generate a wrn strobe if tbre is
high. The transmitter is double buffered, allowing data on din’7:0] to be written to the
buffer register tbr[7:0] while data is being shifted out of the shift register tsr[7:0]. The
transmitter generates a frame which consists of the idle state (high on sdo), low start bit,
eight data bits, and a stop bit.

REFERENCES
Ben Cohen, “VHDL Coding styles and methodologies” , 2nd edition.

Volnei A. Pedroni, “Circuit Design with VHDL”, 4th edition, 2004.

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R.S Goanker , “Microprocessor architecture, programming & applications” 3rd edition.

Douglas V Hall, “ Microprocessor and interfacing” , 2nd edition

Z.Novabi, “ Vhdl analysis and modeling of digital system”, 3rd edition

-
Websites:
1.http://www.vhdlonline.com
2.http://www.exar.com
3.http://www.altavista.com
4.http://www.intel.com

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