Proceedings of The National Conference

On Undergraduate Research (NCUR) 2005

Washington and Lee University
Virginia Military Institute
Lexington, Virginia
April 21 - 24, 2005

A Study of the Body Effect in nMOS Enhancement Mode Transistors

Wei-Han Jeng, and Kanchanadet Banchusuwan
Department of Electrical and Computer Engineering
Virginia Military Institute
Lexington, VA 24450. USA

Faculty Advisor: Dr. J. Shawn Addington

Abstract
MOSFET devices are characterized by a threshold voltage, which determines when the device is “on” or “off” in
digital logic gate applications. A variation of this threshold voltage, caused by changes in the base to source voltage,
can have significant effects on the design and performance of these digital logic gates. This variation is called the
body effect. This study involves an evaluation of the body effect in the nMOS enhancement mode transistors. First,
several transistor structures were designed and fabricated, following the procedures established in a previous study.
Then, the researchers performed an investigation of the extent of the body effect for each of these structures under
varying test conditions, and demonstrated how this effect is significant in digital logic gate design.
Keywords: nMOS, Body effect, Semiconductor

1. Introduction
The project is based on a specific characteristic of n-channel enhancement MOSFET (nMOS) devices, known as
body effect. As an extension of work that was started last year [1], this research investigates how non-zero source-
base voltages (VSB) influence the operational characteristics of these devices. Due to the different condition of the
base voltage, the cascaded nMOS transistors (logic gates) perform differently. Specifically, the voltage required to
“trigger” (turn on or off) these logic gates is significantly altered by the presence of body effect in the transistors.
Since nMOS logic design requires the use of varying transistor sizes for proper functionality, this project also
includes an evaluation of multiple nMOS transistor structures (of varying size) in order to better understand the
extent of body effect on such structures. Such data will assist in improving the performance of these logic devices by
incorporating the body effect in the design process.

2. nMOS Technology

2.1 device structure and layout [1]

Figure 1 is the schematic, edge view, and top view of a nMOS device. nMOS enhancement mode devices may
operate as switches by applying a gate (G) voltage to modulate (open and close) the channel between the source (S)
and drain (D) regions. When the difference between gate and source voltage (VGS) is more positive than the
threshold voltage (VT), an inversion layer (p-type material converted to n-type) is created under the gate that
completes the channel and allows current (ID) to flow through the circuit (Figure 2). Non-zero source-base voltages
(VSB), common in certain digital designs, result in changes in this threshold voltage, as shown in Figure 3.
 Figure 1 Different views of nMOS device

2.2 threshold voltage and body effect

Figure 2 shows the ideal transfer characteristic curve between ID and VGS. The important information gained from
this curve is the threshold voltage (VT), which is the voltage necessary to turn the device “on.”

Figure 2 Transfer characteristic of nMOS transistor

Figure 3 shows the ideal transfer characteristic curve for different values of VSB. Due to the body effect, changes in
the source-base voltage result in changes in the threshold voltage.

Figure 3 Transfer characteristic of nMOS transistor with body effect

2.3 nMOS transistor design

The design of the nMOS transistor is based on references [2,3]. The design of nMOS transistor size is based on the
design from an earlier study [4].

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3. Test
Transistors of multiple sizes are characterized under different test conditions in order to see the extent of the body
effect. The transistors are biased in the saturation region by shorting the gate to the drain and applying a drain
voltage of 5 volts. The transfer characteristics (ID vs VGS) of each transistor are then measured for different values of
VSB. These data result in two analyses – the changes in VT with VSB (body effect), and the influence of transistor size
on the body effect.

4. Results
The devices on the wafer are labeled into 12 positions. There are 2 or 3 devices in each position. These positions are
shown as Figure 4:

a b

Figure 4 Device orders on single wafer; a: Device orders, b: Final product

Table 1 is the ratio (W/L) of nMOS transistor gate regions. The ratio determines the size of the transistor for our
study.

Table 1 Ratio of gate region

Transistor W (unit) L (unit) W/L
1&7 a 4 18 0.22
b 12 4 3
2&8 a 4 18 0.22
b 12 4 3
3&9 a 4 26 0.15
b 10 4.5 2.22
c 10 4 2.5
4 & 10 a 4 26 0.15
b 10 4.5 2.22
c 10 4 2.5
5 & 11 a 4 34 0.12
b 10 3.5 2.86
c 12 3.5 3.43
6 & 12 a 4 34 0.12
b 10 3.5 2.86
c 12 3.5 3.43

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4.1 data
Figures 5, 6, and 7 are the transfer characteristic curves (ID vs VGS) under different source-base voltages (0V to 5V).
We establish an “on-current” level of 0.07 mA. The intersections of the x- axis and the curves provide an estimate of
the threshold voltage (VT).

ID vs.VGS 9c

0.52

0.47

0.42

0.37
Vsb=0
I (mA)

0.32 Vsb=1

0.27
Vsb=2
Vsb=3
0.22

0.17

0.12

0.07
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 3.75 4 4.25 4.5

V GS (V)

Figure 5 Transfer characteristic curves for the device 9c

ID vs. VGS 12b

0.27

0.22 Vsb=0
Vsb=1
ID (mA)

Vsb=2
Vsb=3
0.17 Vsb=4
Vsb=5

0.12

0.07
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 3.75 4 4.25 4.5

VGS (V)

Figure 6 Transfer characteristic curves for the device 12b

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 ID vs. VGS 12c

0.22

0.195

0.17
Vsb=0
Vsb=1
ID (mA)

0.145
Vsb=2
Vsb=3
Vsb=4
Vsb=5
0.12

0.095

0.07
0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4 1.45 1.5 1.55

VGS (V)

Figure 7 Transfer characteristic curves for the device 12c

4.2 observations

4.2.1 body effect

By observing the characteristic curves (Figure 5, 6, 7), the body effect is apparent. As expected [5], an increase in
VSB results in an increase in the threshold voltage (Figure 8).

VT vs VSB
1

0.9

0.8
VT (V)

0.7

0.6

0.5

0.4
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5

VSB (V)

Figure 8 VT vs VSB

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Our results also indicate that the extent of body effect is a function of transistor size (Figure 9). An increase in the
ratio (W/L) of the gate region results in a more significant increase in the threshold voltage due to body effect.

Increase in VT vs Transistor Size

85

84

83
Increase in VT (%)

82

81

80

79

78
2.4 2.6 2.8 3 3.2 3.4 3.6

ratio of gate region size (W/L)

Figure 9 % increase in VT for different transistor size

5. Conclusion
The results of our study confirm the influence of body effect on the performance of nMOS enhancement mode
transistors. As introduced earlier, the effect is especially significant in digital logic design. For example, consider the
inverter structure in Figure 10.

Figure 10 Schematic of inverter

In this circuit, the VSB of the switching transistor, M2, is always zero. However, due to the saturated load
configuration, the VSB of loading transistor, M1, is never zero, and has a maximum value of VDD-VT1, where VT1 is
the threshold voltage of transistor M1 [1].
The inherent limitations of the saturated load configuration are clearly demonstrated by this study in that attempts
to increase the output level, Vout, are countered by the corresponding increase in VT1 due to the body effect. This is
especially important in cascaded systems where this output, Vout, must trigger subsequent devices.
Although the body effect cannot be eliminated, an estimation of its impact on varying transistor sizes may lead to
design modifications that minimize the impact of the body effect on the overall performance of the device.

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6. References

1. Wei-Han Jeng and Kan Banchusuwan, “The Design and Realization of nMOS Digital Devices” , NCUR
2004 Proceedings, April 2004.
2. Jaeger, R.C. and Blalock, T.N., Microelectronic Circuit Design, 2nd ed. (2004), McGraw Hill, New York,
New York, pp. 195-96, pp. 377-407.
3. Jaeger, R.C., Introduction to Microelectronic Fabrication, 2nd ed. (2002), Vol. V of the Modular Series on
Solid State Devices, Prentice Hall, Upper Saddle River, New Jersey, pp. 49, pp. 53, pp. 217.
4. Gau and Boet, Microelectronic Fabrication, 2004 St. Cyr French Military Academy Training at VMI
5. Sung-Mo Kang, CMOS DIGITAL INTEGRATED CIRCUITS, 2nd ed. (1999), McGraw Hill, New York,
New York, pp. 73-79.

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