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OVERVIEW
1.1 INTRODUCTION
Now you can control your mouse cursor and windows media player with your TV
remote. So when you are watching a movie or listening songs on your PC, you need not
to get up from your seat to change the volume or to change the track you can simply use
your TV remote to do this for you.
This project is an implementation of RC5-remote reception on an 8052
microcontroller. The received code is decoded and sent to the PC IR remote software
written in Visual Basic. The cursor position is moved according to the keys pressed.
There are two modes of operation one is as mouse control and second is Windows media
player control. The convenience of selecting TV channels using your remote and then
pointing the same remote to your Computer so that you can control the whole system
using the single remote control. The 8052 microcontroller is used to control all the
system. An integrated Infrared Receiver is used to receive the infrared signal from the
remote control handset.
The received infrared signal was decoded by using the program, which was
written on the ROM of the Microcontroller. The programs are flashed on the ROM area
of the Microcontroller. The Flash memory is a type of EEPROM. The Details of the
switch pressed was sent to the PC through its serial port. In the PC, Visual Basic was
used to control the PC through the API functions.
The main goal of the project is to control mouse cursor and windows media
player with TV remote. This is done with the implementation of RC5-remote on an 8052
microcontroller. Here the IR receiver is connected to the microcontroller. The
microcontroller is connected to the pc through RS232. When a certain key is pressed in
the remote, it sends infrared signal through its IR transmitter to the IR receiver which is
connected to the 8052 microcontroller the received infrared signal is decoded by using
the program written on the ROM of the microcontroller. Hence the operations of cursor
and windows media player are performed according to the key pressed.
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1.3 COMPONENTS AND METHODOLOGY
Power Supply
Voltage CONTROLLIN
Level G UNIT IR
Converter Receiver
IR
PC Transmitter
2
• The output of 5V is generated first by this section which is fed to the Vcc pin or
40th pin of the microcontroller to supply operating voltage.
• Crystal oscillator which is in conjunction with few capacitors is connected to the
18th and 19th pin of the microcontroller.
• RS 232 is connected to the microcontroller to interface with PC.
• MAX 232 IC is working as the interface between the RS 232 and the
microcontroller.
• IR receiver is connected to the microcontroller through the port 3. IR receiver is
connected to P3.0
• IR transmitter is fixed in the remote.
• The IR transmitter transmits certain infrared signal with respect to the keys
pressed in the RC5 TV remote to the IR receiver which is connected to the 89S52
microcontroller.
• The mouse cursor and the windows media player in the PC functions according to
the keys pressed in the TV remote.
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CHAPTER 2
EMBEDDED SYSTEM
4
Certain operating systems or language platforms are tailored for the embedded
market, such as Embedded Java and Windows XP Embedded. However, some low-end
consumer products use very inexpensive microprocessors and limited storage, with the
application and operating system both part of a single program. The program is written
permanently into the system's memory in this case, rather than being loaded into RAM
(random access memory), as programs on a personal computer are.
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experienced designer. Selecting a right microprocessor may turn out as a most difficult
first step and it is getting complicated as new devices continue to pop-up very often.
In the 8 bit segment, the most popular and used architecture is Intel's 8031. Market
acceptance of this particular family has driven many semiconductor manufacturers to
develop something new based on this particular architecture. Even after 25 years of
existence, semiconductor manufacturers still come out with some kind of device using
this 8031 core.
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CHAPTER 3
MICROCONTROLLER (AT89S52)
3.1 INTRODUCTION
A Microcontroller consists of a powerful CPU tightly coupled with memory,
various I/O interfaces such as serial port, parallel port timer or counter, interrupt
controller, data acquisition interfaces-Analog to Digital converter, Digital to Analog
converter, integrated on to a single silicon chip.
If a system is developed with a microprocessor, the designer has to go for
external memory such as RAM, ROM, EPROM and peripherals. But controller is
provided all these facilities on a single chip. Development of a Microcontroller
reduces PCB size and cost of design.
Features
• Compatible with MCS®-51 Products
• 8K Bytes of In-System Programmable (ISP) Flash Memory – Endurance: 10,000
Write/Erase Cycles
• 4.0V to 5.5V Operating Range
• Fully Static Operation: 0 Hz to 33 MHz
• Three-level Program Memory Lock • 256 x 8-bit Internal RAM • 32 Programmable
I/O Lines
• Three 16-bit Timer/Counters
• Eight Interrupt Sources
• Full Duplex UART Serial Channel
• Low-power Idle and Power-down Modes
• Interrupt Recovery from Power-down Mode • Watchdog Timer
• Dual Data Pointer
• Power-off Flag • Fast Programming Time
• Flexible ISP Programming (Byte and Page Mode)
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• Green (Pb/Halide-free) Packaging Option
3.2 DESCRIPTION
The AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller
with 8K bytes of in-system programmable Flash memory. The device is manufactured
using Atmel’s high-density nonvolatile memory technology and is compatible with
the industry standard 80C51 instruction set and pinout. The on-chip Flash allows the
program memory to be reprogrammed in-system or by a conventional nonvolatile
memory programmer. By combining a versatile 8-bit CPU with in-system
programmable Flash on a monolithic chip, the Atmel AT89S52 is a powerful
microcontroller which provides a highly-flexible and cost-effective solution to many
embedded control applications.
The AT89S52 provides the following standard features: 8K bytes of Flash,
256 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit
timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port,
on-chip oscillator, and clock circuitry. In addition, the AT89S52 is designed with
static logic for operation down to zero frequency and supports two software selectable
power saving modes. The Idle Mode stops the CPU while allowing the RAM,
timer/counters, serial port, and interrupt system to continue functioning. The Power-
down mode saves the RAM con-tents but freezes the oscillator, disabling all other
chip functions until the next interrupt or hardware reset. 8-bit Microcontroller with 8K
Bytes In-System Programmable Flash AT89S52 1919D
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PIN-DIAGRAM:
9
FIGURE 3.2: BLOCK DIAGRAM OF AT89S52 MICROCONTROLLER
DESCRIPTION
4.1 VCC
Supply voltage
4.2 GND
Ground
4.3 Port 0
Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin
can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as
high-impedance inputs.
9
Port 0 can also be configured to be the multiplexed low-order address/data bus
during accesses to external program and data memory. In this mode, P0 has internal
pull-ups.
Port 0 also receives the code bytes during Flash programming and outputs the
code bytes during program verification. External pull-ups are required during program
verification.
4.4 Port 1
Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1
output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins,
they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port
1 pins that are externally being pulled low will source current (IIL) because of the
internal pull-ups.
In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external
count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively,
as shown in the following table.
Port 1 also receives the low-order address bytes during Flash programming
and verification
4.5 Port 2
Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2
output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins,
they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port
2 pins that are externally being pulled low will source current (IIL) because of the
internal pull-ups.
Port 2 emits the high-order address byte during fetches from external program
memory and during accesses to external data memory that uses 16-bit addresses
(MOVX @ DPTR). In this application, Port 2 uses strong internal pull-ups when
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emitting 1s. During accesses to external data memory that uses 8-bit addresses
(MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.
Port 2 also receives the high-order address bits and some control
signals during Flash programming and verification.
4.6 Port 3
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3
output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins,
they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port
3 pins that are externally being pulled low will source current (IIL) because of the
pull-ups.
Port 3 receives some control signals for Flash programming and verification.
Port 3 also serves the functions of various special features of the AT89S52, as
shown in the following table.
4.7 RST
Reset input. A high on this pin for two machine cycle while the oscillator is
running resets the device. This pin drives high for 98 oscillator periods after the
Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to
disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature
is enabled.
4.8 ALE/PROG
Address Latch Enable (ALE) is an output pulse for latching the low byte of the
address during accesses to external memory. This pin is also the program pulse input
(PROG) during Flash programming.
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In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator
frequency and may be used for external timing or clocking purposes. Note, however,
that one ALE pulse is skipped during each access to external data memory.
If desired, ALE operation can be disabled by setting bit 0 of SFR location
8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction.
Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if
the microcontroller is in external execution mode.
4.9 PSEN
Program Store Enable (PSEN) is the read strobe to external program memory.
When the AT89S52 is executing code from external program memory, PSEN is
activated twice each machine cycle, except that two PSEN activations are skipped
during each access to external
data memory.
4.10 EA/VPP
External access enable (EA) must be strapped to GND in order to enable the
device to fetch code from external program memory locations starting at 0000H up to
FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched
on reset.
EA should be strapped to VCC for internal program executions.
This pin also receives the 12-volt programming enable voltage (VPP) during
Flash programming.
4.11 XTAL1
Input to the inverting oscillator amplifier and input to the internal clock
operating circuit.
4.12 XTAL2
Output from the inverting oscillator amplifier.
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3.3 SPECIAL FUNCTION REGISTERS
A map of the on-chip memory area called the Special Function Register (SFR)
space is shown in Table 3-1.
Note that not all of the addresses are occupied, and unoccupied addresses may
not be implemented on the chip. Read accesses to these addresses will in general
return random data, and write accesses will have an indeterminate effect.
User software should not write 1s to these unlisted locations, since they may
be used in future products to invoke new features. In that case, the reset or inactive
values of the new bits will always be 0.
Timer 2 Registers: Control and status bits are contained in registers T2CON
(shown in Table 3.2) and T2MOD (shown in Table 3.6) for Timer 2. The register pair
(RCAP2H, RCAP2L) is the Capture/Reload registers for Timer 2 in 16-bit capture
mode or 16-bit auto-reload mode.
Interrupt registers: The individual interrupt enable bits are in the IE register.
Two priorities can be set for each of the six interrupt sources in the IP register.
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Table 3.1: AT89S52 SFR Map and Reset Values
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Table 3.2: T2CON – Timer/Counter 2 Control Register
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Dual Data Pointer Registers: To facilitate accessing both internal and external data
memory, two banks of 16-bit Data Pointer Registers are provided: DP0 at SFR
address locations 82H-83H and DP1 at 84H-85H. Bit DPS = 0 in SFR AUXR1 selects
DP0 and DPS = 1 selects DP1. The user should ALWAYS initialize the DPS bit to the
appropriate value before accessing the respective Data Pointer Register.
Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the
PCON SFR. POF is set to “1” during power up. It can be set and rest under software
control and is not affected by reset.
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3.4.1 Data Memory:
The AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes
occupy a parallel address space to the Special Function Registers. This means that the
upper 128 bytes have the same addresses as the SFR space but are physically separate
from SFR space.
When an instruction accesses an internal location above address 7FH, the
address mode used in the instruction specifies whether the CPU accesses the upper
128 bytes of RAM or the SFR space. Instructions which use direct addressing access
the SFR space.
For example, the following direct addressing instruction accesses the SFR at
location 0A0H (which is P2).
MOV 0A0H, #data
Instructions that use indirect addressing access the upper 128 bytes of RAM.
For example, the following indirect addressing instruction, where R0 contains 0A0H,
accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).
MOV @R0, #data
Note that stack operations are examples of indirect addressing, so the upper
128 bytes of data RAM are available as stack space.
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3.5.1 Using the WDT
To enable the WDT, a user must write 01EH and 0E1H in sequence to the
WDTRST register (SFR location 0A6H). When the WDT is enabled, the user needs to
service it by writing 01EH
and 0E1H to WDTRST to avoid a WDT overflow. The 14-bit counter overflows
when it reaches 16383 (3FFFH), and this will reset the device. When the WDT is
enabled, it will increment every machine cycle while the oscillator is running. This
means the user must reset the WDT at least every 16383 machine cycles. To reset the
WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write-only
register. The WDT counter cannot be read or written. When WDT overflows, it will
generate an output RESET pulse at the RST pin. The RESET pulse duration is
98xTOSC, where TOSC = 1/FOSC. To make the best use of the WDT, it should be
serviced in those sections of code that will periodically be executed within the time
required to prevent a WDT reset.
3.6 TIMERS
3.6.1 Timer 0 and 1
Timer 0 and Timer 1 in the AT89S52 operate the same way as Timer 0 and
Timer 1 in the AT89C51 and AT89C52.
3.7.2 Timer 2
Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event
counter. The type of operation is selected by bit C/T2 in the SFR T2CON (shown in
Table 3.2). Timer 2 has three operating modes: capture, auto-reload (up or down
counting), and baud rate generator. The modes are selected by bits in T2CON, as
shown in Table 3.5. Timer 2 consists of two 8-bit registers, TH2 and TL2. In the
Timer function, the TL2 register is incremented every machine cycle. Since a machine
cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator
frequency.
Table 3.5: Timer 2 Operating Modes
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frequency. To ensure that a given level is sampled at least once before it changes, the
level should be held for at least one full machine cycle.
• Capture Mode:
In the capture mode, two options are selected by bit EXEN2 in T2CON. If
EXEN2 = 0, Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in
T2CON. This bit can then be used to generate an interrupt. If EXEN2 = 1, Timer 2
performs the same operation, but a 1-to-0 transition at external input T2EX also
causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L,
respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set.
The EXF2 bit, like TF2, can generate an interrupt. The capture mode is illustrated in
Figure 3.4.
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Table 3.6: T2MOD – Timer 2 Mode Control Register
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Figure 3.4: Timer 2 Auto Reload Mode (DCEN = 0)
22
The baud rate generator mode is similar to the auto-reload mode, in that a
rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in
registers RCAP2H and RCAP2L, which are preset by software.
The baud rates in mode 1 and 3 are determined in Timer2’s over rate floe
according to the equation.
The Timer can be configured for either timer or counter operation. In most
applications, it is configured for timer operation (CP/T2 = 0). The timer operation is
different for Timer 2 when it is used as a baud rate generator. Normally, as a timer, it
increments every machine cycle (at 1/12 the oscillator frequency). As a baud rate
generator, however, it increments every state time (at 1/2 the oscillator frequency).
The baud rate formula is given below.
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Figure 3.6: Timer 2 in Baud Rate Generator Mode
In the clock-out mode, Timer 2 roll-overs will not generate an interrupt. This
behavior is similar to when Timer 2 is used as a baud-rate generator. It is possible to
use Timer 2 as a baud-rate generator and a clock generator simultaneously. Note,
however, that the baud-rate and clock-out frequencies cannot be determined
independently from one another since they both use RCAP2H and RCAP2L.
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FIGURE 3.7: Timer 2 in Clock-Out Mode
3.9 INTERRUPTS
The AT89S52 has a total of six interrupt vectors: two external interrupts
(INT0 and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port
interrupt. These interrupts are all shown in Figure 3.8.
Each of these interrupt sources can be individually enabled or disabled by
setting or clearing a bit in Special Function Register IE. IE also contains a global
disable bit, EA, which disables all interrupts at once.
Note that Table 3.7 shows that bit position IE.6 is unimplemented. User
software should not write a 1 to this bit position, since it may be used in future AT89
products.
Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in
register T2CON. Neither of these flags is cleared by hardware when the service
routine is vectored to. In fact, the service routine may have to determine whether it
was TF2 or EXF2 that generated the interrupt, and that bit will have to be cleared in
software.
The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in
which the timers overflow. The values are then polled by the circuitry in the next
cycle. However, the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle
in which the timer overflows.
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Table 3.7: Interrupt Enable (IE) Register
26
external clock signal, since the input to the internal clocking circuitry is through a
divide-by-two flip-flop, but minimum and maximum voltage high and lowtime
specifications must be observed.
27
Figure 3.10: External Clock Drive Configuration
Table 3.8: Status of External Pins During Idle and Power-down Modes
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CHAPTER 4
IR TRANSMITTER, IR RECEIVER
& 555 TIMER
4.1 INTRODUCTION
This is an IR transmitting circuit which can be used in many projects (I designed
this to try to make my 3D glasses wireless). This IR transmitter sends 40 kHz (frequency
can be adjusted using R2) carrier under computer control (computer can turn the IR
transmission on and off). IR carriers at around 40 kHz carrier frequencies are widely used
in TV remote controlling and ICs for receiving these signals are quite easily available.
The 555 timer integrated circuit (IC) has become a mainstay in electronics design. A 555
timer will produce a pulse when a trigger signal is applied to it. The pulse length is
determined by charging then discharging a capacitor connected to a 555 timer. A 555
timer can be used to debounce switches, modulate signals, create accurate clock signals,
create pulse width modulated (PWM) signals, etc. A 555 timer can be obtained from
various manufacturers including Fairchild Semiconductor and National Semiconductor.
A 555 timer is shown below in Fig 5.1.
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• Vcc 5V to 15 V supply input
• Discharge Used to discharge a capacitor
• Threshold Used to detect when the capacitor has charged. The Output pin goes low
when capacitor has charged to 66.6% of Vcc.
• Control Voltage Used to change Threshold and Trigger set point voltages and is rarely
used
The monostable 555 timer circuit can be used in the following applications:
• Debounce a momentary/pushbutton switch
• Turning on an actuator for a set period of time
• Turn an output from a resistive sensor from analog signal to digital signal.
30
FIGURE 4.3: 555 Timer Astable Circuit
Fig 4.3 shows an Astable 555 timer circuit. The Astable 555 timer circuit outputs
a series of pulses. When the circuit is first turned on, the discharge pin is disconnected
from ground and output pin is set high because the trigger pin is below 33% Vcc Voltage.
The capacitor C starts to charge through resistors R1 and R2. The threshold pin is used to
detect when the voltage across the capacitor reaches 66.6% Vcc voltage. When the
voltage across the capacitor reaches 66.6% Vcc voltage, the output pin is set low and the
discharge pin is connected back to ground. When the discharge pin is connected back to
ground, the capacitor starts discharging though resistor R2. When the voltage across the
capacitor reaches 33.3% Vcc voltage, the cycle repeats and creates a series of output
pulses. An astable circuit triggers from previous output pulse whereas a monostable
circuit requires an externally applied trigger.
The astable 555 timer circuit can be used in the following applications:
• Modulate transmitters such as ultrasonic and IR transmitters
• Create an accurate clock signal
• Turn on and off an actuator at set time intervals for a fixed duration
31
Verify with the TA that everything is soldered correctly. Then apply power to the
transmitter circuit. Use an oscilloscope to observe the signal at node A. Adjust the 10kΩ
variable resistor until the signal at node A is a 38 kHz series of pulses. Apply power to
the receiver circuit Point the IR light emitting diode (LED) on the transmitter to the
detector on the receiver. When the pushbutton is depressed the visible LED on the
receiver should blink. If the visible led is blinking randomly, put exposed 35 mm camera
film around the IR detector.
4.3 IR RECEIVERS
Infrared receivers pick up infrared signals within line-of-sight, and within 30 feet
or so, and turn the signal into electrical impulses. These electrical impulses can be carried
around the home on wires, and then turned back into infrared signals by emitters. Due to
their complexity and sensitivity, infrared receivers tend to be the most expensive part of
an infrared distribution system.
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CHAPTER 5
REGULATED POWER SUPPLY
5.1 INTRODUCTION
A variable regulated power supply, also called a variable bench power
supply, is one where you can continuously adjust the output voltage to your
requirements. Varying the output of the power supply is the recommended way to
test a project after having double checked parts placement against circuit drawings
and the parts placement guide.
This type of regulation is ideal for having a simple variable bench power
supply. Actually this is quite important because one of the first projects a hobbyist
should undertake is the construction of a variable regulated power supply. While a
dedicated supply is quite handy e.g. 5V or 12V, it's much handier to have a
variable supply on hand, especially for testing.
Most digital logic circuits and processors need a 5 volt power supply. To
use these parts we need to build a regulated 5 volt source. Usually you start with
an unregulated power To make a 5 volt power supply, we use a LM7805 voltage
regulator IC (Integrated Circuit). The IC is shown below.
The LM7805 is simple to use. You simply connect the positive lead of your
unregulated DC power supply (anything from 9VDC to 24VDC) to the Input pin,
33
connect the negative lead to the Common pin and then when you turn on the
power, you get a 5 volt supply from the Output pin.
34
FIGURE 5.2: CIRCUIT DIAGRAM OF POWER SUPLY
35
TABLE 5.1 PIN OUTS OF D-9 AND D-25
When communicating with various micro processors one needs to convert the
RS232 levels down to lower levels, typically 3.3 or 5.0 Volts. Here is a cheap and simple
way to do that. Serial RS-232 (V.24) communication works with voltages -15V to +15V
for high and low. On the other hand, TTL logic operates between 0V and +5V. Modern
low power consumption logic operates in the range of 0V and +3.3V or even lower.
36
TABLE 5.2 LOGIC LEVELS OF TTL & RS232
Thus the RS-232 signal levels are far too high TTL electronics, and the negative
RS-232 voltage for high can’t be handled at all by computer logic. To receive serial data
from an RS-232 interface the voltage has to be reduced. Also the low and high voltage
level has to be inverted. This level converter uses a Max232 and five capacitors. The
max232 is quite cheap (less than 5 dollars) or if you’re lucky you can get a free sample
from Maxim. The MAX232 from Maxim was the first IC which in one package contains
the necessary drivers and receivers to adapt the RS-232 signal voltage levels to TTL
logic.
8 4 1 3 1 2 P 3 R . 0X D
7 3 T 1 O U T 8 R 1 I RN 1 O 9 U T
VCC
6 2 R 2 I RN 2 O U T
1 1 0 1 4 T 1 O U T
T XP D 3 .1 1 1 T 2 I NT 1 O 7 U T
C 4 T 1 I NT 2 O U T
5 V 1
3 C 1 +
C0 . 51 u 4f C 1 -
5 C 2 +
C 6 C 2 -
0 . 1 u 2f
0 . 1 u f 6 V +
GND
V -
C 7
M A X 3 2 3 2
15
0 . 1 u f
CHAPTER 6
38
KEIL COMPILATION TOOL
40
6.4 KEIL C CROSS COMPILER:
Keil is a German based Software development company. It provides several
development tools like
• IDE (Integrated Development environment)
• Project Manager
• Simulator
• Debugger
• C Cross Compiler, Cross Assembler, Locator/Linker
Keil Software provides you with software development tools for the ARM
microcontrollers. With these tools, you can generate embedded applications for the
multitude of ARM derivatives. Keil provides following tools for ARM development
1. ARM Optimizing C Cross Compiler,
2. Macro Assembler,
3. ARM Utilities (linker, object file converter, library manager),
4. Source-Level Debugger/Simulator,
5. µVision for Windows Integrated Development Environment.
The keil ARM tool kit includes three main tools, assembler, compiler and linker.
An assembler is used to assemble your ARM assembly program
A compiler is used to compile your C source code into an object file
A linker is used to create an absolute object module suitable for your in-circuit
emulator.
CHAPTER 7
41
FLASH MAGIC
7.1 INTRODUCTION
Flash Magic is a PC tool for programming flash based microcontrollers from
NXP using a serial protocol while in the target hardware.
Flash Magic is a feature-rich Windows based tool for the downloading of code
into NXP flash microcontrollers. It utilizes a feature of the microcontrollers called ISP,
which allows the transfer of data serially between a PC and the device.
Flash Magic can erase devices, program them, read data and read and set various
configuration information. Rather than providing the basic features of ISP, Flash Magic
adds additional features and intelligence, allowing complex operations to be performed.
For example, erasing can be any collection of pages, blocks, the hex file to be
programmed or the entire device. Some devices store the ISP boot loader in flash
memory, so Flash magic implements methods to protect this code from being erased.
Additional advanced features of Flash Magic include the automatic programming
of checksums, entering ISP mode via a serial command, execution of Just in Time
modules allowing endless flexibility in the data programmed, control over RS232 signals
to place devices into ISP mode, and control over the timing of such signals.
Flash Magic has been available for free for over six years and supports all current
8-bit (8052), 16-bit (XA) and 32-bit (ARM) flash microcontrollers from NXP.
• Custom ISP tool for in-house use, for example production line programming
where it is essential the user interface is simplified as much as possible
• End user ISP tool for updating the firmware of products. You can build the hex
file into the application or allow it to be fetched over the internet. Adverts for new
products could be displayed to the user. Use one tool for all your products involving
potentially multiple NXP microcontrollers.
• Gang programming tool. Invoke multiple instances of the Flash Magic DLL in
separate threads, each using a different COM port to allow parallel ISP programming
• Future-proofing products. Rather than write your own ISP tool and have to keep
updating it for new NXP devices, updates to the DLL will automatically add new devices
42
7.2 FEATURES:
43
circuit diagram is included in the Manual. Essential for ISP with target hardware that is
hard to access.
• Able to send commands to place the device in BootROM mode, with support for
command line interfaces. The installation includes an example project for the Keil and
Raisonance 8052 compilers that show how to build support for this feature into
applications.
• Able to play any Wave file when finished programming.
• Built in automated version checker - helps ensure you always have the latest
version.
• Powerful, flexible Just In Time Code feature. Write your own JIT Modules to
generate last minute code for programming. Uses include:
o Serial number generation
o Copy protection and copy authorization
o Storing program date and time - manufacture date
o Storing program operator and location
o Lookup table generation
o Language tables or language selection
o Centralized record keeping
o Obtaining latest firmware from the Corporate Web site or project intranet
• Sponsored by NXP Semiconductors
• Features automatically updating Internet links including links to related technical
documents, software updates, utilities and code examples, using Embedded Hints
technology
• Displays information about the selected Hex File, including the creation and
modification dates, flash memory used, percentage of the current device used
• Completely free!
• Flash Magic works on any versions of Windows, except Windows 95. 10Mb of
disk space is required
CHAPTER 8
PROJECT CIRCUITRY
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8.1 PROJECT CIRCUIT
In this project, wireless mouse system is mainly based on the 8- bit micro
controller. Here we are using the micro controller named as 89C52 and it needs 5volts of
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power supply. In the power supply circuit, convert the A.C to D.C voltage using Bridge
rectifier. Then we can get the 12volt of DC supply. Using LM7805 regulator, we can get
the required 5v of supply to the micro controller. Connect the power supply unit of 5v to
the Vcc pin or 40th pin of the controller. Crystal oscillator is connected to the 18 th and 19th
pin of the micro controller.
Mainly the project is used to move the cursor and operation of windows
media player wirelessly using TV remote. IR receiver is connected to the micro controller
though the port 3. IR receiver is connected to the P3.0. IR transmitter is fixed in the
remote. So press the key2 in the remote, cursor move in upper direction, press the key4 in
the remote, cursor move in left direction, press the key6 in the remote, cursor move in
right direction, press the key8 in the remote, cursor move in lower direction. The system
is connected to the PC using MAX232.
8.2 CONCLUSION:
Using this project, there need not be any wire interface between the PC and
mouse. Here we can control the PC using TV remote. The project is mainly based on the
RC-5 protocol using IR sensors.
Using this project, we can control many electric appliances using tv remote with
the help of PC. The PC can also be controlled by mobile phones by doing slight
modifications to the kit.
REFERENCES:
[1]. Mr. Mazidi, “The 8052 Microcontroller and Embedded Systems”, PHI, 2000
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[2]. Mr. A.V. Deshmuk, “Microcontrollers (Theory & Applications)”, WTMH, 2005
[3]. Mr. Daniel W Lewis, “Fundamentals of Embedded Software.”
APPENDIX
SOURCE CODE:
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org 00h
main:
jb IR,$ ;Wait for first bit
mov VAR1,#255 ;3.024mS delay
djnz VAR1,$
mov VAR1,#255
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djnz VAR1,$
mov VAR1,#255
djnz VAR1,$
mov VAR1,#255
djnz VAR1,$
mov VAR1,#255
djnz VAR1,$
mov VAR1,#100
djnz VAR1,$
mov c,IR ;Read Flip bit
mov FLIP,c
clr A
mov COUNT,#5 ;Count for address
fadd:
mov VAR1,#255 ;1.728mS delay for each bit
djnz VAR1,$
mov VAR1,#255
djnz VAR1,$
mov VAR1,#255
djnz VAR1,$
mov VAR1,#4
djnz VAR1,$
mov c,IR
rlc a
djnz COUNT,fadd
mov ADDR,A ;Save the address
clr a
mov COUNT,#6 ;Count for Command
fcmd:
mov VAR1,#255 ;1.728mS Delay for each bit
djnz VAR1,$
mov VAR1,#255
djnz VAR1,$
mov VAR1,#255
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djnz VAR1,$
mov VAR1,#4
djnz VAR1,$
mov c,IR
rlc a
djnz COUNT,fcmd
mov TEMP,CMD ;Save the old command
mov CMD,a ;Save the new command
mov a,ADDR ;Cheack for valid address
cjne a,#00,nvalid
jb MODE,key ;Use mouse mode if Mode bit is 0
acall mouse
ljmp main
key: ;or keyboard mode if Mode bit is 1
acall keyboard
nvalid:
ljmp main
mskip:
cjne a,#01H,mskip1
acall chk_valid
jb VALID,ok1
ret
ok1:
mov a,#31H
acall tx
ret
mskip1:
cjne a,#02H,mskip2
mov a,#32H
acall tx
ret
mskip2:
cjne a,#03H,mskip3
acall chk_valid
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jb VALID,ok2
ret
ok2:
mov a,#33H
acall tx
ret
mskip3:
cjne a,#04H,mskip4
mov a,#34H
acall tx
ret
mskip4:
cjne a,#05H,mskip5
mov a,#35H
acall tx
ret
mskip5:
cjne a,#06H,mskip6
mov a,#36H
acall tx
ret
mskip6:
cjne a,#26H,mskip7
mov a,#37H
acall tx
ret
mskip7:
cjne a,#38H,mskip8
mov a,#38H
acall tx
ret
mskip8:
cjne a,#10H,mskip9
mov a,#37H
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acall tx
ret
mskip9:
cjne a,#11H,mskip10
mov a,#38H
acall tx
mskip10:
ret
chk_valid:
mov a,TEMP
cjne a,CMD,ms_valid1
ret
ms_valid1:
clr a
mov c,FLIP
rlc a
mov TEMP1,a
clr a
mov c,TOG
rlc a
cjne a,TEMP1,ms_valid
clr VALID
ret
ms_valid:
mov c,FLIP
mov TOG,c
setb VALID
ret
keyboard: ;Routine for Keyboard operation
mov a,TEMP
cjne a,CMD,k_valid1
ret
k_valid1:
clr a
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mov c,FLIP
rlc a
mov TEMP1,a
clr a
mov c,TOG
rlc a
cjne a,TEMP1,k_valid
ret
k_valid:
mov c,FLIP
mov TOG,c
mov a,CMD
clr c
cjne a,#7,chk
chk:
jnc greater
add a,#30H
acall tx
ret
greater:
cjne a,#0CH,next
mov a,#30H
acall tx
jnb RI,$
clr RI
mov a,SBUF
cjne a,#'m',keymode1
clr MODE
ret
keymode1:
setb MODE
ret
next:
cjne a,#26H,next1
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mov a,#37H
acall tx
ret
next1:
cjne a,#38H,next2
mov a,#38H
acall tx
ret
next2:
cjne a,#10H,next3
mov a,#37H
acall tx
ret
next3:
cjne a,#11H,next4
mov a,#38H
acall tx
ret
next4:
cjne a,#20H,next5
mov a,#36H
acall tx
ret
next5:
cjne a,#21H,next6
mov a,#35H
acall tx
ret
next6:
cjne a,#0DH,next7
mov a,#39H
acall tx
next7:
ret
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tx: ;Serial Transmit
mov sbuf,a
jnb TI,$
clr TI
ret
END
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