CMOS Fabrication

...Or What Lies Beneath...

Anurup Mitra

BITS Pilani

August 2007

Anurup Mitra CMOS Fabrication

Wire Bonding

Anurup Mitra CMOS Fabrication

Fabrication Process

A chip consists of layers of different materials which are electrically

isolated from each other.

Anurup Mitra CMOS Fabrication

Fabrication Process

A chip consists of layers of different materials which are electrically

isolated from each other. To make an electrical contact between
unlike layers, a contact or via is used.

Anurup Mitra CMOS Fabrication

Fabrication Process

A chip consists of layers of different materials which are electrically

isolated from each other. To make an electrical contact between
unlike layers, a contact or via is used.
The fabrication sequence consists of a series of steps in which
layers of the chip are defined through photolithography.

Anurup Mitra CMOS Fabrication

Fabrication Process

A chip consists of layers of different materials which are electrically

isolated from each other. To make an electrical contact between
unlike layers, a contact or via is used.
The fabrication sequence consists of a series of steps in which
layers of the chip are defined through photolithography.
Photolithography uses ‘masks’ to transfer the patterns for each
layer one at a time.

Anurup Mitra CMOS Fabrication

Fabrication Process

A chip consists of layers of different materials which are electrically

isolated from each other. To make an electrical contact between
unlike layers, a contact or via is used.
The fabrication sequence consists of a series of steps in which
layers of the chip are defined through photolithography.
Photolithography uses ‘masks’ to transfer the patterns for each
layer one at a time.
Since many entire chips are printed at once, the cost is
proportional to the area rather than the number of devices being
used in the chip/s.

Anurup Mitra CMOS Fabrication

CMOS Technologies

The main CMOS technologies are :

n-well The pMOS transistors are placed in the n-well and
the nMOS transistors are created on the substrate

Anurup Mitra CMOS Fabrication

CMOS Technologies

The main CMOS technologies are :

n-well The pMOS transistors are placed in the n-well and
the nMOS transistors are created on the substrate
p-well Guess!

Anurup Mitra CMOS Fabrication

CMOS Technologies

The main CMOS technologies are :

n-well The pMOS transistors are placed in the n-well and
the nMOS transistors are created on the substrate
p-well Guess!
twin-well This technology allows optimisation of each
transistor type

Anurup Mitra CMOS Fabrication

CMOS Technologies

The main CMOS technologies are :

n-well The pMOS transistors are placed in the n-well and
the nMOS transistors are created on the substrate
p-well Guess!
twin-well This technology allows optimisation of each
transistor type
triple-well This process permits excellent isolation between
analog and digital circuitry in a mixed signal chip

Anurup Mitra CMOS Fabrication

Photolithography

The primary method for defining areas of interest (i.e. where we

want materials to be absent or present) on a wafer is by the use of
photoresists.

Anurup Mitra CMOS Fabrication

Photolithography

The primary method for defining areas of interest (i.e. where we

want materials to be absent or present) on a wafer is by the use of
photoresists.
The wafer is coated with the photoresist and subjected to selective
illumination by the photomask or reticle.

Anurup Mitra CMOS Fabrication

...contd.

A photomask is created with chromium (chrome) covered quartz

glass.

Anurup Mitra CMOS Fabrication

...contd.

A photomask is created with chromium (chrome) covered quartz

glass. An ultraviolet light source is used to expose the photoresist.
The UV light floods the mask from the backside of the mask and
passes through the clear sections of the mask to expose the PR
that has been coated on the wafer.

Anurup Mitra CMOS Fabrication

...contd.

A photomask is created with chromium (chrome) covered quartz

glass. An ultraviolet light source is used to expose the photoresist.
The UV light floods the mask from the backside of the mask and
passes through the clear sections of the mask to expose the PR
that has been coated on the wafer.
A developer solvent is then used to dissolve the soluble unexposed
PR, leaving islands of insoluble exposed photoresist.

Anurup Mitra CMOS Fabrication

...contd.

A photomask is created with chromium (chrome) covered quartz

glass. An ultraviolet light source is used to expose the photoresist.
The UV light floods the mask from the backside of the mask and
passes through the clear sections of the mask to expose the PR
that has been coated on the wafer.
A developer solvent is then used to dissolve the soluble unexposed
PR, leaving islands of insoluble exposed photoresist. This, by the
way, is known as a negative photoresist.

Anurup Mitra CMOS Fabrication

...contd.

A photomask is created with chromium (chrome) covered quartz

glass. An ultraviolet light source is used to expose the photoresist.
The UV light floods the mask from the backside of the mask and
passes through the clear sections of the mask to expose the PR
that has been coated on the wafer.
A developer solvent is then used to dissolve the soluble unexposed
PR, leaving islands of insoluble exposed photoresist. This, by the
way, is known as a negative photoresist.
A positive resist is initially insoluble and becomes soluble after
exposure to UV.

Anurup Mitra CMOS Fabrication

...contd.

A photomask is created with chromium (chrome) covered quartz

glass. An ultraviolet light source is used to expose the photoresist.
The UV light floods the mask from the backside of the mask and
passes through the clear sections of the mask to expose the PR
that has been coated on the wafer.
A developer solvent is then used to dissolve the soluble unexposed
PR, leaving islands of insoluble exposed photoresist. This, by the
way, is known as a negative photoresist.
A positive resist is initially insoluble and becomes soluble after
exposure to UV.
Positive resists provide higher resolutions than negative resists but
are however, less sensitive to light.

Anurup Mitra CMOS Fabrication

...contd.

A photomask is created with chromium (chrome) covered quartz

glass. An ultraviolet light source is used to expose the photoresist.
The UV light floods the mask from the backside of the mask and
passes through the clear sections of the mask to expose the PR
that has been coated on the wafer.
A developer solvent is then used to dissolve the soluble unexposed
PR, leaving islands of insoluble exposed photoresist. This, by the
way, is known as a negative photoresist.
A positive resist is initially insoluble and becomes soluble after
exposure to UV.
Positive resists provide higher resolutions than negative resists but
are however, less sensitive to light. As feature sizes shrink, PR’s are
made smaller and this in turn makes them more prone to failure.

Anurup Mitra CMOS Fabrication

Well and Channel Formation

Varying proportions of donor and acceptor impurities can be

achieved by using epitaxy, desposition, or implantation.

Anurup Mitra CMOS Fabrication

Well and Channel Formation

Varying proportions of donor and acceptor impurities can be

achieved by using epitaxy, desposition, or implantation.

Epitaxy Can produce a layer of silicon with fewer defects.

Foundries provide a choice of epi or non-epi wafers.

Anurup Mitra CMOS Fabrication

Well and Channel Formation

Varying proportions of donor and acceptor impurities can be

achieved by using epitaxy, desposition, or implantation.

Epitaxy Can produce a layer of silicon with fewer defects.

Foundries provide a choice of epi or non-epi wafers.
Deposition Places dopant material on Si surface and drives it in
with thermal diffusion to create deep junctions. CVD
can be alternatively be used to lay down thin films of
materials.

Anurup Mitra CMOS Fabrication

Well and Channel Formation

Varying proportions of donor and acceptor impurities can be

achieved by using epitaxy, desposition, or implantation.

Epitaxy Can produce a layer of silicon with fewer defects.

Foundries provide a choice of epi or non-epi wafers.
Deposition Places dopant material on Si surface and drives it in
with thermal diffusion to create deep junctions. CVD
can be alternatively be used to lay down thin films of
materials.
Implantation Ion implantation impinges the Si substrate with
highly accelerated donor or acceptor atoms. It is the
standard method for well and source/drain formation
today.

Anurup Mitra CMOS Fabrication

Silicon Dioxide

Various thicknesses of SiO2 are required. While thin oxides are

used for transistor gates, thick oxides are used for high voltage
devices. Even thicker oxides are used for device isolation.

Anurup Mitra CMOS Fabrication

Silicon Dioxide

Various thicknesses of SiO2 are required. While thin oxides are

used for transistor gates, thick oxides are used for high voltage
devices. Even thicker oxides are used for device isolation.
Oxidation is achieved by heating Si wafers in an oxidising
atmosphere. A variety of processes are used:
Wet Ox This is when the oxidising atmosphere contains water
vapour. It is a rapid process. It is used for fox.

Anurup Mitra CMOS Fabrication

Silicon Dioxide

Various thicknesses of SiO2 are required. While thin oxides are

used for transistor gates, thick oxides are used for high voltage
devices. Even thicker oxides are used for device isolation.
Oxidation is achieved by heating Si wafers in an oxidising
atmosphere. A variety of processes are used:
Wet Ox This is when the oxidising atmosphere contains water
vapour. It is a rapid process. It is used for fox.
Dry Ox Here, the oxidising atmosphere is pure oxygen. This
forms better quality oxides and are used for thinox.

Anurup Mitra CMOS Fabrication

Silicon Dioxide

Various thicknesses of SiO2 are required. While thin oxides are

used for transistor gates, thick oxides are used for high voltage
devices. Even thicker oxides are used for device isolation.
Oxidation is achieved by heating Si wafers in an oxidising
atmosphere. A variety of processes are used:
Wet Ox This is when the oxidising atmosphere contains water
vapour. It is a rapid process. It is used for fox.
Dry Ox Here, the oxidising atmosphere is pure oxygen. This
forms better quality oxides and are used for thinox.
ALD Atomic Layer Deposition is a process in which a thin
chemical layer is attached to a surface and a second
(different) chemical layer is used to react with the
first and produce a thin layer of the required product.

Anurup Mitra CMOS Fabrication

Wafer

A bare Si wafer is chosen

The type will be n or p depending upon the technology

Anurup Mitra CMOS Fabrication

Oxidation of Wafer

The wafer is oxidised at a high temperature

This must be patterned to define the n-well

Anurup Mitra CMOS Fabrication

PR deposition

The photoresist is deposited throughout the wafer

The PR has to be patterned to allow formation of the well

Anurup Mitra CMOS Fabrication

n-well Mask

The PR is exposed through the n-well mask

The softened PR is is removed to expose the oxide

Anurup Mitra CMOS Fabrication

Oxide Etch

The oxide is etched with HF acid where unprotected by PR

The wafer is now exposed to the n-well area

Anurup Mitra CMOS Fabrication

PR removal

The remaining PR is removed via piranha etch

The well is ready to be formed

Anurup Mitra CMOS Fabrication

n-well Formation

The diffusion process can make the the n-well

Ion implantation can also form the same

Anurup Mitra CMOS Fabrication

Oxide Removal

The remaining oxide is stripped with HF acid

This leaves the exposed wafer with the n-well formed

Anurup Mitra CMOS Fabrication

Gate Formation

The gates are made up of polysilicon over thinox

CVD is used to grow the poly (heavily doped) layer

Anurup Mitra CMOS Fabrication

Poly Patterning

The wafer is now patterned with PR and the poly mask

Finally this leaves the device gates

Anurup Mitra CMOS Fabrication

Diffusion Pattern

Again, a protective oxide is grown and PR deposited

PR is patterned according to the diffusion mask

Anurup Mitra CMOS Fabrication

Wafer Exposure for Diffusion

The protective oxide is etched away

The wafer is exposed for S/D/B formation

Anurup Mitra CMOS Fabrication

n-Diffusion Regions

The n+ diffusion regions are formed

Polysilicon blocks the channel area

Anurup Mitra CMOS Fabrication

Self-Aligned Process

This is a self-aligned process

S/D are automatically formed adjacent to the gate

Anurup Mitra CMOS Fabrication

p-Diffusion

The p-diffusion mask is used next

This completes creation of all active regions

Anurup Mitra CMOS Fabrication

Field Oxide

The field oxide is grown to insulate wafer and metal

It is patterned with the contact mask

Anurup Mitra CMOS Fabrication

Metal Formation

Al is sputtered over the entire area filling contact cuts too

Metal is patterned with the metal mask

Anurup Mitra CMOS Fabrication

Multilevel Metallisation - Fig. 1

Anurup Mitra CMOS Fabrication

Multilevel Metallisation - Fig. 2

Anurup Mitra CMOS Fabrication