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Chapitre 2 : Années cinquante

1. Langage de programmation
2. Répertoire d’instruction
3. Format d’instruction
4. Modes d’adressage
5. Type de langage machine
6. Technologie et logiciels
7. Premiers répertoire d’instructions
8. Machine à accumulateur
9. Machine à registres
Architecture des ordinateurs, M. Eleuldj, EMI, Février 2008 Ch.II. 1
Langages de programmation
⇒ Outil d’écriture des programmes exécutables par ordinateur

• Langages de bas niveau : langages machine et langages d’assemblage


• Langages de haut niveau ou évolués

quelques instructions d’un programme en langage machine


….
101001011100111 ; transférer le contenu de l’adresse 103 à A
111100001011101 ; ajouter le contenu de A à B
….

quelque instructions d’un programme en langage d’assemblage


….
MOV A,103 ; transférer le contenu de l’adresse 103 à A
ADD A,B ; ajouter le contenu de A à B
….

Architecture des ordinateurs, M. Eleuldj, EMI, Février 2008 Ch.II. 2


Caractéristiques des langages

Langages de bas niveau


• étroitement lié à l’ordinateur utilisé
• difficiles à lire et à écrire
• fortement exposés aux erreurs

Langages de haut niveau


• indépendance par rapport à l’ordinateur ⇒ portabilité
• programmes facilement compréhensibles
• faciles à apprendre
• instructions proches de la langue naturelle

Architecture des ordinateurs, M. Eleuldj, EMI, Février 2008 Ch.II. 3


Programmation

…. ….
…. ….
Programme A=A+B MOV A,103
Programme
en langage …. ADD A,B
…. en langage
haut niveau …. d’assemblage
….

Compilateur Interpréteur Assembleur


….
….
101001011100111
11110000101110
…. Programme
…. en langage
machine

Ordinateur

Architecture des ordinateurs, M. Eleuldj, EMI, Février 2008 Ch.II. 4


Types d’instruction machine
Ensemble d’instructions machine = répertoire d’instructions

Instruction de transfert de données entre la mémoire et les registre :


MOVE, LOAD, STORE,…

Opération arithmétique ou logique :


ADD, AND,…

Opération de contrôle d’aiguillage :


BR, JUMP,…

Instruction d’entrée/sortie
IN, OUT, …

Architecture des ordinateurs, M. Eleuldj, EMI, Février 2008 Ch.II. 5


Format d’instruction
⇒ Façon avec laquelle les instructions sont stockées en mémoire

101001011100111 ; transférer le contenu de l’adresse 103 à A

instruction 1010 0101 1100111

Code d’opération Adresse du registre A Adresse 103

Architecture des ordinateurs, M. Eleuldj, EMI, Février 2008 Ch.II. 6


1

Influence of Technology and

Software on Instruction Sets:

Up to the dawn of IBM 360

Arvind

Computer Science and Artificial Intelligence Laboratory


M.I.T.

Based on the material prepared by

Arvind and Krste Asanovic

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Importance of Technology

New technologies not only provide greater


speed, size and reliability at lower cost, but
more importantly these dictate the kinds of
structures that can be considered and thus
come to shape our whole view of what a
computer is.

Bell & Newell

September 12, 2005


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Technology is the dominant factor


in computer design
Technology
Transistors Computers
Integrated circuits
VLSI (initially)
Laser disk, CD’s

Technology
Core memories Computers
Magnetic tapes
Disks

Technology

ROMs, RAMs
VLSI Computers
Packaging
Low Power

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But Software...

As people write programs and use computers,


our understanding of programming and
program behavior improves.

This has profound though slower impact

on computer architecture

Modern architects cannot avoid paying


attention to software and compilation issues.

Technology
Computers
Software
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Computers in mid 50’s


• Hardware was expensive
• Stores were small (1000 words)
⇒ No resident system-software!
• Memory access time was 10 to 50 times
slower than the processor cycle
⇒ Instruction execution time was totally dominated by
the memory reference time.
• The ability to design complex control
circuits to execute an instruction was the
central design concern as opposed to the
speed of decoding or an ALU operation
• Programmer’s view of the machine was
inseparable from the actual hardware
implementation
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Programmer’s view of the machine


Arvind

IBM 650
A drum machine with 44 instructions

Instruction: 60 1234 1009


• “Load the contents of location 1234 into the
distribution; put it also into the upper accumulator;
set lower accumulator to zero; and then go to
location 1009 for the next instruction.”

Good programmers optimized the placement of


instructions on the drum to reduce latency!

September 12, 2005


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The Earliest Instruction Sets


Single Accumulator - A carry-over from the calculators.

LOAD x AC ← M[x]

STORE x M[x] ← (AC)

ADD x AC ← (AC) + M[x]

SUB x
MUL x Involved a quotient register

DIV x
SHIFT LEFT AC ← 2 × (AC)

SHIFT RIGHT
JUMP x PC ← x

JGE x if (AC) ≥ 0 then PC ← x

LOAD ADR x AC ← Extract address field(M[x])

STORE ADR x

Typically less than 2 dozen instructions!


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Programming:
Arvind

Single Accumulator Machine


Ci ← Ai + Bi, 1 ≤ i ≤ n A

LOOP LOAD N B
JGE DONE
ADD ONE
STORE N C
F1 LOAD A
F2 ADD B
F3 STORE C N -n
JUMP LOOP ONE 1
DONE HLT

code

How to modify the addresses A, B and C ?

September 12, 2005


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Self-Modifying Code

LOOP LOAD N Ci ← Ai + Bi, 1 ≤ i ≤ n


JGE DONE
ADD ONE
STORE N
F1
LOAD A Each iteration involves
F2
ADD B total book-
F3
STORE C keeping
JUMP ADR LOOP instruction
LOAD F1
fetches 17 14
DONE HLT
ADD ONE
STORE ADR F1
modify the operand
LOAD ADR F2
program fetches 10 8
ADD ONE
for the next STORE ADR F2
iteration stores 5 4
LOAD ADR F3
ADD ONE
STORE ADR F3
JUMP LOOP
DONE HLT
September 12, 2005
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Processor-Memory Bottleneck: Arvind

Early Solutions
• Fast local storage in the processor
– 8-16 registers as opposed to one accumulator Memory

• Indexing capability
– to reduce book keeping instructions
Processor
• Complex instructions
– to reduce instruction fetches

• Compact instructions
– implicit address bits for operands, to reduce
instruction fetches

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Processor State

The information held in the processor at the end of


an instruction to provide the processing context for
the next instruction.
Program Counter, Accumulator, . . .
Programmer visible state of the processor (and memory)
plays a central role in computer organization for both
hardware and software:

• Software must make efficient use of it

• If the processing of an instruction can be interrupted


then the hardware must save and restore the state in
a transparent manner

Programmer’s machine model is a contract


between the hardware and software
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Index Registers
Tom Kilburn, Manchester University, mid 50’s

One or more specialized registers to simplify


address calculation
Modify existing instructions
LOAD x, IX AC ← M[x + (IX)]
ADD x, IX AC ← (AC) + M[x + (IX)]
...

Add new instructions to manipulate index registers

JZi x, IX if (IX)=0 then PC ← x


else IX ← (IX) + 1
LOADi x, IX IX ← M[x] (truncated to fit IX)
...

Index registers have accumulator-like


characteristics
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Using Index Registers


Ci ← Ai + Bi, 1 ≤ i ≤ n
LOADi -n, IX A
LOOP JZi DONE, IX
LOAD LASTA, IX
ADD LASTB, IX
STORE LASTC, IX
JUMP LOOP LASTA

DONE HALT
• Program does not modify itself
• Efficiency has improved dramatically (ops / iter)

with index regs without index regs


instruction fetch 5(2) 17 (14)
operand fetch 2 10 (8)
store 1 5 (4)
• Costs: Instructions are 1 to 2 bits longer
Index registers with ALU-like circuitry
Complex control
September 12, 2005
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Indexing vs. Index Registers

Suppose instead of registers, memory locations


are used to implement index registers.
LOAD x, IX

Arithmetic operations on index registers can be


performed by bringing the contents to the
accumulator

Most bookkeeping instructions will be avoided but


each instruction will implicitly cause several
fetches and stores

⇒ complex control circuitry

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Operations on Index Registers

To increment index register by k


AC ← (IX) new instruction
AC ← (AC) + k
IX ← (AC) new instruction
also the AC must be saved and restored.

It may be better to increment IX directly


INCi k, IX IX ← (IX) + k

More instructions to manipulate index register

STOREi x, IX M[x] ← (IX) (extended to fit a word)


...

IX begins to look like an accumulator

⇒ several index registers

several accumulators

⇒ General Purpose Registers


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Support for Subroutine Calls

call F F:
a1
Main
a2
Program
Subroutine F

call F
b1 return
b2

A special subroutine jump instruction

M: JSR F F ← M + 1 and
jump to F+1

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Indirect Addressing and


Arvind

Subroutine Calls
Indirect addressing Subroutine
LOAD (x) means AC ← M[M[x]] M+1
F M+2
M+3
...
F+1
Caller
Events:
S1 LOAD (F) fetch
M JSR F Execute M inc F arg
arg
Execute S1
result
Execute S2
M+3
Execute S3 S2 STORE(F)
inc F store
result

Indirect addressing almost eliminates the

need to write self-modifying code (location S3


JUMP (F)
F still needs to be modified)

⇒ Problems with recursive procedure calls


September 12, 2005
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Recursive Procedure Calls and


Reentrant Codes
Indirect Addressing through a register

LOAD R1, (R2)

Load register R1 with the contents of the


word whose address is contained in register R2
memory
registers Pure Code
PC

SP Data

Stack

September 12, 2005


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Evolution of Addressing Modes

1. Single accumulator, absolute address


LOAD x
2. Single accumulator, index registers
LOAD x, IX
3. Indirection
LOAD (x)
4. Multiple accumulators, index registers, indirection
LOAD R, IX, x
or LOAD R, IX, (x) the meaning?
R ← M[M[x] + (IX)]
or R ← M[M[x + (IX)]]
5. Indirect through registers
LOAD RI, (RJ)
6. The works
LOAD RI, RJ, (RK) RJ = index, RK = base addr
September 12, 2005
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Variety of Instruction Formats

• Two address formats: the destination is

same as one of the operand sources

(Reg × Reg) to Reg RI ← (RI) + (RJ)


(Reg × Mem) to Reg RI ← (RI) + M[x]

– x can be specified directly or via a register


– effective address calculation for x could include

indexing, indirection, ...

• Three address formats: One destination and

up to two operand sources per instruction

(Reg x Reg) to Reg RI ← (RJ) + (RK)


(Reg x Mem) to Reg RI ← (RJ) + M[x]

September 12, 2005


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More Instruction Formats


• Zero address formats: operands on a stack
add M[sp-1] ← M[sp] + M[sp-1]
load M[sp] ← M[M[sp]]

– Stack can be in registers or in memory (usually top of


stack cached in registers)

• One address formats: Accumulator machines


– Accumulator is always other implicit operand

Many different formats are possible!

September 12, 2005


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Data Formats and Memory Addresses

Data formats:
Bytes, Half words, words and double words
Some issues
• Byte addressing
Big Endian 0 1 2 3
vs. Little Endian 3 2 1 0

• Word alignment
Suppose the memory is organized in 32-bit words.

Can a word address begin only at 0, 4, 8, .... ?

0 1 2 3 4 5 6 7

September 12, 2005


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Some Problems

• Should all addressing modes be provided for


every operand?
⇒ regular vs. irregular instruction formats

• Separate instructions to manipulate


Accumulators, Index registers, Base registers
⇒ large number of instructions

• Instructions contained implicit memory


references -- several contained more than one
⇒ very complex control

September 12, 2005


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Compatibility Problem at IBM

By early 60’s, IBM had 4 incompatible lines of


computers!
701 → 7094
650 → 7074
702 → 7080
1401 → 7010

Each system had its own

• Instruction set
• I/O system and Secondary Storage:
magnetic tapes, drums and disks
• assemblers, compilers, libraries,...
• market niche
business, scientific, real time, ...

⇒ IBM 360
September 12, 2005
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IBM 360 : Design Premises

Amdahl, Blaauw and Brooks, 1964

• The design must lend itself to growth and


successor machines
• General method for connecting I/O devices
• Total performance - answers per month rather
than bits per microsecond ⇒ programming aids
• Machine must be capable of supervising itself
without manual intervention
• Built-in hardware fault checking and locating aids
to reduce down time
• Simple to assemble systems with redundant I/O
devices, memories etc. for fault tolerance
• Some problems required floating point words
larger than 36 bits

September 12, 2005


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IBM 360: A General-Purpose


Register (GPR) Machine
• Processor State
– 16 General-Purpose 32-bit Registers
• may be used as index and base register
• Register 0 has some special properties
– 4 Floating Point 64-bit Registers
– A Program Status Word (PSW)
• PC, Condition codes, Control flags
• A 32-bit machine with 24-bit addresses

– No instruction contains a 24-bit address !


• Data Formats
– 8-bit bytes, 16-bit half-words, 32-bit words,
64-bit double-words

September 12, 2005


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IBM 360: Implementation

Model 30 ... Model 70


Storage 8K - 64 KB 256K - 512 KB
Datapath 8-bit 64-bit
Circuit Delay 30 nsec/level 5 nsec/level
Local Store Main Store Transistor Registers
Control Store Read only 1µsec Conventional circuits

IBM 360 instruction set architecture completely hid


the underlying technological differences between
various models.

With minor modifications it survives till today

September 12, 2005


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IBM S/390 z900 Microprocessor

• 64-bit virtual addressing


– first 64-bit S/390 design (original S/360 was 24-bit, and
S/370 was 31-bit extension)
• 1.1 GHz clock rate (announced ISSCC 2001)
– 0.18µm CMOS, 7 layers copper wiring
– 770MHz systems shipped in 2000
• Single-issue 7-stage CISC pipeline
• Redundant datapaths
– every instruction performed in two parallel datapaths and
results compared
• 256KB L1 I-cache, 256KB L1 D-cache on-chip
• 20 CPUs + 32MB L2 cache per Multi-Chip Module
• Water cooled to 10oC junction temp

September 12, 2005


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What makes a good instruction set?

One that provides a simple software interface yet


allows simple, fast, efficient hardware
implementations

… but across 25+ year time frame

Example of difficulties:
ƒ Current machines have register files with more storage
than entire main memory of early machines!
ƒ On-chip test circuitry in current machines has hundreds
of times more transistors than entire early computers!

September 12, 2005


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Full Employment for Architects


• Good news: “Ideal” instruction set changes continually
– Technology allows larger CPUs over time
– Technology constraints change (e.g., now it is power)
– Compiler technology improves (e.g., register allocation)
– Programming styles change (assembly, HLL, object-oriented, …)
– Applications change (e.g., multimedia, ....)
– Bad news: Software compatibility imposes huge damping

coefficient on instruction set innovation

– Software investment dwarfs hardware investment


– Innovate at microarchitecture level, below the ISA level (this is
what most computer architects do)
• New instruction set can only be justified by new large market
and technological advantage
– Network processors
– Multimedia processors

– DSP’s

September 12, 2005


Modes d’adressage

⇒ chemin à suivre pour obtenir l’adresse effective

Mode direct ou absolu :


MOVE R1, R2 ; R1 Å (R2)
MOVE R1, 405 ; R1 Å (405)
Mode immédiat :
MOVI R1, 405 ; R1 Å 405
MOVI 103, 405 ; 103 Å 405
Mode indirect :
MOVE R1, @100 ; R1 Å ((100))

Mode indexé :
MOVE R1, 17(R2) ; R1 Å (10 + (R2))
MOVE 1, Table(R2) ; 1 Å (Table + (R2))

Architecture des ordinateurs, M. Eleuldj, EMI, Février 2008 Ch.II. 7


Types de langage machine (1/2)
Considérons l’instruction : A= B + C

Machine à plusieurs opérandes (Vax 11) :


ADDW3 B,C,A ; A Å (B) + (C)

Machine à deux opérandes (PDP 11) :


MOVE B,A ; A Å (B)
ADD C,A ; A Å (B) + (C)

Machine à un opérande (Vax 11)


LDM B ; Charger B dans l’accumulateur
ADD C ; Ajouter C a l’accumulateur
STM A ; Stocker l’accumulateur dans A

Architecture des ordinateurs, M. Eleuldj, EMI, Février 2008 Ch.II. 8


Types de langage machine (2/2)
Considérons l’instruction : A= B + C

Machine à registres (Cyber 170)


EA1 B ; X1 Å (B)
EA2 C ; X2 Å (C)
IX6 X1 + X2 ; X6 Å (X1) + (X2)
SA6 A ; A Å (X6)

Machine à registres (HP 3000)


LOAD B ; mettre B dans la pile
LOAD C ; mettre C dans la pile
ADD ; ajouter les 2 élément au dessus de la pile et mettre
; le résultat sur la pile
STORE A ; 1 Å (Table + (R2))
Architecture des ordinateurs, M. Eleuldj, EMI, Février 2008 Ch.II. 9