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This phase modulation, PM tutorial is split into several pages each of which addresses different
aspects of phase modulation operation and technology:

[1] Frequency synthesizer tutorial

[2] PLL, phase locked loop tutorial
[3] Synthesizer / PLL phase noise
[4] Direct digital synthesizer DDS tutorial
[5] Low phase noise synthesizer design
[6] VCO voltage controlled oscillator design
[7] VCO phase noise
[8] Phase detector
[9] PLL loop filter design

PLL frequency synthesizers are widely used in all forms of radio communications equipment
today. From cellular phones to all forms of wireless products and domestic radios and televisions
to professional radio communications equipment, the local oscillators virtually all use PLL
frequency synthesizers.

PLL frequency synthesizers offer very many advantages over the use of other forms of local
oscillator. Frequency synthesizers not only offer high levels of stability and accuracy
(determined by the reference which is normally a crystal oscillator); they are also easy to control
from digital circuitry such as microprocessors. This enables facilities such as keypad frequency
entry, channel memories and more to be implemented.

In view of all their advantages, PLL frequency synthesizers are usually the preferred form of
local oscillator for most applications. Accordingly synthesizers are included in many radio chip-
sets from cellular phones to radio and televisions.

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Most frequency synthesizers are based around a phase locked loop or PLL. The PLL uses the
idea of phase comparison as the basis of its operation. From the block diagram of a basic loop
shown below, it can be seen that there are three basic circuit blocks, a phase comparator, voltage
controlled oscillator, and loop filter. A reference oscillator is sometimes included in the block
diagram, although this is not strictly part of the loop itself even though a reference signal is
required for its operation.


 








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The phase locked loop, PLL, operates by comparing the phase of two signals. The signals from
the voltage controlled oscillator and reference enter the phase comparator Here a third signal
equal to the phase difference between the two input signals is produced.

The phase difference signal is then passed through the loop filter. This performs a number of
functions including the removal of any unwanted products that are present on this signal. Once
this has been accomplished it is applied to the control terminal of the voltage controlled
oscillator. This tune voltage or error voltage is such that it tries to reduce the error between the
two signals entering the phase comparator. This means that the voltage controlled oscillator will
be pulled towards the frequency of the reference, and when in lock there is a steady state error
voltage. This is proportional to the phase error between the two signals, and it is constant. Only
when the phase between two signals is changing is there a frequency difference. As the phase
difference remains constant when the loop is in lock this means that the frequency of the voltage
controlled oscillator is  the same as the reference.

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A phase locked loop, PLL, needs some additional circuitry if it is to be converted into a
frequency synthesizer. This is done by adding a frequency divider between the voltage controlled
oscillator and the phase comparator as shown below.
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Programmable dividers or counters are used in many areas of electronics, including many radio
frequency applications. They take in a pulse train like that below, and give out a slower train. In
a divide by two circuit only one pulse is given out for every two that are fed in and so forth.
Some are fixed, having only one division ratio. Others are programmable and digital or logic
information can be fed into them to set the division ratio.

 



  

When the divider is added into the circuit the phase locked loop, PLL, still tries to reduce the
phase difference between the two signals entering the 

. Again when the
circuit is in lock both signals entering the comparator are exactly the same in frequency. For this
to be true the voltage controlled oscillator must be running at a frequency equal to the phase
comparison frequency times the division ratio.

It can be seen that if the division ratio is altered by one, then the voltage controlled oscillator will
have to change to the next multiple of the reference frequency. This means that the step
frequency of the synthesizer is equal to the frequency entering the comparator.

Most synthesizers need to be able to step in much smaller increments if they are to be of any use.
This means that the comparison frequency must be reduced. This is usually accomplished by
running the reference oscillator at a frequency of a megahertz or so, and then dividing this signal
down to the required frequency using a fixed divider. In this way a low comparison frequency
can be achieved.
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Placing a digital divider is not the only method of making a synthesizer using a phase locked
loop, PLL. It is also possible to use a mixer in the loop. Using this technique places an offset into
the frequency generated by the loop.

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The way in which the phase locked loop, PLL, operates with the mixer incorporated can be
analyzed in the same manner that was used for the loop with a divider. When the loop is in lock
the signals entering the phase detector are at exactly the same frequencies. The mixer adds an
offset equal to the frequency of the signal entering the other port of the mixer. To illustrate the
way this operates figures have been included. If the reference oscillator is operating at a
frequency of 10 MHz and the external signal is at 15 MHz then the VCO must operate at either 5
MHz or 25 MHz.. Normally the loop is set up so that mixer changes the frequency down and if
this is the case then the oscillator will be operating at 25 MHz.
It can be seen that there may be problems with the possibility of two mix products being able to
give the correct phase comparison frequency. It happens that as a result of the phasing in the
loop, only one will enable it to lock. However to prevent the loop getting into an unwanted state
the range of the VCO is limited. For phase locked loops, PLLs, that need to operate over a wide
range a steering voltage is added to the main tune voltage so that the frequency of the loop is
steered into the correct region for required conditions. It is relatively easy to generate a steering
voltage by using digital information from a microprocessor and converting this into an analogue
voltage using a digital to analogue converter (DAC). The fine tune voltage required to pull the
loop into lock is provided by the loop in the normal way.

 




Many high performance synthesizers use several loops that incorporate both mixers and digital
dividers. By using these techniques it is possible to produce high performance wide range signal
sources with very small step sizes. If only a single loop is used then there may be short falls in
the level of performance.

There is a large variety of ways in which multi-loop synthesizers can be made, dependent upon
the requirements of the individual system. However as an illustration a two loop system used as
an example. This uses one loop to give the smaller steps and the second provides larger steps.
This principle can be expanded to give wider ranges and smaller steps.

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The first phase locked loop, PLL, has a digital divider and operates over the range 19 to 28 MHz.
Having a reference frequency of 1 MHz it provides steps of 1 MHz. The signal from this loop is
fed into the mixer of the second one. The second loop has division ratios of 10 to 19, but as the
reference frequency has been divided by 10 to 100 kHz to give smaller steps.
The operation of the whole loop can be examined by looking at extremes of the frequency range.
With the first loop set to its lowest value the divider is set to 19 and the output from the loop is at
19 MHz. This feeds into the second loop. Again this is set to the minimum value and the
frequency after the mixer must be at 1.0 MHz. With the input from the first loop at 19 MHz this
means that the VCO must operate at 20 MHz if the loop is to remain in lock.

At the other end of the range the divider of the first loop is set to 28, giving a frequency of 28
MHz. The second phase locked loop, PLL, has the divider set to 19, giving a frequency of 1.9
MHz between the mixer and divider. In turn this means that the frequency of the VCO must
operate at 29.9 MHz. As the phase locked loops, PLLs, can be stepped independently it means
that the whole synthesizer can move in steps of 100 kHz between the two extremes of frequency.
As mentioned before this principle can be extended to give greater ranges and smaller steps,
providing for the needs of modern receivers.

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PLL frequency synthesizers are particularly flexible to use and to be controlled by digital
commands. In addition to this they offer many distinct advantages over other forms of local
oscillator for many applications both in radio communications equipment as well as test
equipment, etc. As a result PLL frequency synthesizers are widely used for many RF
applications. Even though other forms of generator including Direct Digital Synthesizers are
available, the PLL based synthesizer is has many advantages, and can often be used in
conjunction with other generators including DDS circuits.

 
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The phase locked loop or PLL is a particularly flexible circuit building block. The phase locked
loop, PLL can be used for a variety of radio frequency applications, and accordingly the PLL is
found in many radio receivers as well as other pieces of equipment.

The phase locked loop, PLL, was not used in early radio equipment because of the number of
different stages required. However with the advent of radio frequency integrated circuits, the
idea of phase locked loops, PLLs, became viable. Initially relatively low frequency PLLs became
available, but as RF IC technology improved, so the frequency at which PLLs would operate
rose, and high frequency versions became available.

Phase locked loops are used ain a large variety of applications within radio frequency
technology. PLLs can be used as FM demodulators and they also form the basis of indirect
frequency synthesizers. In addition to this they can be used for a number of applications
including the regeneration of chopped signals such as the colour burst signal on an analogue
colour television signal, for types of variable frequency filter and a host of other specialist
applications

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The operation of a phase locked loop, PLL, is based around the idea of comparing the phase of
two signals. This information about the error in phase or the phase difference between the two
signals is then used to control the frequency of the loop.

To understand more about the concept of phase and phase difference, first visualise a radio
frequency signal in the form of a familiar x-y plot of a sine wave. As time progresses the
amplitude oscillates above and below the line, repeating itself after each cycle. The linear plot
can also be represented in the form of a circle. The beginning of the cycle can be represented as a
particular point on the circle and as a time progresses the point on the waveform moves around
the circle. Thus a complete cycle is equivalent to 360 degrees. The instantaneous position on the
circle represents the phase at that given moment relative to the beginning of the cycle.

To look at the concept of phase difference, take the example of two signals. Although the two
signals have the same frequency, the peaks and troughs do not occur in the same place. There is
said to be a phase difference between the two signals. This phase difference is measured as the
angle between them. It can be seen that it is the angle between the same point on the two
waveforms. In this case a zero crossing point has been taken, but any point will suffice provided
that it is the same on both.
When there two signals have different frequencies it is found that the phase difference between
the two signals is always varying. The reason for this is that the time for each cycle is different
and accordingly they are moving around the circle at different rates. It can be inferred from this
that the definition of two signals having exactly the same frequency is that the phase difference
between them is constant. There may be a phase difference between the two signals. This only
means that they do not reach the same point on the waveform at the same time. If the phase
difference is fixed it means that one is lagging behind or leading the other signal by the same
amount, i.e. they are on the same frequency.

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A phase locked loop, PLL, is basically of form of servo loop. Although a PLL performs its
actions on a radio frequency signal, all the basic criteria for loop stability and other parameters
are the same.

A basic phase locked loop, PLL, consists of three basic elements:

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  As the name implies, this circuit block within the PLL compares the
phase of two signals and generates a voltage according to the phase difference between
the two signals.
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  This filter is used to filter the output from the phase comparator in the PLL.
It is used to remove any components of the signals of which the phase is being compared
from the VCO line. It also governs many of the characteristics of the loop and its
stability.
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 The voltage controlled oscillator is the circuit
block that generates the output radio frequency signal. Its frequency can be controlled
and swung over the operational frequency band for the loop.

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The concept of the operation of the PLL is relatively simple, although the mathematical analysis
can become more complicated

The Voltage Controlled Oscillator, VCO, within the PLL produces a signal which enters the
phase detector. Here the phase of the signals from the VCO and the incoming reference signal
are compared and a resulting difference or error voltage is produced. This corresponds to the
phase difference between the two signals.
 
 








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The error signal from the phase detector in the PLL passes through a low pass filter which
governs many of the properties of the loop and removes any high frequency elements on the
signal. Once through the filter the error signal is applied to the control terminal of the VCO as its
tuning voltage. The sense of any change in this voltage is such that it tries to reduce the phase
difference and hence the frequency between the two signals. Initially the loop will be out of lock,
and the error voltage will pull the frequency of the VCO towards that of the reference, until it
cannot reduce the error any further and the loop is locked.

When the PLL is in lock a steady state error voltage is produced. By using an amplifier between
the phase detector and the VCO, the actual error between the signals can be reduced to very
small levels. However some voltage must always be present at the control terminal of the VCO
as this is what puts onto the correct frequency.

The fact that a steady error voltage is present means that the phase difference between the
reference signal and the VCO is not changing. As the phase between these two signals is not
changing means that the two signals are on exactly the same frequency.

°

The phase locked loop, PLL, is one of the most versatile building blocks in radio frequency
electronics today. Whilst it was not widely used for many years, the advent of the IC meant that
phase locked loop and synthesizer chips became widely available. This made them cheap to use
and their advantages could be exploited to the full. Nowadays most hi-fi tuners and car radios
use them and a large proportion of the portable radios on the market as well. With their interface
to microprocessors so easy their use is assured for many years to come.

 
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Synthesizer PLL phase noise is a particularly important parameter for any phase locked loop
based frequency synthesizer. Although key parameters like frequency stability, frequency range
and synthesizer step size, and frequency range are widely quoted in specification sheets for
synthesizers, the phase noise is equally important.

The phase noise of a PLL frequency synthesizer is important for many reasons. It affects the
performance of the equipment in which the synthesizer is used in a number of ways.

For signal generators a clean source is needed for the tests in which the generator may be used.

If the frequency synthesizer is used in a radio communications system, then it will affect the
performance of the system. For a radio receiver used in a radio communications system it will
affect parameters such as reciprocal mixing and under some conditions the noise floor.

If the frequency synthesizer is used in a transmitter, then it can cause wide-band noise to be
transmitted and this could cause interference to other users. Accordingly for any radio
communications application, the level of phase noise is important. As the majority of the phase
noise is likely to be generated by the synthesizer, PLL phase noise characteristics are of great
importance.

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Phase noise is present on all signals to some degree and it is caused by small phase (and hence
frequency) perturbations or jitter on the signal. It manifests itself as noise spreading out either
side from the main carrier
Some signal sources are better than others. Crystal oscillators are very good and have very low
levels of phase noise. Free running variable frequency oscillators normally perform well.
Unfortunately synthesizers, and especially those based around phase locked loops, do not always
fare so well unless they are well designed. If significant levels of phase noise are present on a
synthesizer used as a local oscillator in a receiver, it can adversely affect the performance of the
radio in terms of reciprocal mixing.

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Each of the components in a frequency synthesizer produces noise that will contribute to the
overall noise that appears at the output. The actual way in which the noise from any one element
in the loop contributes to the output will depend upon where it is produced. Noise generated by
the VCO will affect the output in a different way to that generated in the phase detector for
example.

To see how this happens take the example of noise generated by the voltage controlled oscillator.
This will pass through the divider chain and appear at the output of the phase detector. It will
then have to pass through the loop filter. This will only allow through those components of the
noise that are below the loop cut-off frequency. These will appear on the error voltage and have
the effect of cancelling out the noise on the voltage controlled oscillator. As this effect will only
take place within the loop bandwidth, it will reduce the level of noise within the loop bandwidth
and have no effect on noise outside the loop bandwidth.

Noise generated by the phase detector is affected in a different way. Again only the components
of the noise below the loop bandwidth will pass through the low pass filter. This means that there
will be no components outside the loop bandwidth appearing on the tune voltage at the control
terminal of the voltage controlled oscillator, and there will be no effect on the oscillator. Those
components inside the loop bandwidth will appear at the oscillator control terminal. These will
affect the oscillator and appear as phase noise on the output of the voltage controlled oscillator.

Matters are made worse by the fact that the division ratio has the effect of multiplying the noise
level. This arises because the synthesizer effectively has the effect of multiplying the frequency
of the reference. Consequently the noise level is also multiplied by a factor of 20 log N, where N
is the division ratio.

Noise generated by the reference undergoes exactly the same treatments as that generated by the
phase detector. It too is multiplied by the division ratio of the loop in the same way that the phase
detector noise is. This means that even though the reference oscillator may have a very good
phase noise performance this can be degraded significantly, especially if division ratios are high.

Dividers normally do not produce a significant noise contribution. Any noise they produce may
be combined with that of the phase detector.
The combined noise of the loop at the output generally looks like that shown in Figure 2. Here it
can be seen that the noise within the loop bandwidth arises from the phase detector and the
reference. Outside the loop bandwidth it arises primarily from the voltage controlled oscillator.
From this it can be seen that optimisation of the noise profile is heavily dependent upon the
choice of the loop bandwidth. It is also necessary to keep the division ratio in any loop down to
reasonable levels. For example a 150 MHz synthesizer with a 12.5 kHz step size will require a
division ratio of 12000. In turn this will degrade the phase detector and reference phase noise
figures by 81 dB inside the loop bandwidth - a significant degradation by anyone's standards!
Provided that division ratios are not too high then a wide loop bandwidth can help keep the
voltage controlled oscillator noise levels down as well.

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PLL phase noise can affect different systems in different ways. However it is important that for
all applications the phase noise on the signal is known and within the required limits. However
phase noise can give rise to a number of different problems:

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  When PLL frequency synthesizers are used within a

transmitter, a local oscillator source with large amounts of phase noise can be radiated
away from the wanted frequency band. This is transmitted as wideband noise and can
cause interference to other users nearby.
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 For transmissions using phase modulation, the phase jitter or
phase noise can cause errors in the reception of the data. PLL phase noise in both the
transmitter and receiver can increase the occurrence of bit errors. It is therefore essential
that the PLL phase noise is kept to acceptable limits within both the transmitter and
receiver.
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   This is a problem that occurs when the phase noise from the local
oscillator signal is superimposed onto a strong off channel signal. This phase noise then
masks out the much lower level weaker signal. Further information on Reciprocal Mixing
can be found from the Radio Receivers menu page.
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Some oscillators have phase noise levels that are quoted in their specifications. Any high quality
signal generator will have the level of phase noise specified, as do many high performance
crystal oscillators used as standards. Their performance is generally specified in dBc/Hz and at a
given offset from the carrier. The term dBc simply refers to the level of noise relative to the
carrier, i.e. -10 dBc means that the level is 10 lower than the carrier.

The bandwidth in which the noise is measured also has to be specified. The reason for this is that
noise spreads over the frequency spectrum. Obviously the wider bandwidth that is used, the
greater the level of noise that will pass through the filter and be measured. To prove this, just try
selecting a different bandwidth on a receiver and check what happens to the noise level. It will
rise for a wider bandwidth and fall when a narrow bandwidth is used. Technically the most
convenient bandwidth to use a 1 Hz bandwidth and so this is used. When measuring this a wider
bandwidth is usually used because it is difficult to obtain 1 Hz bandwidth filters and a correction
is made mathematically.

Finally the level of noise varies as different offsets from the carrier are taken. Accordingly this
must be included in a specification. A very good oscillator might have a specification of -100
dBc/Hz at 10 kHz offset.

It has already been mentioned that the level of phase noise changes as the offset from the carrier
changes and for "simple" signal sources like crystal oscillators or variable frequency oscillators
the phase noise reduces as the frequency from the main carrier is increased. For frequency
synthesizers the picture is a little more complicated as we shall see.

°

PLL phase noise is a particularly important parameter for any synthesizer. It can have a
significant effect on the performance of the system in which it is used whether in a signal
generator, radio communications system, or any other application. Accordingly when designing
or specifying a synthesizer, the PLL phase noise is one of the major parameters that should be
included in the specification from the outset. In this way, the PLL phase noise performance can
be incorporated into the overall design at the earliest stages and no costly rework have to be
undertaken.

 

 

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Direct digital synthesis (DDS) is a powerful technique used in the generation of radio frequency
signals for use in a variety of applications from radio receivers to signals generators and many
more. The technique has become far more widespread in recent years with the advances being
made in integrated circuit technology that allow much faster speeds to be handled which in turn
enable higher frequency DDS chips to be made.

Although often used on its own, Direct Digital Synthesis is often used in conjunction with
indirect or phase locked loop synthesizer loops. By combining both technologies it is possible to
take advantage of the best aspects of each. In view of the fact that integrated circuits are now
widely available, this makes them easy to use.

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As the name suggests this form of synthesis generates the waveform directly using digital
techniques. This is different to the way in which the more familiar indirect synthesizers that use a
phase locked loop as the basis of their operation.

A direct digital synthesizer operates by storing the points of a waveform in digital format, and
then recalling them to generate the waveform. The rate at which the synthesizer completes one
waveform then governs the frequency. The overall block diagram is shown below, but before
looking at the details operation of the synthesizer it is necessary to look at the basic concept
behind the system.

The operation can be envisaged more easily by looking at the way that phase progresses over the
course of one cycle of the waveform. This can be envisaged as the phase progressing around a
circle. As the phase advances around the circle, this corresponds to advances in the waveform.


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The synthesizer operates by storing various points in the waveform in digital form and then
recalling them to generate the waveform. Its operation can be explained in more detail by
considering the phase advances around a circle as shown in Figure 2. As the phase advances
around the circle this corresponds to advances in the waveform, i.e. the greater the number
corresponding to the phase, the greater the point is along the waveform. By successively
advancing the number corresponding to the phase it is possible to move further along the
waveform cycle.

The digital number representing the phase is held in the phase accumulator. The number held
here corresponds to the phase and is increased at regular intervals. In this way it can be sent hat
the phase accumulator is basically a form of counter. When it is clocked it adds a preset number
to the one already held. When it fills up, it resets and starts counting from zero again. In other
words this corresponds to reaching one complete circle on the phase diagram and restarting
again.

 








 
  




Once the phase has been determined it is necessary to convert this into a digital representation of
the waveform. This is accomplished using a waveform map. This is a memory which stores a
number corresponding to the voltage required for each value of phase on the waveform. In the
case of a synthesizer of this nature it is a sine look up table as a sine wave is required. In most
cases the memory is either a read only memory (ROM) or programmable read only memory
(PROM). This contains a vast number of points on the waveform, very many more than are
accessed each cycle. A very large number of points is required so that the phase accumulator can
increment by a certain number of points to set the required frequency.

The next stage in the process is to convert the digital numbers coming from the sine look up table
into an analogue voltage. This is achieved using a digital to analogue converter (DAC). This
signal is filtered to remove any unwanted signals and amplified to give the required level as
necessary.

Tuning is accomplished by increasing or decreasing the size of the step or phase increment
between different sample points. A larger increment at each update to the phase accumulator will
mean that the phase reaches the full cycle value faster and the frequency is correspondingly high.
Smaller increments to the phase accumulator value means that it takes longer to increase the full
cycle value and a correspondingly low value of frequency. In this way it is possible to control the
frequency. It can also be seen that frequency changes can be made instantly by simply changing
the increment value. There is no need to a settling time as in the case of phase locked loop based
synthesizer.

From this it can be seen that there is a finite difference between one frequency and the next, and
that the minimum frequency difference or frequency resolution is determined by the total number
of points available in the phase accumulator. A 24 bit phase accumulator provides just over 16
million points and gives a frequency resolution of about 0.25 Hz when used with a 5 MHz clock.
This is more than adequate for most purposes.

These synthesizers do have some disadvantages. There are a number of spurious signals which
are generated by a direct digital synthesizer. The most important of these is one called an alias
signal. Here images of the signal are generated on either side of the clock frequency and its
multiples. For example if the required signal had a frequency of 3 MHz and the clock was at 10
MHz then alias signals would appear at 7 MHz and 13 MHz as well as 17 MHz and 23 MHz etc..
These can be removed by the use of a low pass filter. Also some low level spurious signals are
produced close in to the required signal. These are normally acceptable in level, although for
some applications they can cause problems.

 
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Phase noise in PLL frequency synthesizers if of great importance because it determines many
factors about the equipment into which it is incorporated. For receivers it determines the
reciprocal mixing performance, and in some circumstances the bit error rate. In transmitters the
phase noise performance of the frequency synthesizer determines features such as adjacent
channel noise and it contributes to the bit error rate for the whole system.

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Phase noise is generated at different points around the synthesizer loop and depending upon
where it is generated it affects the output in different ways. For example, noise generated by the
VCO has a different effect to that generated by the phase detector. This illustrates that it is
necessary to look at the noise performance of each circuit block in the loop when designing the
synthesizer so that the best noise performance is obtained.

Apart from ensuring that the noise from each part of the circuit is reduced to an absolute
minimum, it is the loop filter which has the most effect on the final performance of the circuit
because it determines the break frequencies where noise from different parts of the circuit start to
affect the output.

To see how this happens take the example of noise from the VCO. Noise from the oscillator is
divided by the divider chain and appears at the phase detector. Here it appears as small
perturbations in the phase of the signal and emerges at the output of the phase detector. When it
comes to the loop filter only those frequencies which are below its cut-off point appear at the
control terminal of the VCO to correct or eliminate the noise. From this it can be seen that VCO
noise which is within the loop bandwidth is attenuated, but that which is outside the loop
bandwidth is left unchanged.

The situation is slightly different for noise generated by the reference. This enters the phase
detector and again passes through it to the loop filter where the components below the cut-off
frequency are allowed through and appear on the control terminal of the VCO. Here they add
noise to the output signal. So it can be seen that noise from the reference is added to the output
signal within the loop bandwidth but it is attenuated outside this.

Similar arguments can be applied to all the other circuit blocks within the loop. In practice the
only other block which normally has any major effect is the phase detector and its noise affects
the loop in exactly the same way as noise from the reference. Also if multi-loop synthesizers are
used then the same arguments can be used again.

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As noise is generated at different points around the loop it is necessary to discover what effect
this has on the output. As a result it is necessary to relate all the effects back to the VCO. Apart
from the different elements in the loop affecting the noise at the output in different ways, the
effect of the multiplication in the loop also has an effect.

The effect of multiplication is very important. It is found that the level of phase noise from some
areas is increased in line with the multiplication factor (i.e. the ratio of the final output frequency
to the phase comparison frequency). In fact it is increased by a factor of 20 log10 N where N is
the multiplication factor. The VCO is unaffected by this, but any noise from the reference and
phase detector undergoes this amount of degradation. Even very good reference signals can be a
major source of noise if the multiplication factor is high. For example a loop which has a divider
set to 200 will multiply the noise of the reference and phase detector by 46 dB.

From this information it is possible to build up a picture of the performance of the synthesizer.
Generally this will look like the outline shown in Fig. 6. From this it can be seen that the noise
inside the loop bandwidth is due mainly to components like the phase detector and reference,
whilst outside the loop the VCO generates the noise. A slight hump is generally seen at the point
where the loop filter cuts off and the loop gain falls to unity.

By predicting the performance of the loop it is possible to optimise the performance or look at
areas which can be addressed to improve the performance of the whole synthesizer before the
loop is even built. In order to analyse the loop further it is necessary to look at each circuit block
in turn.

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The noise performance of the oscillator is of particular importance. This is because the noise
performance of the synthesizer outside the loop is totally governed by its performance. In
addition to this its performance may influence decisions about other areas of the circuit.

The typical noise outline for a VCO is flat at large frequency offsets from the carrier. It is
determined largely by factors such as the noise figure of the active device. The performance of
this area of the oscillator operation can be optimised by ensuring the circuit is running under the
optimum noise performance conditions. Another approach is to increase the power level of the
circuit so that the signal to noise ratio improves.
Closer in the noise starts to rise, initially at a rate of 20 dB per decade. The point at which this
starts to rise is determined mainly by the Q of the oscillator circuit. A high Q circuit will ensure a
good noise performance. Unfortunately VCOs have an inherently low Q because of the Q of the
tuning varactors normally employed. Performance can be improved by increasing the Q, but this
often results in the coverage of the oscillator being reduced.

Still further in towards the carrier the noise level starts to rise even faster at a rate of 30 dB per
decade. This results from flicker or 1/f noise. This can be improved by increasing the level of
low frequency feedback in the oscillator circuit. In a standard bipolar circuit a small un-bypassed
resistor in the emitter circuit can give significant improvements.

To be able to assess the performance of the whole loop it is necessary to assess the performance
of the oscillator once it has been designed and optimised. Whilst there are a number of methods
of achieving this the most successful is generally to place the oscillator into a loop having a
narrow bandwidth and then measure its performance with a spectrum analyser. By holding the
oscillator steady this can be achieved relatively easily. However the results are only valid outside
the loop bandwidth. However a test loop is likely to have a much narrower bandwidth than the
loop being designed the noise levels in the area of interest will be unaltered.

'

The noise performance of the reference follows the same outlines as those for the VCO, but the
performance is naturally far better. The reason for this is that the Q of the crystal is many orders
of magnitude higher than that of the tuned circuit in the VCO.

Typically it is possible to achieve figures of -110 dBc/Hz at 10 Hz from the carrier and 140
dBc/Hz at 1 kHz from a crystal oven. Figures of this order are quite satisfactory for most
applications. If lower levels of reference noise are required these can be obtain, but at a cost. In
instances where large multiplication factors are necessary a low noise reference may be the only
option. However as a result of the cost they should be avoided wherever possible. Plots of typical
levels of phase noise are often available with crystal ovens giving an accurate guide to the level
of phase noise generated by the reference.

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Divider noise appears within the loop bandwidth. Fortunately the levels of noise generated
within the divider are normally quite low. If an analysis is required then it will be found that
noise is generated at different points within the divider each of which will be subject to a
different multiplication factor dependent upon where in the divider it is generated and the
division ratio employed from that point.
Most divider chains use several dividers and if an approximate analysis is to be performed it may
be more convenient to only consider the last device or devices in the chain as these will
contribute most to the noise. However the noise is generally difficult to measure and will be seen
with that generated by the phase detector.

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Like the reference signal the phase detector performance is crucial in determining the noise
performance within the loop bandwidth. There are a number of different types of phase detector.
The two main categories are analogue and digital.

Mixers are used to give analogue phase detectors. If the output signal to noise ratio is to be as
good as possible then it is necessary to ensure that the input signal levels are as high as possible
within the operating limits of the mixer. Typically the signal input may be limited to around -10
dBM and the local oscillator input to +10 dBm. In some instances higher level mixers may be
used with local oscillator levels of +17 dBm or higher. The mixer should also be chosen to have
a low NTR (noise temperature ratio). As the output is DC coupled it is necessary to have a low
output load resistance to prevent a backward bias developing. This could offset the operation of
the mixer and reduce its noise performance.

It is possible to calculate the theoretical noise performance of the mixer under optimum
conditions. An analogue mixer is likely to give a noise level of around -153 dBc/Hz.

There are a variety of digital phase detectors which can be used. In theory these give a better
noise performance than the analogue counterpart. At best a simple OR gate type will give figures
about 10 dB better than an analogue detector and an edge triggered type (e.g. a dual D type or
similar) will give a performance of around 5 dB better than the analogue detector.

These figures are the theoretical optimum and should be treated as guide although they are
sufficient for initial noise estimates. In practice other factors may mean that the figures are
different. A variety of factors including power supply noise, circuit layout etc. can degrade the
performance from the ideal. If very accurate measurements are required then results from the
previous use of the circuit, or from a special test loop can provide the required results.


 

There are a variety of parameters within the area of the loop filter which affect the noise
performance of the loop. The break points of the filter and the unity gain point of the loop
determined by the filter govern the noise profile.

In terms of contributions to the noise in the loop the major source is likely to occur if an
operational amplifier is used. If this is the case a low noise variety must be used otherwise the
filter will give a large contribution to the loop phase noise profile. This noise is often viewed as
combined with that from the phase detector, appearing to degrade its performance from the ideal.

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Having investigated the noise components from each element in the loop, it is possible to
construct a picture of how the whole loop will perform. Whilst this can performed
mathematically, a simple graphical approach quickly reveals an estimate of the performance and
shows which are the major elements which contribute to the noise. In this way some re-design
can be undertaken before the design is constructed, enabling the best option to be chosen on the
drawing board. Naturally it is likely to need some optimisation once it has been built, but this
method enables the design to be made as close as possible beforehand.

First it is necessary to obtain the loop response. This is dependent upon a variety of factors
including the gain around the loop and the loop filter response. For stability the loop gain must
fall at a rate of 20 dB per decade (6 dB per octave) at the unity gain point. Provided this criterion
is met a wide variety of filters can be used. Often it is useful to have the loop response rise at a
greater rate than this inside the loop bandwidth. By doing this the VCO noise can be attenuated
further. Outside the loop bandwidth a greater fall off rate can aid suppress the unwanted
reference sidebands further. From a knowledge of the loop filter chosen the break points can be
calculated and with a knowledge of the loop gain the total loop response can be plotted.

With the response known the components from the individual blocks in the loop can be added as
they will be affected by the loop and seen at the output.

First take the VCO. Outside the loop bandwidth its noise characteristic is unmodified. However
once inside this point the action of the loop attenuates the noise, first at a rate of 20 dB per
decade, and then at a rate of 40 dB per decade. The overall affect of this is to modify the
response of the characteristic as shown in Fig. 10. It is seen that outside the loop bandwidth the
noise profile is left unmodified. Far out the noise is flat, but further in the VCO noise rises at the
rate of 20 dB per decade. Inside the loop bandwidth the VCO noise will be attenuated first at the
rate of 20 dB per decade, which in this case gives a flat noise profile. Then as the loop gain
increases at the filter break point, to 40 dB per decade this gives a fall in the VCO noise profile
of -20 dB per decade. However further in the profile of the stand alone VCO noise rises to -30dB
per decade. The action of the loop gives an overall fall of -10 dB per decade.

The effects of the other significant contributions can be calculated. The reference response can
easily be deduced from the manufacturers figures. Once obtained these must have the effect of
the loop multiplication factor added. Once this has been calculated the effect of the loop can be
added. Inside the loop there is no effect on the noise characteristic, however outside this
frequency it will attenuate the reference noise, first at a rate of 20 dB per decade and then after
the filter break point at 40 dB per decade.
The other major contributor to the loop noise is the phase detector. The effect of this is treated in
the same way as the reference, having the effect of the loop multiplication added and then being
attenuated outside the loop bandwidth.

Once all the individual curves have been generated they can be combined onto a single plot to
gain a full picture of the performance of the synthesizer. When doing this it should be
remembered that it is necessary to produce the RMS sum of the components because the noise
sources are not correlated.

Once this has been done then it is possible to optimise the performance by changing factors like
the loop bandwidth, multiplication factor and possibly the loop topology to obtain the best
performance and ensure that the required specifications are met. In most cases the loop
bandwidth is chosen so that a relatively smooth transition is made between the noise
contributions inside and outside the loop. This normally corresponds to lowest overall noise
situation.

°

Although this approach may appear to be slightly "low tech" in today's highly computerised
engineering environment it has the advantage that a visual plot of the predicted performance can
be easily put together. In this way the problem areas can be quickly identified, and the noise
performance of the whole synthesizer optimised before the final design is committed.

 
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Within a phase locked loop, PLL, or frequency synthesizer, the performance of the voltage
controlled oscillator, VCO is of paramount importance. This is because the VCO Voltage
Controlled Oscillator performance determines many of the overall performance characteristics of
the overall synthesizer.

In order that the PLL or synthesizer can meet its full specification a well designed voltage
controlled oscillator is essential. Designing a really high performance voltage controlled
oscillator, VCO, is not always easy as there are a number of requirements that need to be met.
However by careful design, and some experimentation a good VCO design can be developed.

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Just like any other circuit, with a VCO there are a number of design requirements that need to be
known from the beginning of the design process. These basic requirements for the VCO will
govern many of the decisions concerning the circuit topology and other fundamental aspects of
the circuit. Some of the basic requirements are:<.p>

m Tuning range
m Tuning gain - tuning shift for a given tuning voltage change
m Phase noise (low phase noise)

These are some of the main requirements that need to be known from the outset of the design of
the VCO. The overall tuning range and the gain are basic requirements that are part of the basic
design of any PLL into which the VCO may be incorporated. So too is the phase noise
characteristic. As phase noise is a basic parameter of any PLL or frequency synthesizer, so too is
the characteristic of the VCO, and low phase noise VCOs are often required. For example the
VCO performance may govern the overall design of the frequency synthesizer or PLL, if a given
phase noise performance is to be met.

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Like any oscillator, a VCO may be considered as an amplifier and a feedback loop. The gain of
the amplifier may be denoted as A and the feedback as B.
For the circuit to oscillate the total phase shift around the loop must be 360 degrees and the gain
must be unity. In this way signals are fed back round the loop so that they are additive and as a
result, any small disturbance in the loop is fed back and builds up. In view of the fact that the
feedback network is frequency dependent, the build up of signal will occur on one frequency, the
resonant frequency of the feedback network, and a single frequency signal is produced.

Many oscillators and hence VCOs use a common emitter circuit. This in itself produces a phase
shift of 180 degrees, leaving the feedback network to provide a further 180 degrees.

Other oscillator or VCO circuits may use a common base circuit where there is no phase shift
between the emitter and collector signals (assuming a bipolar transistor is used) and the phase
shift network must provide either 0 degrees or 360 degrees.

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Two commonly used examples of VCO circuits are the Colpitts and Clapp oscillators. Of the
two, the Colpitts circuit is the most widely used, but these circuits are both very similar in their
configuration.

These circuits operate as oscillators because it is found that a bipolar transistor with capacitors
placed between the base and emitter (C1) and the emitter and ground (C2) fulfils the criteria
required for providing sufficient feedback in the correct phase to produce an oscillator. For
oscillation to take place the ratio C1: C2 must be greater than one.

The resonant circuit is made by including a inductive element between the base and ground. In
the Colpitts circuit this consists of just an inductor, whereas in the Clapp circuit an indictor and
capacitor in series are used.

The conditions for resonance is that:

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The capacitance for the overall resonant circuit is formed by the series combination of the two
capacitors C1 and C2 in series. In the case of the Clapp oscillator, the capacitor in series with the
inductor is also included in series with C1 and C2.

Thus the series capacitance is:

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In order to make the oscillator tune it is necessary to vary the resonant point of the circuit. This is
best achieved by adding a capacitor across the indictor in the case of the Colpitts oscillator.
Alternatively for the Clapp oscillator, it can be the capacitor in series with the inductor.
For high frequency applications a circuit where the inductive reactance is placed between the
base and ground is often preferred as it is less prone to spurious oscillations and other anomalies.

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It is possible to use both bipolar devices and FETs within a VCO, using the same basic circuit
topologies. The bipolar transistor has a low input impedance and is current driven, while the FET
has a high input impedance and is voltage driven. The high input impedance of the FET is able to
better maintain the Q of the tuned circuit and this should give a better level of performance in
terms of the phase noise performance where the maintenance of the Q of the tuned circuit is a
key factor in the reduction of phase noise.

Another major factor is the flicker noise generated by the devices. Oscillators are highly non-
linear circuits and as a result the flicker noise is modulated onto VCO as sidebands and this
manifests itself as phase noise. In general bipolar transistors offer a lower level of flicker noise
and as a result VCOs based around them offer a superior phase noise performance.

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To make a VCO, the oscillator needs to be tuned by a voltage. This can be achieved by making
the variable capacitor from varactor diodes. The tune voltage for the VCO can then be applied to
the varactors.

When varactor diodes are used, care must be taken in the design of the circuit to ensure that the
drive level in the tuned circuit is not too high. If this is the case, then the varactor diodes may be
driven into forward conduction, reducing the Q and increasing the level of spurious signals.

There are two main types of varactor diode that may be used within a VCO: abrupt and hyper-
abrupt diodes. The names refer to the junction within the diode. The abrupt ones do not have a
sharp a transition between the two semiconductor types in the diode, and this affect the
performance offered.

Hyper-abrupt diodes have a relatively linear voltage : capacitance curve and as a result they offer
a very linear tuning characteristic that may be required in some applications. They are also able
to tune over a wide range, and may typically tune over an octave range with less than a 20 volt
change in tuning voltage. However they do not offer a particularly high level of Q. As this will
subtract from the overall Q of the tuned circuit this will mean that the phase noise performance is
not optimum.

Abrupt diodes, while not offering such a high tuning range or linear transfer characteristic are
able to offer a higher Q. This results in a better phase noise (i.e. low phase noise) performance
for the VCO. The other point to note is that they may need a high tuning voltage to provide the
required tuning range, as some diodes may require a tuning voltage for the VCO to vary up to 50
volts or slightly more.

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The design of a VCO voltage controlled oscillator can be interesting and challenging. Whether
the aim is to design a low noise VCO, a low current VCO, a PLL VCO, or one that will cover a
wide tuning range there are many aspects that need to be addressed. Often when a successful
design has been obtained, it will slightly modified to enable it to cover a wide range of similar
applications.

 
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VCO phase noise is a key parameter in the voltage controlled oscillator used for applications
including use in frequency synthesizers for radio receivers, transmitters and RF signal
generators. VCO phase noise is a key specification parameter for any VCO design as the phase
noise performance of a VCO will affect the overall performance of the system in which the
oscillator is located.

Poor levels of VCO phase noise can manifest themselves in different ways. For an analogue
radio receiver a poor performance oscillator may result in poor reciprocal mixing performance. It
may also raise the noise floor of the receiver. In a radio system relying on phase modulation,
phase noise will degrade the bit error rate performance.

For transmitters, a poor level of phase noise performance will result in noise being transmitted
beyond the required transmit band, causing interference to users on other frequencies. Again it
can result in poor levels of bit error rate in a radio communications system.

Additional RF signal generators will look for as "clean" a signal as possible. Phase noise if a key
parameter for the performance of the signal generator, and in turn the VCO phase noise
performance is elemental in determining areas of the overall phase noise performance.

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Phase noise is present on all signal sources to a greater or lesser degree. Some forms of oscillator
are better than others, those that use higher Q circuits and have smaller tuning ranges tend to
offer a better phase noise performance, however the requirements for VCOs tend to require wide
tuning ranges, and this makes their design more challenging.

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Phase noise consists of small random perturbations in the phase of the signal, i.e. phase jitter. An
ideal signal source would be able to generate a signal in which the phase advanced at a constant
rate. This would produce a single spectral line on a perfect spectrum analyzer. Unfortunately all
signal sources produce some phase noise or phase jitter, and these perturbations manifest
themselves by broadening the bandwidth of the signal.

Click on the link for a Phase Noise tutorial

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To ensure that a design provides the optimum VCO phase noise performance, there are a number
of key points that can be followed in the design. These will help ensure that the design is able to
provide a high level of VCO phase noise performance, although even when the design ahs been
realised, there is still likely to be some optimisation required to provide the best performance.

m Ö   

 
 One of the major factors in determining the VCO phase noise
performance is the Q of the resonant circuit. Broadly, the higher the Q of the oscillator
tuned circuit, the better the VCO phase noise performance. Thus inductors should be
chosen to provide the highest Q, as should the capacitors. This is particularly true of
voltage controlled oscillators, VCOs where the varactor diodes normally employed have
a lower Q than other capacitors.

Typically high Q tuned circuits do not have the tuning range of lower Q circuits. This
means that when wide tuning ranges are required, it becomes more difficult to obtain a
high level of Q and hence the optimum phase noise.

As an illustration of the effect of having a high Q resonant circuit in an oscillator, crystal

oscillators exhibit very low levels of phase noise as a result of the fact that the crystals
used in them possess very high levels of Q.
m   

   It is possible to use both bipolar devices and FETs within
an RF oscillator, using the same basic circuit topologies. The bipolar transistor has a low
input impedance and is current driven, while the FET has a high input impedance and is
voltage driven. The high input impedance of the FET is able to better maintain the Q of
the tuned circuit and this should give a better level of performance in terms of the phase
noise performance where the maintenance of the Q of the tuned circuit is a key factor in
the reduction of phase noise. That said, many bipolar transistor designs are able to offer
excellent phase noise performance.

Another major factor is the flicker noise generated by the devices. Oscillators are highly
non-linear circuits and as a result the flicker noise is modulated onto the oscillation as
sidebands. This manifests itself as VCO phase noise. In general bipolar transistors offer a
lower level of flicker noise and as a result oscillators based around them often offer a
superior phase noise performance.
m  

 A critical feature in any oscillator design is to ensure that the
correct level of feedback is maintained. There should be sufficient to ensure that
oscillation is maintained over the frequency range, over the envisaged temperature range
and to accommodate the gain and parameter variations between the devices used.
However if the level of feedback is too high, then the level of VCO phase noise will also
be increased. Thus the circuit should be designed to provide sufficient feedback for
reliable operation and little more.
m °  
 

  

 It is found that the noise floor of an oscillator is
reasonably constant in absolute terms despite the level of the output signal. In some
 designs there can be improvements in the overall signal to noise floor level to be made by
using a high level signal and applying this directly to the mixer or other circuit where it
may be required. Accordingly some low noise circuits may use surprisingly high
oscillator power levels.
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 It is necessary to ensure that any supply line or other extraneous
noise is not presented to the oscillator. Supply line ripple, or other unwanted pickup can
seriously degrade the performance of the oscillator. To overcome this, good supply
smoothing and regulation is absolutely necessary. Additionally it may be advisable to
place the oscillator within a screened environment so that it does not pick up any stray
noise. It is worth remembering that the oscillator acts as a high gain amplifier, especially
close to the resonant frequency. Any noise picked up can be amplified and will manifest
itself as VCO phase noise.

°

There are many elements to ensuring that VCO phase noise performance can be optimised. With
phase noise being a key parameter in many situations, it is essential that the VCO phase noise
performance meets its requirements. In this way, the performance of the overall system will not
be degraded by the VCO phase noise performance.

 
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The phase detector is the core element of a phase locked loop, PLL. Its action enables the phase
differences in the loop to be detected and the resultant error voltage to be produced.

There is a variety of different circuits that can be used as phase detectors, some that use what
may be considered as analogue techniques, while others use digital circuitry. However the most
important difference is whether the phase detector is sensitive to just phase or whether it is
sensitive to frequency and to phase. Thus phase detectors may be split into two categories:

m Phase only sensitive detectors

m Phase - frequency detectors

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Phase detectors that are only sensitive to phase are the most straightforward form of detector.
They simply produce an output that is proportional to the phase difference between the two
signals. When the phase difference between the two incoming signals is steady, they produce a
constant voltage. When there is a frequency difference between the two signals, they produce a
varying voltage. In fact the simplest form of phase only sensitive detector is a mixer. From this it
can be seen that the output signal will be have sum and difference signals.

The difference frequency product is the one used to give the phase difference. It is quite possible
that the difference frequency signal will fall outside the pass-band of the loop filter. If this occurs
then no error voltage will be fed back to the Voltage Controlled Oscillator (VCO) to bring it into
lock. This means that there is a limited range over which the loop can be brought into lock, and
this is called the capture range. Once in lock the loop can generally be pulled over a much wider
frequency band.

To overcome this problem the oscillator must be steered close to the reference oscillator
frequency. This can be achieved in a number of ways. One is to reduce the tuning range of the
oscillator so that the difference product will always fall within the pass-band of the loop filter. In
other instances another tune voltage can be combined with the feedback from the loop to ensure
that the oscillator is in the correct region. This is approach is often adopted in microprocessor
systems where the correct voltage can be calculated for any given circumstance.

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Another form of detector is said to be phase-frequency sensitive. These circuits have the
advantage that whilst the phase difference is between +/- 180 a voltage proportional to the phase
difference is given. Beyond this the circuit limits at one of the extremes. In this way no AC
component is produced when the loop is out of lock and the output from the phase detector can
pass through the filter to bring the phase locked loop, PLL, into lock.

 
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The design of the PLL, loop filter is crucial to the operation of the whole phase locked loop. The
choice of the circuit values here is usually a very carefully balanced compromise between a
number of conflicting requirements.

The PLL filter is needed to remove any unwanted high frequency components which might pass
out of the phase detector and appear in the VCO tune line. They would then appear on the output
of the Voltage Controlled Oscillator, VCO, as spurious signals. To show how this happens take
the case when a mixer is used as a phase detector. When the loop is in lock the mixer will
produce two signals: the sum and difference frequencies. As the two signals entering the phase
detector have the same frequency the difference frequency is zero and a DC voltage is produced
proportional to the phase difference as expected. The sum frequency is also produced and this
will fall at a point equal to twice the frequency of the reference. If this signal is not attenuated it
will reach the control voltage input to the VCO and give rise to spurious signals.

When other types of phase detector are used similar spurious signals can be produced and the
filter is needed to remove them.

The filter also affects the ability of the loop to change frequencies quickly. If the filter has a very
low cut-off frequency then the changes in tune voltage will only take place slowly, and the VCO
will not be able to change its frequency as fast. This is because a filter with a low cut-off
frequency will only let low frequencies through and these correspond to slow changes in voltage
level.

Conversely a filter with a higher cut-off frequency will enable the changes to happen faster.
However when using filters with high cut-off frequencies, care must be taken to ensure that
unwanted frequencies are not passed along the tune line with the result that spurious signals are
generated.

The loop filter also governs the stability of the loop. If the filter is not designed correctly then
oscillations can build up around the loop, and large signals will appear on the tune line. This will
result in the VCO being forced to sweep over wide bands of frequencies. The proper design of
the filter will ensure that this cannot happen under any circumstances.