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Chapter Outline
• Basic Microsequencer Design
• Very Simple Microsequencer
• Relatively Simple Microsequencer
• Reducing the Number of
Microinstructions
• Microcoded vs. Hardwired Control
• Pentium Microprocessor
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Micro--stuff
Micro
‘Registers and data paths are the
same as before’
• Micro
Micro--operations (register transfers)
• Microinstructions ((μ
μ-operations +
sequencing information)
Generic Microsequencer
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Microinstruction Format
SELECT: Indicates the source of the next address
(absolute or a derived address)
p
ADDR: Specifies an absolute address
μ‐OPERATIONS: lists the μ‐OPS to be carried out
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Types of Microcode
• Horizontal (a bit is allocated in the
microinstruction for each μ-OP of the
processor) – could be long
long, only one/a
few are used at a time, 16 μ-Ops =>
• Vertical ((μ-Ops are grouped and
assigned a code) 16 μ-Ops =>
H & V need control signals to be derived
from μ-Ops
• Direct
Di t ((stores
t the
th control
t l signals,
i l suchh
as -ld, inc,.. in memory-
memory- and directly
generates them)
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FETCH1: AR ← PC
FETCH2: DR ← M,
M PC ← PC + 1
FETCH3: IR ← DR[7..6], AR ← DR[5..0]
ADD1: DR ← M
ADD2: AC ← AC + DR
AND1: DR ← M
AND2: AC ← AC ^ DR
JMP1: PC ← DR[5..0]
INC1: AC ← AC + 1
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State Assignments
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Mapping Logic
State Addresses
State Address
FETCH1 0000 (0)
FETCH2 0001 (1)
FETCH3 0010 (2)
ADD1 1000 (8)
ADD2 1001 (9)
AND1 1010 (10)
AND2 1011 (11)
JMP1 1100 (12)
INC1 1110 (14)
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FETCH1: AR ← PC
FETCH2: DR ← M,
M PC ← PC + 1
FETCH3: IR ← DR[7..6], AR ← DR[5..0]
ADD1: DR ← M
ADD2: AC ← AC + DR
AND1: DR ← M
AND2: AC ← AC ^ DR
JMP1: PC ← DR[5..0]
INC1: AC ← AC + 1
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Micro--operations
Micro
Mnemonic Micro-
Micro-Operation
ARPC ARÅ
AR ÅPC
ARDR ARÅ
AR ÅDR[5..0]
PCIN PCÅ
PC ÅPC + 1
PCDR PCÅ
PC ÅDR[5..0]
DRM DRÅ
DRÅM
IRDR IRÅ
IRÅDR[7..6]
PLUS ACÅ
AC ÅAC + DR
AND ACÅ
AC ÅAC^DR
ACIN ACÅ
AC ÅAC + 1
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Control Signals
‘Derived from the RTL code of all the states’
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Control Signals
Regroup
g p operations
p by
y destination
“AR” ARÅ
AR ÅPC; ARÅ
ARÅDR[5..0]
“PC” PCÅPC + 1; PCÅ
PCÅ PCÅDR[5..0]
“DR” DRÅM
DRÅ
“IR” IRÅDR[7..6]
IRÅ
“AC” ACÅAC + DR; ACÅ
ACÅ ACÅAC^DR; ACÅ
ACÅAC + 1
Control Signals
Savings in logic:
DRLOAD,
MEMBUS
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• Simultaneous micro-
micro-operations in
different fields
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• Simultaneous micro-
micro-operations in
different fields
• Include a NOP in each field
• Simultaneous micro-
micro-operations in
different fields
• Include a NOP in each field
• Group together micro-
micro-operations that
modify
od y the e same
sa e register
eg s e
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• Simultaneous micro-
micro-operations in
different fields
• Include a NOP in each field
• Group together micro-
micro-operations that
modify
od y the e same
sa e register
eg s e
• Distribute remaining micro-
micro-operations to
minimize total number of bits required
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Micro--operations
Micro
Mnemonic Micro-
Micro-Operation
ARPC ARÅ
AR ÅPC
AIDR ARÅ
AR ÅDR[5..0]
PCIN PCÅ
PC ÅPC + 1
PCDR PCÅ
PC ÅDR[5..0]
DRM DRÅ
DR ÅM
PLUS ACÅ
AC ÅAC + DR
AND ACÅ
AC ÅAC^DR
ACIN ACÅ
AC ÅAC + 1
Micro--operation Assignments
Micro
M1 M2
NOP NOP
DRM PCIN
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Micro--operation Assignments
Micro
M1 M2
NOP NOP
DRM PCIN
ACIN PCDR
PLUS ARPC
AND AIDR
(Data related) (Address related)
Micro--operation Assignments
Micro
M1 M2
NOP NOP
DRM PCIN
ACIN PCDR
PLUS ARPC
AND
AIDR
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Micro--operation Assignments
Micro
and Field Values
Vertical Microcode
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Micro--operation Generation
Micro
Nanoinstructions
128 μ-instructions with 32 μ-
operations need 128*32bits.
16 unique combinations: nano-
memory 16*32,
Access these 16 locations
using 4-bits.
Microcode memory is then
128*4
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Relatively Simple
Microsequencer
• No changes to
– Instruction set
– Data paths
– ALU
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State Assignments
Mapping:IR
[
[3..0]00
]
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Microsequencer Hardware
Three sources of
next address
->
> larger mux
mux.,
To support
conditional jump,
‘+1’ circuit is
necessary
Error in figure?
Condition Values
Condition
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Branch Types
Branch Logic
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Micro--operations
Micro
‘22-bits for them’
Horizontal Microcode
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Horizontal Microcode
Horizontal Microcode
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Control Signals
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Microsubroutines
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Microsequencer with
Microsubroutines
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Revised Microcode
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Microcode Jumps
‘Sharing states under certain condition’
Revised Microcode
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Control Signals
‘Derived from the RTL code of all the
states’
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Summary
• Basic Microsequencer Design
• Very Simple Microsequencer
• Relatively Simple Microsequencer
• Reducing the Number of
Microinstructions
• Microcoded vs. Hardwired Control
• Pentium Microprocessor
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Address Register
Carry Sum
Final Product
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Data
Read Mask Register
Write
Data Register
Match
Memory Register
Output Register
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