8051 Tutorial

 
Scope
This tutorial is one of a series designed to summarise the main features of a microcontroller
CPU family so that engineers familiar with the general principles of embedded micro
development can rapidly evaluate the 8051 family to determine its suitability for a new
project.

Introduction
The 8051 is one of the most popular 8 bit microcontrollers and combines an instruction set
that allows tight coding of small, particularly I/O intensive, application with enough power and
a large enough program space that it can be used with C.  It can address 128K of external
memory and has a basic instruction time of 1 microsecond ( at 12 MHz) although modern
examples may achieve 40 instructions per microsecond running at 40 MHz
Introduced in 1980 the 8031 and 8051 chips were actually a significant upgrade of the 8048
(1976) and was itself enhancements to become the 8052 and subsequently released in
CMOS as the 80C52 (1986). This Micro family is unusual in that Intel have licensed the
architectures design to a significant number of manufacturers each of which has then
created multiple variants ( with their own numbering conventions).  There are now over 1,100
different 8051 variants from 55 different manufacturers and in order to assist you in finding
the best fit to your project details of all these are available in a searchable form on our 8051
Micro-Search  database. You may see all of these referred to generically as members of the
8051 family.
 

Memory and I/O

The 8051 family can address bytes in separate 64Kbyte code (read only) and 64Kbyte data
(read/write) spaces,  these may be internal to the chip or external or a combination of the
two.  It is possible to wire up a system so that these data spaces overlap giving a single 64K
space - this keeps the design simple and also allows a debug monitor to download code and
set software breakpoints into the RAM space greatly simplifying debugging in the absence of
an ICE.
If it is to be used off-chip memory is accessed via up to 20 pins.  Up to 8 address high pins
and then always 8 pins that are used for both the 8 address low signals during the address
setup phase and for the 8 data signals during the data transfer phase.  4 pins are used for
control.
Internal Memory
The original 8031/8051 chip provides 128 bytes of on-chip R/W memory, the 8052 has
increased this to 256 bytes. This memory is used to provide:-
Four banks of eight 8 bit Registers ( the active bank being selected by two bits in the PSW)
16 Bytes (128 bits) for which individual bits may be set, tested and cleared with a single
instruction
Variable space - especially if no off-chip RAM is included in the design
A stack which grows upwards and whose size is limited to the lesser of  the remaining
internal memory or 256.
        this stack may not extend to off-chip memory and is used as a return stack for function
calls and for interrupt handling
        Many C compilers also use the stack for function arguments in which case the basic
allowance is soon used up
Two of these registers R0 and R1 have special properties as they can be used as pointers
into memory .

I/O
I/O ports and peripherals will appear as one or more registers in the 128 Special Function
Register (SFR) space. Single instructions can read write registers or set/clear/test single bits
in all the standard 8051 chips I/O registers
The basic 8051 has a UART, four 8 bit I/O registers and two 16 bit internal counters ( which
have a number of ways in which they will operate).  In order to minimise pin count some of
the I/O bits have multiple but exclusive functions, for example:
18 bits are used to create the external memory and data bus if required.
2 bits provide UART signals if used and 4 bits may be inputs for 2 external interrupts and 2
counts.  Hence a system that required all these resources would be left with only 8 bits of
spare I/O.
You may interface your applications registers directly to the chips I/O ports or may memory
map them using the multiplexed address and data bus but if that bus is not required for
RAM/ROM then its only worth doing this if you need to interface more than the 18 bits that
the bus consumes.
 

Addressing modes
Now how can you get at this memory and I/O.....?   the answer is that if you want to get at
single variables, be they bits or bytes, its easy but its a lot more complex if you need to get at
large buffers or arrays.
Direct Addressing
OPCODE XXX
<----------- Byte ---------> <---- 8 or 16 --->  The address to be referenced is built into the instruc
Depending on the instruction this address can reference a:
1) Byte within the SFR (if value of  XXX is 128 -> 255)
2) Bit within the SFR (if value of  XXX is 128 -> 255)
3) Byte within the lower 128 bytes of Internal RAM (if value  of  XXX is 0 -> 127)
4) Bit within the Bit address area ( if value  of  XXX is 0 -> 127)
Register Indirect Addressing
OPCODE REG
<-------------------------- Byte
--------------------->
 
1) Registers R0, R1 or SP can point at any location in Internal Data Memory
2) Registers R0 or R1 can point at a location in the bottom 256 bytes of the External Data
Memory
3) DPTR can point at any location in External Data Memory
Base + Index
 The Address  = Contents of DPTR or PC + Contents of Accumulator
 

Instruction Set
The 8051 family's instruction set consists of single byte OP-CODE followed by 0/1/2 bytes
with immediate data or an 8 or 16 bit address.  Instructions take 12  clock cycles (60% of
them) or 24 clock cycles.
While only having 33 instructions the variety of different addressing modes means that
depending on which variant of the move instruction is used MOV? R1,XXX then the XXX can
refer to;  a location in the 256 Internal Memory,  to the I/O ports or to the bottom 256 bytes of
External RAM.  In some instructions the contents of certain Registers may act as 8 bit
pointers to 256 of the external or internal memory bytes. There are significant restrictions on
which addressing modes each instruction type can use ( in the jargon it does not have a
symmetrical instruction set), so its difficult to summarise the instruction set in a few words, it
takes 40 page to specify it.   This then is a personal brief summary trying to highlight its
strengths and weaknesses.
Lets call            the  8 bit Accumulator   AC         the 8 Active Registers  REG     
                          the I/O ports   SFR                     the bottom 256 bytes of the External
Memory   EXM
                          the Internal Memory INT ( the bottom half is easily addressed - the top half, if
it exists, sometimes requires a fiddle )
                          an address held in the 16 bit data pointer can be the source or destination of
some instructions  (DPTR)
 
Single instructions may..........
INC and DEC the AC or one of the REG, SFR, INT and (DPTR) locations.
Logical 8 bit AND  OR  XOR can be done between source( AC, REG, SFR, INT, immediate
value ) and, with the destination being overwritten, destination( AC, I/O, INT ).
8 bit BCD and unsigned Byte arithmetic takes place between the AC and as source( REG,
SFR, INT, immediate value ) with the result returned in the AC.
An 8 bit by 8 bit unsigned multiply with a 16 bit result as well as an 8 bit divided by 8 bit
instruction can only be done between a set register and AC (take 48 clock cycles).
An area of the on-chip memory (16 bytes, 128 bits) can have individual bits set, cleared,
tested, complimented and AND/ORed with the Carry bit in a single instruction which is very
useful as low overhead flags. 
The variants on the move instruction are the most diverse but can be summarised ........
Source( AC, REG, SFR, EXM, immediate value or (DPTR)) and destination( AC, REG, SFR,
EXM or (DPTR) ) but there are some invalid combinations and its never possible to have the
same class as source and destination - so no  move R4,R5  or  from SFR to SFR  these
must take two instructions and go via AC or a register. 
Control instructions
Jumps and Calls with 16 bit addresses allow control to pass to any part of the 64K code
space.  11 bit Jumps and Calls provide compatibility with the 8048 and efficient movement
within a 2K module. Fast conditional Jumps are possible +/- 128 bytes of the current address
and a Jump is provide that adds the AC to the contents of the DPTR to provide vectored
jump tables.
 
Good things about the instruction set........
Most of the above operations use 1 or 2 bytes for an instruction so are fast and compact
Manipulation of bits and bytes is easy
I/O and the on-chip 128 or 256 of RAM are easily and quickly read and written
So writing in assembler can create very compact code that handles I/O well
Bad things about this.......
Its not a very clean assembler to come to terms with if you are new to writing assembler
code
The need to do all arithmetic via the Accumulator can be a significant bottleneck
Careful control and usage of the Registers is necessary
Handling large programs and large numbers of arrays, or large sized arrays is difficult and
may be best left to a C compiler
If you are using other than byte length variables speed will go down
But on balance its probably no more idiosyncratic than other 8 bit CPUs designed as an I/O
controller and to be low cost
 

Interrupts
The basic 8051 provides a non-maskable Reset signal and individually vectored interrupts at
two priority levels with two off-chip and three on-chip sources.

Power consumption
The original HMOS 8051 consumed (worst case) 160 mAmps at 12 MHz and 5v. The
present generation of CMOS 80C52 consume 30 mAmps (at 12Mhz).  Modern designs
optimised for minimum power consumption are available that consume as little as 1 mAmp
and run at 2 volts.
In addition where power consumption is a problem the 80C52 and many variants allow the
programmer to adopt a number of power saving strategies ranging from stopping CPU
execution but preserving the registers (returning to normal execution on receipt of an
interrupt) to also turning off the on-chip RAM and/or the peripherals.

Pinouts
Two pinouts of the 80C51 have become "standard" and as enhancements tend to be
implemented as alternative functions of I/O pins these layouts have stuck. These are the 40
pin DIP and the 44 pin PLCC (the images below shows a variant with extra Interrupts INT3-5
and a second UART mapped optionaly to I/O ports).  Depending on the application area the
chip is targeted at and the I/O that needs to be accessed packages for 8051 variants can
have anything between 8 and 144 pins.

As you can see most pins have alternate functions

Pn.m is bit m of port n       A is Address     AD is the multiplexed lower Address and Data
 

Performance
The original 8051 operated at 12MHz and took 12 cycles to execute a single instruction that
would set or clear a single bit in a register (1 µSec)  or 2 µSec to move an indexed byte from
external memory to the Accumulator. To give an example of a more complex sequence if we
wish to create a general routine to move a string of n bytes from one area of external RAM to
another then the setup takes ~65 µSec and each byte needs ~11 µSec.
However, the current generation has improved performance by both increasing the operating
frequency to 40MHz and by reducing the number of cycles required for an instruction to 1 or
2. Hence potentially increasing the speed of instruction execution from 1 per micro second to
one every 25 nano seconds.
 

Enhancement
The 8051 is without doubt the CPU family with the most variants on the market; as we said
above we know of over 1,100 different 8051 variants from 55 different manufacturers. A
consequence of this variety is that there was no central manufacturers web site to which you
could go when designing a system in order to choose the most suitable 8051 chip. It was
with this problem in mind that we created our 8051 Micro-Search  database please visit it if
you need to explore the diversity of this microcontroller family.  
Below are some of the more common enhancements:
When the 8051 was introduced the only memory options available were 4K of ROM or
EEPROM and 128 bytes on-chip RAM.  Technology has moved on allowing Flash memory of
64K or more and with RAM of 2K or 4K being common.
The 8052 and variants based on it include an additional counter (now 3) and increase the
stack space to 256 bytes - any additional RAM is mapped to look like external memory -  so
unfortunately 4K RAM does not result in 4K of stack.
Some designers provide additional data pointers to speed up array moves.
Some provide additional counters and timers for pulse width modulated and stepper motor
control.
Enhanced mathematical performance is also available from 16 bit multiply/divide to floating
point support.
Then there are variants with support for specific I/O such as A/D, D/A, LED and LCD drivers
as well as protocol such as I²C, SPI, CAN, USB and even Ethernet.
The full range of enhancements we have identified when creating our 8051 database can be
viewed here
Another option that is available for high volume applications is to incorporate the 8051 core
as the processing power of a custom design. Of course you could do this via Intel or one of
the other major manufacturers if your volume and influence were such as to get their
attention but there are also a number of small foundries and FPGA manufacturers who have
8051 licences or IP that can be incorporated - see our list of  8051 IP Cores.
 

Cost
A common 8052 with no on-chip program storage can be purchased from RS for £1.20 in
100 off  (Oct06).  
80p for 100 off buys an 8 pin single chip system with 1K of flash suitable for very small
applications.
For £1.46 at 100 off its possible to get a 38 pin package with 768 bytes RAM and 16K of
Flash, enhanced timers and A/D suitable for quite significant single chip applications.
As usual volume will reduce these prices but the higher the amount of memory, the greater
the pin out and the more specialised the peripherals the greater the costs will be.
 

Development Tools
The 8051 itself provides very little in the way of development support - if one of the external
interrupts is free the CPU can be made to run in single step mode and by overlapping the
code and data space a software monitor can run the code under test in RAM inserting
software interrupts to create breakpoints.  The hardware development tool of choice is
undoubtedly the In Circuit Emulator (ICE), however, the diversity of 8051 variants is such
that availability or not of a suitable ICE could dominate the chip selection process.
Assemblers and more commonly C Compilers are readily available and some of these have
target monitors or simulators which may assist in developing code for single chip devices.
Development libraries are available to support Real Time Executives, TCP/IP stacks and
Flash file systems.