4G Terminals: How are We Going

to Design Them?

Jan Craninckx and Stéphane Donnay

IMEC, Leuven, Belgium
4G Wireless World

llite Ce
ate ork WLAN ne llula
S tw two r
ne rk
Ad-hoc
network

WBAN
Too Many Radio Standards…
l GSM (850/900/1800/1900)
l IS-95
l UMTS
l 4G
l DECT
l 802.11b/a/g
l Bluetooth
l DAB, DVB
l WBAN
l …
Software-Defined Radio
l The ultimate goal might be a “Software Radio”
¤ A-to-D conversion at the antenna…

ADC

DIGITAL
DAC

¢ ADC : 10GS/s, >10bit

¢ Digital processing : ??Gops
¢ Power consumption : >>10W

l Not very realisitic

¤ Even in 2010…
Software-Defined Radio
l So we need a reconfigurable radio

LNA VGA ADC

DIGITAL
PLL
I/Q

PA DAC
Software-Defined Radio
l So we need a reconfigurable radio

LNA VGA ADC

DIGITAL
PLL
I/Q

PA DAC

l Every block should adapt its performance towards the

standard requirements
¤ Center frequency, signal bandwidth, noise, linearity, …
Outline
l System-on-Chip integration
¤ Cost impact
¤ Substrate noise
l System-in-Package design
¤ Technology
¤ Design tools
l System-level architecture trade-offs
¤ Digital compensation techniques
¤ Analog/digital co-simulation
System-on-Chip Integration
l Technology : plain CMOS
¤ + extra process options:
¢ Thick oxide transistors
¢ Dual-VT option
¢ HIPO or MOPO resistors
¢ Poly/Poly or MiM capacitors
¢ Triple-well
¢ Flash memory
¤ increased silicon cost
l Cost is more than mm2
¤ Packaging
¤ Test
¤ Yield
¤ Power consumption
¤ (Re)Design time
¤ Substrate noise [Van Zeijl et al., JSSC Dec. ’02]
Substrate Noise
l Substrate noise is a potential threat to SoC
¤ Digital switching generates >100mV bounce on power and
ground lines
¤ This also ends up in the common substrate…
l 3 Steps in substrate noise
¤ Generation
¤ Propagation
¤ Impact

l Generation
¤ Spice simulation
¢ Only for small problems
¤ Simple macromodel
¢ 100kgates = 1 big inverter
Substrate Noise Generation
l Substrate noise Waveform ANalysis (SWAN):
Ipower [mA] Inoise [uA]
0.4 10
D Q
0.0 5

CP QN
-0.4 0
C
-0.8 -5
[van Heijningen et al.,
-1.2 -10
DAC 2000] 0.0 0.5 1.0 1.5 2.0 0.0 0.5 1.0 1.5 2.0
time [ns] time [ns]

l Predicts substrate voltage fast and accurate

Vsub [mV]
40
measurement

20

-20

simulation

20

0 [Badaroglu et al.,
-20 JSSC July 2003]
-40
12.55 12.60 12.65 12.70 12.75
time [us]
Impact on analog (RF) circuits
l 0.25um CMOS LNA
¤ Substrate coupling is mostly
through input transistor

20

-20
dB
TF in → out
-40

-60
TF sub → out

-80
0 2 4 6 8 10
freq. (GHz)
System-in-a-Package Integration
l SoC is not the Holy Grail
¤ CMOS for everything has a performance cost
l Perfect trade-off : optimal technology for every function
¤ High-quality passives for RF
¤ High-frequency silicon technology for radio transceivers
¤ Advanced CMOS for digital
¤ Memory ICs
l Thin-film MCM technology CHIP

C
L
BCB
R Gla ss
SiP Demonstrator
Integrated Patch Antenna RF filters

BiCMOS
IC

Commercial GaAs Switch

Commercial GaAs PA
SiP Demonstrator : BGA Technology
l Glass is a bad thermal conductor
¤ PA on BGA
l Antenna requires thick dielectric
¤ laminate
SiP Demonstrator

[Ryckaert et al.,
IMS 2003]
System-Level Design Issues
l Radio link budget analysis
¤ First-order approximations : A, NF, IP3, …
¢ Spreadsheet
¤ More accurate : simulation of SNR / SDR / BER
¢ Mixed RF/analog/digital simulation tool

l RF simulation techniques
¤ Harmonic balance
¤ Transient-based
l Modeling new components
¤ MEMS: mechanical!
l Cost/performance models
¤ Which technology for which function?
¢ Cost: Area, BOM, design time
¢ Gain: Performance, power
System-Level Architecture Trade-Offs
l The analog world is not perfect…
¤ Analog non-idealities severely impact the radio performance

LNA VGA ADC

DIGITAL
PLL
I/Q

PA DAC

Noise

Linearity Phase noise

DC-offsets

I/Q mismatch
Digital Compensation Techniques
l Can substantially alleviate the analog requirements
¤ DC-offset compensation for zero-IF receivers
¤ Predistortion for PA linearity
¤ Quadrature error correction for image rejection
¤ Common phase noise compensation
l Should be considered immediately during the system-level
design
¤ Digital cost
¢ Number of operations, latency, …
¤ Analog gain
¢ Area, power, yield, …
Digital Compensation Techniques
l Example : I/Q mismatch and common phase noise in a zero-
IF WLAN receiver
¤ 10% ampl.
mismatch
¤ 10º phase
mismatch
¤ -32dBc in-
band phase
noise

[Tubbax et al., VTC 2003]

High-Level Co-Simulation
l 3 parts to simulate:
¤ Large digital block
¢ MHz
¤ Low-frequency analog
¢ MHz
¤ RF analog
¢ GHz

l Mixed-signal loops
¢ kHz !

l Speed-up the simulation of the RF nonlinear circuits : FAST

¤ Analog block becomes a computational graph
¤ Efficient signal representation
¢ Multi-Carrier Multi-Rate (MCMR)
FAST
l Front-end Architecture Simulator for digital Telecom
applications
l High-level model of analog circuits
¤ Avoid iterative solving of nonlinear differential equations
¤ Computational graph to improve simulation speed
¢ (non-linear) S-parameters
¢ Volterra series
Vcc
Ha (s)
input
R3
L output
T1
In
Hb(s) x2 K2gm3 +
Out Hd(s)
T2
R1 R2
T3
+ Hc(s)
C

x3 K3gm3

l Multi-Rate Multi-Carrier signal representation

¤ Limits the number of timepoints to calculate
[Vandersteen et al., DAC 2000]
FAST/OCAPI Co-Simulation
Radio
OFDM Channel Model
Modulator
Matlab
Nonlinear
Power Amplifier FAST
Test signal FAST/OCAPI
generator OCAPI Co-Simulation

System Simulation
parameters results

Digital Specs
met?
Analog/RF Non-ideal
zero-IF receiver
Environment
Equalizer/Decoder

[Eberle et al., DATE 2003]

FAST/OCAPI Co-Simulation : Example
l Zero-IF receiver : AGC and DC-offset algorithm
¤ Full end-to-end model 0
¢ Mixed A/D TX 10
¢ Channel model -2 BER
10
¢ Mixed A/D RX
-4
¢ RF VGA model : 10
xy21
50
Estimated Signal Power
u v
x1
a21 b21
y2 0 in dB
a11 a22 b11 y2’ NonLin .
w -50
x2
a12 ?n1 ? @ f c 1
yx21 ?n ? @ 2 f RF VGA
? 2? c High gain Setting
c1 0.5
c21 ?? 3 ??
n @ 3 f c

Low gain
¤ Simulation speed 0

¢ 25sec for 80k payload bits 10

Baseband
VGA Setting
l Efficient exploration of the 0

design space -10

-100 -50 0 50
relative RF input power level in dB
Conclusions
l There’s still a lot of work to do!
l Technology
¤ SoC has its limitations
¤ SiP could solve them
¤ Digital compensation techniques can overcome (some of) the
analog limitations
l Design tools
¤ For building blocks
¤ For the complete system
¢ Mixed digital/analog/RF co-simulation