R 15

Code No: A27AF

B V R AJ U I N S T I T U T E O F T E C H N O L O G Y , N A RSA P U R
(UGC AUTONOMOUS)
B.Tech III Year I Semester Regular/Supplementary Examinations, Nov/Dec 2019
EMBEDDED SYSTEMS
(OPEN ELECTIVE)
Scheme of Evaluation

total
Q.NO PART A Marks marks
allocated
2
The stage of the design methodology would determine what type of
2
1.a CPU to use 2 *1
1.b Classify embedded systems based on complexity and performance
Three types 1 *0.5 2
List the types 3 *0.5
1.c the role of watch dog timer in embedded systems any two 2 *1 2
1.d device driver definition 1 *1 2
Its importance 1 *1
1.e details about PSW register in 8051
2
Four sentences 4 *0.5
1.f MOV instruction 1 *1
2
MOVX instruction 1 *1
1.g the files generated during cross-compilation.
2
Four files each carries 0.5 mark 4 *0.5
1.h Semaphore definition 1 *1
2
Its variants 1 *1
1.i List out the features of SHARC processor
2
Any for features 4 *0.5
1.j two applications of I2C protocol
2
two applications 2 *1
PART-B
2.a top-down and bottom-up design: diagram 1 *1
Requirements 2 *1
Specifications 2 *1
10
Architecture 2 *1
components 2 *1
System intigration 1 *1
OR
3 neat design layout of the model train controller: diagram 2 *1
requirements 4 *1 10
specifications 4 *1
4.a Block diagram’s serial & parallel 2 *1
5
explanation 3 *1
4.b Block diagram 2 *1
5
explanation 3 *1
OR
“data transmission”, “data reception” scenarios of serial driver along
5 with its neat flow-chart representation
Serial transmission diagram 2 *1 10
Flow chart 3 *1
explanation 5 *1

6.a principle operation of 8051 microcontroller : neat diagram 2 *1

5
principle operation 3 *1
6.b a program to convert ASCII digit ‘5’ 2.5 *1
5
e a program to convert ASCII digit ‘8’ 2.5 *1
OR
7.a Timer modes of operation in 8051 microcontroller
5
Timer modes table/figure 2 *1
explantion 3 *1
5
7.b Programming steps: 7 steps 5 *1
8 What is the shared data problem 2 *1
10
solutions to avoid shared data problem 8 *1
OR
9 Debugging definition 2 *1
10
debugging techniques 8 *1

10.a the thumb mode of ARM processor explanation 5 *1

5
10.b instruction-level parallelism with example.
explanation 2 *1
5
explanation with example. 3 *1
OR

11.a uses of CAN protocols 5 *1 10

CAN bus communication process 5 *1

Prepared by
P.Rajesh
Asst.Professor
Department of Electronics and Communication Engineering