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# EECE 412: Digital Integrated Circuits

## Lecture 2: Design Metrics

R. Kanj
Dept. of Electrical and Compute Engineering
American University of Beirut

## [Slides adapted from Prof. M. Mansour, I. Kayssi, A. Chehab,

Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al, and from the
slides of Profs. Irwin and Vijay at PSU]

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Fundamental Design Metrics

 Cost \$\$
 Non Recurring Engineering cost (fixed)
- design effort
 Recurring Engineering cost (variable)
- cost of parts, assembly, test

##  Robustness and Reliability

 Noise margins
 Noise immunity

 Performance
 Speed (delay)
 Power consumption: energy

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Cost of Integrated Circuits
 NRE (non-recurring engineering) costs
 Fixed cost to produce the design
 Influenced by the design complexity and designer productivity
 More pronounced for small volume products

##  Recurring costs – proportional to product volume

 Fabrication: From silicon to chip
 assembly (packaging)
 test

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Cost per IC: \$\$

NRE cost
cost per IC = RE cost per IC + -----------------
# functional chips

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Silicon Wafer

Wafer

Single die

test

Packaged chip

From http://www.amd.com
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Recurring Costs

cost of wafer
cost of die fabrication = -----------------------------------
dies per wafer × die yield

##  × (wafer diameter/2)2  × wafer diameter

dies per wafer = ----------------------------------  ---------------------------
die area ( 2 × die area )

## O= defect (e.g. dust particle) 6

Yield Calculation


 defects per unit area  die area 
die yield  1  
  
D  A   is approximately 3
Y  (1  )

100
Yield (%)
80

60

40

20

0 1 2 3 4 5

DxA
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Yield Example

 Example
 wafer diameter 30 cm, die area of 2.5 cm2, 1 defects/cm2,
 = 3 (measure of manufacturing process complexity)
 240 dies/wafer (remember, wafers round & dies square)
 die yield of 16%
 240 x 16% = only 38 dies/wafer die yield !

## Die cost is strong function of die area:

Calls for minimizing area: simple regular gates

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Examples of Cost Metrics (1994)

## Chip Metal Line Wafer Defects Area Dies/ Yield Die

layers width cost /cm2 (mm2) wafer cost
386DX 2 0.90 \$900 1.0 43 360 71% \$4
486DX2 3 0.80 \$1200 1.0 81 181 54% \$12
PowerPC 4 0.80 \$1700 1.3 121 115 28% \$53
601
HP PA 3 0.80 \$1300 1.0 196 66 27% \$73
7100
DEC 3 0.70 \$1500 1.2 234 53 19% \$149
Alpha
Super 3 0.70 \$1700 1.6 256 48 13% \$272
SPARC
Pentium 3 0.80 \$1500 1.5 296 40 9% \$417

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Now that my chip is fabricated

## For functional chips concerns include:

- Robustness to noise
- Speed consideration
- Power consumption
VDD

0 1

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Robustness and Reliability in Digital IC

 Noise
 Definition: unwanted variations of voltages and currents
at the logic nodes
 Where can noise come from on a chip?

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Robustness and Reliability

##  from two wires placed side by side

 capacitive coupling
v(t)
- voltage change on one wire can
influence signal on the neighboring wire
- cross talk
i(t)
 inductive coupling
- current change on one wire can
influence signal on the neighboring wire
 resistive coupling

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Robustness and Reliability

##  from noise on the power and ground supply rails

 can influence signal levels in the gate

VDD

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Example of Capacitive Coupling
 Signal wire glitches as large as 80% of the supply
voltage will be common due to crosstalk between
neighboring wires as feature sizes continue to scale

Pulsed Signal
0.12um CMOS
0.16um CMOS

## Black line quiet

Red lines pulsed 0.25um CMOS
Glitche strength vs technology 0.35um CMOS

## From Dunlop, Lucent, 2000

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Static Gate Behavior
 Steady-state behavior of a gate – static behavior – tell
how robust a circuit is with respect to noise disturbances.

##  Digital circuits perform operations on Boolean variables

x {0,1}
 A logical variable is associated with a nominal voltage
level for each logic state
1  VOH and 0  VOL

VOH = ! (VOL)
Vin Vout
VOL = ! (VOH)

##  Difference between VOH and VOL is the logic or signal

swing Vsw 15
DC Operation
Voltage Transfer Characteristics (VTC)

## Vout Vin Vout

VOH = f (VOL)
Vout=Vin

Switching Threshold
VM

VOL = f (VOH)

## VOL VOH Vin

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Mapping Logic Levels to the Voltage Domain

##  Acceptable ‘1’ and ‘0’ voltages are delimited by VIH and

VIL that represent points on the VTC curve where the
gain (dVout/dVin) = -1
 Logic ‘1’: [ VIH, VOH] Logic ‘0’: [VOL, VIL]

Vout
"1" VOH Slope = -1
VOH
VIH

Undefined
Region
Slope = -1
VIL
VOL
"0" VOL
VIL VIH Vin
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Noise Margins
 For robust circuits, that tolerate noise, want the “0” and
“1” intervals to be as large as possible
VDD VDD

VOH "1"
NMH = VOH - VIH
VIH
Noise Margin High Undefined
Region
Noise Margin Low VIL
NML = VIL - VOL
VOL
"0"
Gnd Gnd
Gate Output Gate Input

##  Large noise margins are desirable, but not sufficient …

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The Regenerative Property
 A gate with regenerative property ensure that a disturbed
signal converges back to a nominal voltage level (e.g.
0V, 5V)

v0 v1 v2 v3 v4 v5 v6

v2
5
V (volts)

v0
3

1 v1

-1
0 2 4 6 8 10
t (nsec)
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Conditions for Regeneration
good Low

Distorted Low v0 v1 v2 v3 v4 v5 v6

v1 = f(v0)

f(v) f(v)

v1

good Low
v2

v0 v1
Distorted Low

Regenerative Gate

##  To be regenerative, the VTC must have a transition

region with a gain greater than 1 (in absolute value)
bordered by two valid zones where the gain is smaller
than 1.
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Noise Immunity
 Noise margin expresses the ability of a circuit to
overpower a noise source
 Absolute noise margin values are deceptive
 a floating node is more easily disturbed than a node driven by a
low impedance (in terms of voltage)

##  Noise immunity is the capability to suppress noise

sources
 expresses the ability of the system to process and transmit
information correctly in the presence of noise

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Directivity

##  A gate must be undirectional: changes in an output level

should not appear at any unchanging input of the same
circuit
 Key metrics: output impedance of the driver and input
 ideally, the output impedance of the driver should be zero
 input impedance of the receiver should be infinity

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The Ideal Inverter
 The ideal gate should have
 infinite gain in the transition region
 a gate threshold located in the middle of the logic swing
 high and low noise margins equal to half the swing
 input and output impedances of infinity and zero, resp.
Vout

Ri = 

Ro = 0

g=- Fanout = 

## NMH = NML = VDD/2

Vin
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Fan-In and Fan-Out

##  Fan-out – number of load gates

connected to the output of the
driving gate
 gates with large fan-out are slower
N

##  Fan-in – the number of inputs to

the gate M
 gates with large fan-in are bigger
and slower

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Performance Metrics - Delay Definitions

Vin Vout

Vin
Propagation delay
input 50% tp = (tpHL + tpLH)/2
waveform

t
tpHL tpLH
Vout
90%
output
50% signal slopes
waveform
10%
t
tf tr

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Modeling Propagation Delay
 Model circuit as first-order RC network

## vout (t) = (1 – e–t/)V

R
vout
where  = RC

vin C
Time to reach 50% point is
t = ln(2)  = 0.69 

## Time from 10% to 90% point is

t = ln(9)  = 2.2 

##  First order model of a gate

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Ring Oscillator

T = 2  tp  N

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Power and Energy Dissipation
 Power consumption: how much energy is consumed
per operation and how much heat the circuit dissipates
 supply line sizing (determined by peak power)
Ppeak = Vddipeak
 battery lifetime (determined by average power dissipation)
p(t) = v(t)i(t) = Vddi(t) Pavg= 1/T  p(t) dt = Vdd/T  idd(t) dt
 packaging and cooling requirements

##  Two important components:

 dynamic power
 Charging and discharging of capacitors
 Temporary path between supply rails

 static power
 Independent of switching activity

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Summary

##  Digital integrated circuits have come a long way and

still have quite some good potential left for the coming