Three-Dimensional SVM for Modular Power Electronics Systems
P. Rodríguez, J. Pou, A. Luna , D. Ghizoni*, J. Guo*, G. Francis*, R. Burgos*, and D. Boroyevich*
Power Quality and Renewable Energy (QuPER)
Departments of Electrical and Electronic Engineering
Technical University of Catalonia
EUETIT, Colom 1, 08222 – Barcelona - SPAIN
prodriguez@ee.upc.edu
Abstract-Space vector modulation (SVM)⎯based on the
explicit control of converter switching states⎯is not the most
suitable approach for the modulation of modular power
electronics systems due to its apparent lack of modeling
flexibility. This paper addresses this issue by presenting a new
analytical standpoint for the analysis of SVM in modular power
conversion systems, namely power electronics building blocks
(PEBB) -based systems. Specifically, the paper presents a
mathematically and physically sound modulation technique for
PEBB-based converters developed by means of a three-
dimensional (3D) space-vector representation. As a result, a
processing efficient three-dimensional space-vector modulation
algorithm is proposed (3D-SVM). The algorithm itself rests on
the well-known carrier-based pulse width modulation
technique, therefore it does not require any trigonometric
calculations, definitions of optimal sequences, and direct control
over the switching states of the three-phase converter. The
proposed 3D-SVM technique is verified by simulation and
experimental results obtained with a three-phase power
converter using 33kW IGBT-based PEBB modules.
I. INTRODUCTION
Space-vector modulation (SVM) is an advanced technique
for the generation of output voltages or currents in three-
phase inverters based on the spatial visualization of their
variables [1]. In the conventional approach of this technique,
the inverter is understood as a whole, allowing full control
over the switching sequences of the switches and achieving
maximum use of the dc-link voltage. Usually, SVM analysis
uses Clarke’s transformation to describe mathematically the
modulation process, which yields a two-dimensional (2D)
representation of the space vector variables (using the well
known αβ plane). The origin of this standpoint comes from
three-phase motor drive applications, in which the zero-
sequence current is usually zero. This constrained view
however gives rise to a misinterpretation of the modulation
process, which complicates the extension of conventional
SVM technique toward more complex converter structures,
for example, four-legged inverters.
Since the conventional SVM technique is based on a
centralized control of the switching states of the inverter, its
usage in modular power electronics requires a complete re-
design of the modulator and associated algorithms. Such is
the case studied in this paper, where each leg of the inverter
is implemented by means of a power electronics building
block (PEBB). Each inverter PEBB, or phase-leg, works as a
self-sufficient power processing unit, where the duty-cycle is
its main control variable and the sensed ac current and dc
voltage its main feedback variables. The PEBB definition is a
smart power processing unit capable of performing different
0-7803-9252-3/05/$20.00 ©2005 IEEE
* Center for Power Electronics Systems (CPES)
Department of Electrical and Computer Engineering
Virginia Polytechnic Institute and State University
Blacksburg, VA 24061 - USA
rp.burgos@ieee.org
power electronics functions while communicating with its
peers [2]. The output voltage of each PEBB is synthesized by
means of carrier-based modulation.
When three PEBBs are arranged as a three-phase full-
bridge inverter, the standard carried-based sinusoidal PWM
(SPWM) technique can be used to synthesize the three-phase
output voltage. In SPWM, the switching pattern can be
modified by slopes variation in the carrier signal of the
PEBBs. However, the inverter only operates in linear mode
when the modulation index is m ∈ [0L1] . As it is well-
known, the linear region of the SPWM can be extended
further by the addition of a zero-sequence signal (ZSS) to the
sinusoidal references (ZSS-PWM) [3].
In 1974, K. G. King [4] proposed an analog technique to
*
obtain the zero-sequence signal ( v ZSS ) to be subtracted from
a set of generic references ( v Fan , v *Fbn , v *Fcn ) in order to
*
achieve the maximum use of the dc-link voltage. This simple
technique yields the following well known expression:
*
v ZSS =
1
2
{ ( *
max v Fan *
, v Fbn *
, v Fcn ) (
+ min v *Fan , v Fbn
*
, v *Fcn )} (1)
The modulation technique based on this optimal zero-
sequence signal achieves the same results as the conventional
SVM technique using symmetrical placement of the zero
vectors in each switching period. This approach however
does not use any trigonometric calculations, switching
sequence arrangement, or switching intervals control [5].
Eq. (1) can be easily implemented in a modular power
electronics system based on PEBBs. Some relatively recent
publications explain the relationship between SVM and
optimal ZSS-PWM [6-9]. In such publications, (1) is
obtained after analyzing the inverter switching states under a
2D approach. In this work, the analysis of the modulation
process is performed using a three-dimensional (3D)
approach. The conclusions obtained from this analysis have a
higher physical meaning than in the 2D case, and the
resultant three-dimensional space-vector modulation
technique (3D-SVM) can be easily extended to four-legged
and multilevel converters.
II. MAXIMUM USE OF DC-BUS VOLTAGE IN THREE-PHASE
FULL-BRIDGE CONVERTERS
A PEBB-based three-phase full-bridge inverter with a
generic load is shown in Fig. 1. In this figure, two dc-link
capacitors connected in series are represented in order to
obtain a reference point in the middle of the dc-bus (‘0’).
Therefore, the voltages on the capacitors are vC1>0 and
vC2<0, and their absolute value is half the dc-link voltage.
497
 vC 1
C1

(0) vdc
(a)
vC 2 C2

Fig. 1. Three-phase full-bridge inverter based on PEBB’s.

According to Fig. 1, the following convention will be αβ plane

considered for further explanations in this paper: 3

i) The ac referred (ACR) voltages are the output voltages 4 2

of the inverter (vFan, vFbn, vFcn) referred to the neutral

point of the load, ‘n’. (b) 0 7

ii) The dc referred (DCR) voltages are the output voltages 5 1

(vFa0, vFb0, vFc0) referred to the dc-bus midpoint, ‘0’. 6

Moreover, the switching state of each PEBB is defined by

the variable si = ±1 for i = {a, b, c} , in which the positive or
negative values represent the ON state of the upper or lower
switch, respectively. Fig. 2. Normalized DCR generating vectors:
In the synthesis of a generic ACR voltage vector, the (a) on the α-β-γ frame, (b) View from the zero-sequence axis.
maximum use of the dc-bus voltage is achieved when an
optimal strategy is used in the modulation process. In this In the inverter of Fig. 1, no zero-sequence current can flow
paper, to determine which is the most efficient strategy a true in the load side, and consequently no zero-sequence voltage
three-dimensional approach will be used. Thus, each can exist across of the balanced load. Consequently, the ACR
switching state of the inverter can be represented by: voltage vector will always be on the αβ plane, independently
r
[ ]
S j = s aj sbj s cj ; j = {0...7} , (2)
of the value of the zero-sequence component of the DCR
voltage vector. When the zero-sequence component of the
where the following switching matrix shows all eight DCR voltage vector is not equal to zero, such a component
possible switching states for the inverter: will not be present at the ACR voltage vector, and it will be
r
[ r r r r r r
S = S 0 S1 S 2 S 3 S 4 S5 S 6 S 7
r T
] spontaneously transformed into a “flotation voltage” between
the nodes ‘0’ and ‘n’ (v0n). This is the key of the maximum
⎡1 1 1 −1 −1 −1 1 − 1⎤
T
use of the dc-bus voltage, since the inverter does not need to
(3) regulate the γ component of the DCR voltage vector, but only
⎢
= ⎢1 − 1 1 1 1 − 1 − 1 − 1⎥⎥ .
its angular position, in order to achieve a generic ACR
⎢⎣1 − 1 − 1 − 1 1 1 1 − 1⎥⎦ voltage vector placed on the αβ plane.
Therefore, the eight three-dimensional DCR generating When conventional SPWM is used for the modulation of
vectors can be obtained as: the inverter, the synthesized DCR vector is on the αβ plane
and v0n is equal to zero. In such case, the magnitude of the
[
r r r r r r r r T
VF 0 = S·u = V0 V1 V2 V3 V4 V5 V6 V7 , (4) ] synthesized ACR vector (equal to the DCR vector) will be
abc limited by the inner hexagon shown in Fig. 2(b). The dashed
where all of the vectors have been normalized to vdc/2, and circle drawn inside this inner hexagon corresponds to the
r r r T
u = [u a u b u c ] represents the unitary vectors of the synthesis of a set of balanced three-phase sinusoidal ACR
natural a-b-c reference base. By means of the Clarke voltages using SPWM with modulation index m = 1 .
transformation [10], the eight DCR generating vectors can be When SVM is applied to the inverter, the maximum use of
r r on the α-β-γ as Fig. 2(a) shows. Conventionally,
represented r r the dc-bus voltage is achieved. In SVM, the synthesized
V0 and V7 are known as zero-vectors, while V1 to V6 are DCR vector is not on the αβ plane and v0n is not equal to
known as active-vectors. In Fig. 2(a) the αβ plane (plane zero. In this case, the magnitude of the synthesized ACR
without zero-sequence component) is also represented. When vector, which is on the αβ plane, will be limited by the outer
a generic DCR voltage vector is synthesized by the inverter, hexagon shown in Fig. 2(b). The solid circle drawn inside
its angular position in the αβ plane is determined by the this outer hexagon corresponds to the synthesis of a set of
combination of two active vectors, whereas its γ component balanced three-phase sinusoidal ACR voltages by means of
is regulated by the two zero-vectors. SVM with m = 2 3 .

498
 r r r T
III. GENERATING-VECTORS IMPLIED IN THE SYNTHESIS OF b1 = [u 0 u1 u2 ]
THE DCR REFERENCE VECTOR
⎡ 1 1 1⎤
The synthesis of a generic DCR reference vector will be =
1 r
V0 [ r
V1
r
V2 ]
T
=
1 ⎢
1 − 1 − 1⎥⎥ u,
(6a)
performed by the sequential application throughout a 3 3⎢
⎢⎣ 1 1 − 1⎥⎦
switching period of the proper generating vectors. In order to
r r r T
know the duty cycle of each one of the generating vectors b 2 = [u 0 u3 u4 ]
used in the synthesis of such DCR reference vector, it seems
interesting to transform it from the natural a-b-c reference ⎡ 1 1 1⎤
base to a new one, which is directly based on the generating =
1 r
3
V0 [ r
V3
r
V4 ] T
=
1 ⎢
3⎢
−1 1 − 1⎥⎥ u,
(6b)
vectors. This new reference base is called generating base. ⎢⎣ − 1 1 1⎥⎦
To determine which generating vectors should be applied
r r r T
in the synthesis of the DCR voltage vector, the total space b 3 = [u 0 u5 u6 ]
defined by the cube of Fig. 1, which is called the
controllability cube, is divided into twelve subspaces. Three ⎡ 1 1 1⎤
generating vectors delimit each subspace; two of them =
1 r
[
V0
r
V5
r
V6 ] T
=
1 ⎢
− 1 − 1 1⎥⎥ u.
(6c)
correspond to the active vectors and the third one 3 3⎢
⎢⎣ 1 − 1 1⎥⎦
corresponds to a zero-vector. In this work, three subspaces
are defined as the basis for the synthesis of the DCR vector. Fig. 3(d) shows the planes corresponding to the zero line-
Such subspaces are shown in Fig. 3 and can be expressed as: to-line voltages, which are orthogonal to the figure (vFab=0,
r r
{
Subspace SS012 ≡ SS V0 , V1 , V2
r
} vFbc=0, vFca=0). These planes coincide with some of the
boundaries of the generating bases. Thereby, a good method
r r
{ r
Subspace SS034 ≡ SS V0 , V3 , V4 , and (5) } to decide which will be the generating base in charge of the
r r
{ r
Subspace SS056 ≡ SS V0 , V5 , V6 . } DCR vector synthesizing is to analyze the signs of the
reference line-to-line DCR voltages.
From these subspaces, three generating bases are defined, If the following logic variables are defined from the signs
which are constituted by the unitary vectors shown in (6). In of the line-to-line voltages of the DCR reference vector:
the technique presented in this paper,
r it is assumed that a C1 = (v Fab ≥ 0) , C2 = (v Fbc ≥ 0) , and C3 = (v Fca ≥ 0) , (7)
generic DCR voltage vector VF 0 = [v Fa 0 v Fb 0 v Fc 0 ]⋅ u
the following exclusive-nor functions determine the
must be synthesized by a particular generating base when the generating base to be used in the synthesis of such vector:
two active components of this vector (expressed on such
base) are either positive or negative simultaneously, P1 = C1 ⊕ C2 , P2 = C2 ⊕ C3 , and P3 = C3 ⊕ C1 , (8)
regardless of the sign of the zero component in that base. where Pi=1 indicates that the DCR reference voltage vector
belongs to the generating base i; see Fig. 3(d).

IV. TRANSFORMATION OF THE DCR REFERENCE VECTOR

INTO THE GENERATING BASES
When inverting the matrices in (6), the a-b-c natural
reference frame can be expressed on the different generating
bases as:
⎡ 1 1 0⎤
3⎢
u= ⎢ 0 −1 1⎥⎥ ⋅ b1 , (9a)
(a) (b) (c) 2
⎢⎣ 1 0 − 1⎥⎦
0=
v
Fb =0 ⎡ 1 0 − 1⎤
v Fa b 3⎢
1 0⎥⎥ ⋅ b 2 ,
c
C 2 & C 3 C 3 & C1 u= ⎢ 1 (9b)
2
2 3 ⎢⎣ 0 − 1 1⎥⎦
C1 & C 2 1 1 C1 & C 2
(d) 3 2
⎡ 0 −1 1⎤
3⎢
C3 & C1 C 2 & C 3 u= 1 0 − 1⎥⎥ ⋅ b 3 . (9c)
2 ⎢
⎢⎣ 1 1 0⎥⎦
vFca= 0

If a generic reference ACR voltage vector is defined by:

[ ]
r*
VFn = v Fa
*
0
*
v Fb 0
*
v Fc 0 ⋅u , (10)
Fig. 3. Basic subspaces: (a) SS012; (b) SS034; (c) SS056; and it is initially assumed that the ACR voltage vector will be
(d) Identification of the generating bases. equal to the DCR voltage vector (like in SPWM), the DCR

499
voltage vector to be synthesized can be expressed on the ⎡1 0 0⎤
[ ]
r* 3 *
v *Fcn ⎢0 0 0⎥ ⋅ b1 (12a)
proper generating base as:
If P1 = 1 : VZSS = v Fan v *Fbn
[ ] ⎢ ⎥
r 2
If P1 = 1 : V F*0 = v F* 00 v F* 10 v F* 20 ⋅ b 1 012
⎢⎣1 0 0⎥⎦
012

⎡ 1 1 0⎤ (11a) ⎡1 0 0⎤
[ ]
r*
=
2
3 *
[ * *
⎢
]
v Fan v Fbn v Fcn ⎢ 0 − 1 1⎥ ⋅ b 1 ,
⎥
If P2 = 1 : VZSS =
034 2
3 *
v Fan *
v Fbn *
v Fcn ⎢1 0 0⎥ ⋅ b
⎢ ⎥ 2 (12b)
⎢⎣ 1 0 − 1⎥⎦ ⎢⎣0 0 0⎥⎦

[ ]
r
If P2 = 1 : V F*0 = v F* 00 v F* 30 v F* 40 ⋅ b 2 ⎡0 0 0⎤
[ ]
034
r* 3 * ⎢1 0 0 ⎥ ⋅ b
If P3 = 1 : VZSS = v Fan v *
v *

2
Fbn Fcn ⎢ ⎥ 3 (12c)
⎡ 1 0 − 1⎤ (11b)
056
⎢⎣1 0 0⎥⎦
=
2
3 *
[ *
v Fan v Fbn *
v Fcn ] ⎢ 1 1 0⎥ ⋅ b ,
⎢ ⎥ 2 Using (6), the space-vector component to be canceled can
⎣⎢ 0 − 1 1⎥⎦ be transformed into the a-b-c natural base, as follows:
[ ]
r
If P3 = 1 : V F*0 = v F* 00 v F* 50 v F* 60 ⋅ b 3 ⎡ 1 1 1⎤
[ ]
056 r* 1 * ⎢0 0 0⎥ ⋅ u
If P1 = 1 : VZSS = v Fan v *
Fbn v *
Fcn ⎢ ⎥ (13a)
⎡ 0 − 1 1⎤ (11c) abc 2
⎢⎣ 1 1 1⎥⎦
=
2
3 *
[ *
v Fan v Fbn *
v Fcn ] ⎢ 1 0 − 1⎥ ⋅ b .
⎢ ⎥ 3

⎢⎣ 1 1 0⎥⎦ ⎡ 1 1 1⎤
[ ]
r* 1 ⎢ 1 1 1⎥ ⋅ u
If P2 = 1 : VZSS = v *Fan v *
Fbn v *
Fcn ⎢ ⎥ (13b)
In (11), independently of the generating base being used, abc 2
the contribution of the zero-vectors in the synthesis of the ⎢⎣0 0 0⎥⎦
reference vector of (10) is easily identifiable by means of the
⎡ 0 0 0⎤
vF00 component. This component does not affect to the
[ ]
r* 1 ⎢ 1 1 1⎥ ⋅ u
angular position of the DCR voltage vector on the αβ plane, If P3 = 1 : VZSS = v *Fan v *
Fbn v *
Fcn ⎢ ⎥ (13c)
abc 2
and it is only regulating the γ component of the DCR voltage ⎢⎣ 1 1 1⎥⎦
vector in order to ensure that such a vector is effectively on
A simple analysis of the matrices shown in (13) permits to
the αβ plane. obtain a generalized expression for the zero-sequence signal
to be subtracted from the original ACR reference voltage
V. 3D-SVM ALGORITHM vector in order to obtain the modified DCR reference voltage
vector. This generalized expression is given by:
To achieve the maximum use of the dc-link voltage, the
DCR reference voltage vector, which is supposed initially *
v ZSS =
1
2
{( )
P3 ⋅ v *Fan + P1 ⋅ v *Fbn + P2 ⋅ v Fcn
*
(14) ( ) ( ) }
equal to the ACR reference vector, should be modified. This
is done by cancellation of the vF00 component in the DCR and the diagram of the 3D-SVM algorithm proposed in this
reference voltage vector of (11). Cancellation of the vF00 paper is shown in Fig. 4.
eliminates the net contribution of the zero-vectors on the
modified DCR voltage vector. In the conventional SVM VI. PEBB-BASED CONVERTER STRUCTURE
technique, this cancellation is achieved byr means r of
equalizing the duty cycle of both zero-vectors ( V0 and V7 ) in The modularity and flexibility of a PEBB-based modular
every switching period. power electronics system is such that it can allow for
From (11), the space-vector component that should be expeditious on-site reconfiguration, both topology- and
canceled in each case can be written as (12) shows. function-wise, as well as for power scalability through the
r r
VFn* VF*0
abc
* * *
v Fan v Fbn v Fcn[ ] abc

C1 P1
v *Fan − v *Fbn
1
0 *
vZSS ≡ v0 n
C2 P2
− v *Fcn { ( P )v + ( P2 )v *Fcn }
* 1
v Fbn 0
1
2 3
*
Fan + ( P1 )v Fbn
*

C3 P3
v *Fcn − v *Fan
1
0

Fig. 4: Diagram of the 3D-SVM algorithm proposed.

500
interconnection of parallel or series modules. For low voltage
systems (230-460 VAC), the choice of a single phase-leg as
PEBB is usually a rational alternative, which gives ample
freedom for the implementation of half-bridge, H-bridge,
three-phase full bridge, and four-legged converters
depending on the application at hand. This distributed power
stage structure fully exploits the PEBB definition, i.e., an
intelligent power module capable of interacting with its peers
in order to perform conventional power electronics tasks, yet
implicitly requires a distributed control system architecture.
This represents a hierarchized power stage and controls
converter structure, which provides maximum flexibility for
both hardware and software implementation and
development through enhanced scalability and reusability. In
this paper specifically, the distributed control architecture
under consideration comprises a hardware-independent
application controller, dubbed universal controller (UC), and
hardware-specific yet application-independent hardware
managers (HM) controlling the PEBB’s. Communication
across the control network is established through a dual fiber-
optic ring network and a developed industrial-based protocol.
Fig. 5 shows a block diagram and actual hardware of the
PEBB-based inverter under study. Each PEBB slides into the
cabinet locking its ac and dc-bus terminals into the bus bars
in the back of the cabinet. This figure also depicts the 33 kW,
1200V/300A PEBB built in the lab.
Fig. 5. Structure and hardware of the PEBB-based inverter.
501
The main PEBB components are: HM with Xilinx FPGA
Virtex XCV300-4BG352, communication ports (Cypress
TAXIchip), current and voltage sensors (LEM LV-25P and
LA200), and A/D converters (AD7869), Powerex IPM
(PM300DVA120), a 35µF film capacitor (UL31BL356K),
and the power terminals. The PEBB converter is designed as
a forced-air cooled system.
Obviously, control of the PEBB-based inverter shown in
Fig. 5 is not trivial, especially if maximum utilization of the
installed capacities is desired. This brief presentation of the
experimental system does not go deeply into details about its
practical implementation or the programming of the 3D-
SVM algorithm on the UC and further insight in these
aspects will be provided in future work.
VII. EXPERIMENTAL RESULTS
The modulation strategy shown in Fig. 4 was programmed
on the UC and applied to a three-phase full-bridge PEBB-
based inverter. In such experiments, the dc-link voltage was
Vdc=100 V, the switching frequency fS=20 kHz, and the
electrical load a wye-connected resistive load (R=0.83 Ω) by
means of a low-pass 2nd order L-C filter (L=216 µH, C=60
µF). The value of the modulation index (m) is normalized to
the SPWM.
Fig 6(c) shows the DCR voltage reference signal for
phase-leg a, v*Fa 0 , which comes from the application of the
3D-SVM algorithm to the synthesis of three balanced
sinusoidal ACR voltages with m=0.6. This well known
waveform coincides with that one obtained from the
application of (1) and gives rise to the same results than if
conventional SVM, with symmetrical placement of the zero
vectors, was used. Therefore, the new standpoint exposed
earlier for analyzing the modulation process in the three-
phase full-bridge inverter can be considered as valid.
Fig 6(b) shows the filtered output current for phase-leg b.
Although this current should be perfectly sinusoidal, the
actual current presents a significant distortion, which is a
consequence of the nonideal characteristics of the inverter.
(a)
(b)
(c)
(d)
Fig. 6. Experimental results. (a) Line-to-line output voltage, vFab,
(b) Leg b filtered output current, iLb, (c) Leg a DCR voltage
reference signal, vFa0*, (d) Top-switch leg a gate signal.
 In fact, the relatively high power of the PEBB used for
these experiments (33 kW) makes necessary that the
blanking time to avoid the so-called shoot-through of the dc
link is also high. For the PEBB of Fig. 5, the blanking time is
td=3.5 µs, which, in relation to the switching period (TS=20
µs), gives rise to an important nonlinearity in the inverter.
To compensate the blanking time effect, the DCR voltage
reference signal should be modified as (15) shows.
v *Fi*0 = v *Fi 0 ± ∆v ; i ∈ {a, b, c} (15)
In (15), ∆v is a function of the blanking time, the delay on
the switch-on and -off, the voltage drop across the switch and
the freewheeling diode, and the magnitude of the current
[11]. The positive or negative sign to be applied in each case
depends on the sign of the current.
Fig. 7(c) shows the DCR voltage reference signal for the
leg a after blanking time compensation. In such signal, the
effect of the term ∆v of (15) can be clearly identified, giving
rise to a discontinuity in the waveform every time the current
in phase-leg a changes its sign. Fig 7(b) shows the filtered
current in the phase-leg b, which is now perfectly sinusoidal.
(a)
(b)
(c)
(d)
Fig. 7. Experimental results. (a) Line-to-line output voltage, vFab,
(b) Leg b filtered output current, iLb, (c) Leg a DCR voltage
compensated reference signal, vFa0**, (d) Top-switch gate signal.
VIII. CONCLUSION
This paper presents the analytical fundamentals of a
practical implementation of SVM in a three-phase PEBB-
based power conversion system. The analysis here presented
uses a true three-dimensional interpretation of the inverter
variables, and after an algebraically sound reasoning, an
alternative SVM algorithm is proposed. This new 3D-SVM
algorithm is highly efficient to be implemented in a
distributed digital control architecture composed of an
application controller (UC) sending duty cycle information to
the PEBB controllers (HM’s). Since the PWM modulator of
the HM is based on a double-slope triangular-carrier
waveform, optimal sequences of generating vectors are
applied at any modulation period. Moreover, considering that
the PWM generators of the different HM’s are perfectly
502
synchronized, the switching frequencies in the PEBB devices
are the minimum as possible from sequences of four
generating vectors.
This paper not only introduces a new 3D-SVM algorithm,
which is even more efficient than that one based on (1)
because its inherent logic character, but also offers an three-
dimensional standpoint in the analysis of the modulation
process. This 3D standpoint is not only useful for the analysis
of the three-phase inverters but also for other flexible PEBB-
based power electronics structures, such as four-legged and
multilevel inverters. Further insight on these aspects will be
given in future work.
ACKNOWLEDGMENT
This work was supported by the Departament
d’Universitats, Recerca i Societat de la Informació of the
Generalitat de Catalunya, under grants 2004BE00060 and
2004BE00150, and by the Ministerio de Ciencia y
Tecnologia of Spain under Project ENE2004-07881-C03-02.
This work made use of Engineering Research Center
Shared Facilities supported by the National Science
Foundation under NSF Award Number EEC-9731677 and
the CPES Industry Partnership Program. Any opinions,
findings and conclusions or recommendations expressed in
this material are those of the authors and do not necessarily
reflect those of the National Science Foundation.
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