Académique Documents
Professionnel Documents
Culture Documents
ar
Service Guide
vii
Appendices
Appendix D Schematics
viii
List of Figures
1-1 PCB No. 96183-1A Mainboard Layout (Top) ........................................................ 1-2
1-2 PCB No. 96183-1A Mainboard Layout (Bottom) ................................................... 1-3
1-3 PCB No. 96534-SE CPU Board Layout (Top)....................................................... 1-4
1-4 PCB No. 96534-SE CPU Board Layout (Bottom).................................................. 1-4
1-5 PCB No. 97355-1 Audio Board............................................................................. 1-5
1-6 PCB No. 97348-1 Battery Board .......................................................................... 1-5
1-7 PCB No. 97349-1 Keyboard/Touchpad Board (Top View) .................................... 1-6
1-8 PCB No. 97349-1 Keyboard/Touchpad Board (Bottom View) ............................... 1-6
1-9 Jumpers and Connectors (Top View) ................................................................... 1-7
1-10 Jumpers and Connectors (Bottom View) .............................................................. 1-8
1-11 Power Management Block Diagram ....................................................................1-24
1-12 System Block Diagram........................................................................................1-31
1-13 Clock Block Diagram ..........................................................................................1-32
2-1 PCI1250 Block Diagram....................................................................................... 2-4
2-2 M1531 Pin Diagram (Top View) ..........................................................................2-23
2-3 M1533 Pin Diagram (Top View) ..........................................................................2-39
2-4 FDC37C67 (TQFP) Pin Diagram.........................................................................2-50
2-5 FDC37C67 (QFP) Pin Diagram...........................................................................2-51
2-6 FDC37C67 Block Diagram..................................................................................2-56
2-7 65555 BGA Ball Assignments (Top View) ...........................................................2-64
2-8 65555 BGA Ball Assignments (Bottom View) ......................................................2-65
2-9 M38813 Pin Diagram ..........................................................................................2-78
2-10 M38813 Block Diagram.......................................................................................2-80
2-11 YMF715 Block Diagram ......................................................................................2-82
4-1 Removing the Battery Pack ................................................................................. 4-2
4-2 Using Connectors With Locks .............................................................................. 4-3
4-3 Disassembly Sequence Flowchart........................................................................ 4-5
4-4 Removing the Memory Door ................................................................................ 4-6
4-5 Installing and Removing Memory......................................................................... 4-7
4-6 Removing the Modem Board ............................................................................... 4-8
4-7 Removing the Hard Disk Drive............................................................................. 4-9
4-8 Removing the Display Hinge Covers...................................................................4-10
4-9 Removing the Keyboard .....................................................................................4-10
4-10 Unplugging the Keyboard Connectors .................................................................4-11
ix
4-11 Removing the LED Cover ...................................................................................4-12
4-12 Removing the Heat Sink Assembly .....................................................................4-12
4-13 Unplugging the Display Cable .............................................................................4-13
4-14 Removing the Display Hinge Screws ..................................................................4-13
4-15 Removing the Display Hinge Screws ..................................................................4-14
4-16 Removing the Internal Drive ...............................................................................4-15
4-17 Replacing the CPU .............................................................................................4-15
4-18 Removing Cables ...............................................................................................4-16
4-19 Detaching the Top Cover ....................................................................................4-16
4-20 Removing the Bottom Screws.............................................................................4-17
4-21 Removing the Keyboard/Touchpad Board and DC-DC Converter Board Cover...4-17
4-22 Removing the DC-DC Converter Board ..............................................................4-18
4-23 Removing the Mainboard....................................................................................4-18
4-24 Removing the Charger Board .............................................................................4-19
4-25 Removing the PCMCIA Sockets .........................................................................4-19
4-26 Removing the Hard Disk Drive Heat Sink ...........................................................4-20
4-27 Removing the Audio Board .................................................................................4-20
4-28 Removing the Touchpad and Speakers ..............................................................4-21
4-29 Removing the LCD Bumpers ..............................................................................4-22
4-30 Removing the Display Bezel Screws...................................................................4-22
4-31 Removing the Display Bezel ...............................................................................4-23
4-32 Removing the Inverter Board ..............................................................................4-23
4-33 Removing the LCD Panel ...................................................................................4-24
x
List of Tables
1-1 CPU Mounting Reference Table........................................................................... 1-5
1-2 SW1 Switch Settings ........................................................................................... 1-8
1-3 Memory Address Map .......................................................................................... 1-9
1-4 Interrupt Channel Map ......................................................................................... 1-9
1-5 DMA Channel Map..............................................................................................1-10
1-6 I/O Address Map .................................................................................................1-10
1-7 Processor Specifications.....................................................................................1-11
1-8 BIOS Specifications ............................................................................................1-11
1-9 Memory Configurations.......................................................................................1-12
1-10 Video RAM Configuration....................................................................................1-13
1-11 Video Hardware Specification .............................................................................1-13
1-12 Supported External CRT Resolutions..................................................................1-13
1-13 Supported LCD Resolutions ................................................................................1-14
1-14 Parallel Port Configurations ................................................................................1-14
1-15 Serial Port Configurations ...................................................................................1-15
1-16 Audio Specifications ...........................................................................................1-15
1-17 PCMCIA Specifications.......................................................................................1-16
1-18 Touchpad Specifications .....................................................................................1-16
1-19 Keyboard Specifications......................................................................................1-16
1-20 Windows 95 Key Descriptions .............................................................................1-17
1-21 FDD Specifications .............................................................................................1-17
1-22 HDD Specifications.............................................................................................1-18
1-23 CD-ROM Specifications ......................................................................................1-18
1-24 Battery Specifications .........................................................................................1-19
1-25 Charger Specifications........................................................................................1-20
1-26 DC-DC Converter Specifications.........................................................................1-20
1-27 DC-AC Inverter Specifications ............................................................................1-21
1-28 LCD Specifications .............................................................................................1-21
1-29 AC Adapter Specifications ..................................................................................1-22
1-30 Hotkey Descriptions ............................................................................................1-23
1-31 Standby Mode Conditions and Descriptions ........................................................1-25
1-32 Light Green Mode Conditions and Descriptions...................................................1-26
1-33 Hibernation Mode Conditions and Descriptions ...................................................1-27
1-34 Display Standby Mode Conditions and Descriptions ............................................1-27
xi
1-35 Hard Disk Standby Mode Conditions and Descriptions ........................................1-28
1-36 Location of Drivers in the System Utility CD........................................................1-29
1-37 Location of Applications in the System Utility CD ................................................1-30
1-38 Environmental Requirements..............................................................................1-33
1-39 Mechanical Specifications...................................................................................1-34
2-1 Major Chips List ....................................................................................................2-1
2-2 PCI1250 Terminal Functions.................................................................................2-5
2-3 M1531 Signal Descriptions..................................................................................2-24
2-4 M1531 Numerical Pin List ...................................................................................2-28
2-5 M1533 Numerical Pin List ...................................................................................2-40
2-6 FDC37C67 Pin Descriptions ...............................................................................2-52
2-7 FDC37C67 Multifunction Pin Descriptions...........................................................2-55
2-8 65555 Pin Functions ...........................................................................................2-66
2-9 M38813M4-XXXHP Functions.............................................................................2-77
2-10 M38813M4-XXXHP Pin Description ....................................................................2-79
2-11 YMF715 Descriptions..........................................................................................2-83
3-1 Basic System Settings Parameters .......................................................................3-3
3-2 Startup Configuration Parameters.........................................................................3-4
3-3 Onboard Devices Configuration Parameters .........................................................3-6
3-4 System Security Parameters.................................................................................3-8
3-5 Power Management Settings Parameters .............................................................3-9
4-1 Guide to Disassembly Sequence ..........................................................................4-4
B-1 Exploded View Diagram List ................................................................................ B-1
C-1 Spare Parts List ................................................................................................... C-1
D-1 Schematics List ................................................................................................... D-1
E-1 POST Checkpoint List.......................................................................................... E-1
xii
C h a p t e r 1
System Introduction
1.1 Overview
This computer combines high-performance, versatility, power management features and
multimedia capabilities with unique style and ergonomic design. This computer was designed with
the user in mind. Here are just a few of its many features:
• Performance
• Intel Pentium® processor with MMX™ technology
• 64-bit main memory and external (L2) cache memory
• Large LCD display and PCI local bus video with graphics acceleration
• Internal CD-ROM drive and external 3.5-inch floppy drive, or internal 3.5-inch floppy drive
• High-capacity, Enhanced-IDE hard disk
• Lithium-Ion or Nickel Metal-Hydride battery pack
• Power management system with light green, standby and hibernation power saving modes
• Multimedia
• 16-bit high-fidelity stereo audio with 3-D sound
• Built-in dual speakers
• Ultra-slim, high-speed CD-ROM drive
• Connectivity
• High-speed fax/data modem port
• Fast infrared wireless communication
• USB (Universal Serial Bus) port
• Expansion
• CardBus PC card (formerly PCMCIA) slots (two type II/I or one type III) with ZV (Zoomed
Video) port support
• Port replicator option for one-step connect/disconnect from peripherals
• User-upgradeable memory and hard disk
1.2.1 Mainboard
CPU Volt Freq R4 R6 R8 R11 R20 R22 R24 R26 RX14 RY1 RX6 RX9 RX11 RX12 UX2 UX3
1
V: mount on; X: not mount on
CN6
CN7
CN9 CN11
CN10
CN16 CN13
CN15
CN14
SW1
CN17
CN18
CN21
CN19
CN20
CN22
GF1
CN24
CN23
DIMM
ON OFF
Switch 1 (Logo Screen) OEM Acer
Switch 2 (Password) Bypass Check
Germany U.S. Japanese
Switch 3 (KB Language) On Off Off
Switch 4 (KB Language) Off Off On
Item Specification
CPU type P55C-133/150/166
CPU package TCP
Switchable processor speed (Y/N) Yes
Minimum working speed 0MHz
CPU core voltage 2.0V/2.45V/1.8V
CPU I/O voltage 2.5V/3.3V/2.5V
1.4.6 BIOS
Item Specification
BIOS vendor Acer
BIOS version V3.0
BIOS in flash EPROM (Y/N) Yes
BIOS ROM size 256KB
BIOS package type 32-pin PLCC
Same BIOS for STN color/TFT color (Y/N) Yes
• Expansion RAM module type:144-pin, 64-bit, small outline Dual Inline Memory Module
(soDIMM)
2
You can upgrade memory using 32-MB soDIMMs when these become available. Consult your dealer.
• EDO and fast-page mode DIMMs may be used together in a memory configuration.
Item Specification
DRAM or VRAM DRAM(EDO type)
Fixed or upgradeable Fixed
Memory size/configuration 2MB (256K x 16 x 4pcs)
Memory speed 50ns
Memory voltage 3.3V
Memory package TSOP
1.4.10 Video
Item Specification
Video chip C&T65555
Working voltage 3.3V
Resolution x Color on LCD Only TFT LCD (SVGA) DSTN LCD (SVGA)
640x480x16 Y Y
640x480x256 Y Y
640x480x65,536 Y Y
640x480x16,777,216 Y Y
800x600x16 Y Y
800x600x256 Y Y
800x600x65,536 Y Y
800x600x16777216 Y Y
1024x768x16 Y Y
1024x768x256 Y Y
1024x768x65536 Y Y
1280x1024x16 Y Y
1280x1024x256 Y Y
Using software, you can set the LCD to a higher resolution than its physical
resolution, but the image shown on the LCD will pan.
Item Specification
Number of parallel ports 1
ECP support Yes (set by BIOS setup)
Connector type 25-pin D-type
Location Rear side
Selectable parallel port (by BIOS Setup) • Parallel 1 (3BCh, IRQ7)
• Parallel 2 (378h, IRQ7)
• Parallel 3 (278h, IRQ5)
• Disable
Item Specification
Number of serial ports 1
16550 UART support Yes
Connector type 9-pin D-type
Location Rear side
Selectable serial port (by BIOS Setup) • Serial 1 (3F8h, IRQ4)
• Serial 2 (2F8h, IRQ3)
• Disable
1.4.13 Audio
Item Specification
Chipset YMF715
Audio onboard or optional Built-in
Mono or stereo Stereo
Resolution 16-bit
Compatibility SB-16 , Windows Sound System
Mixed sound sources Voice, Synthesizer, Line-in, Microphone, CD
Voice channel 8-/16-bit, mono/stereo
Sampling rate 44.1 kHz
Internal microphone No
Internal speaker / quantity Yes / 2 pcs.
Microphone jack Yes
Headphone jack Yes
1.4.14 PCMCIA
PCMCIA is an acronym for Personal Computer Memory Card International Association. The
PCMCIA committee set out to standardize a way to add credit-card size peripheral devices to a
wide range of personal computers with as little effort as possible.
There are two type II/I or one type III PC Card slots found on the left panel of the notebook. These
slots accept credit-card-sized cards that enhances the usability and expandability of the notebook.
ZV (Zoomed Video) port support allows your system to support hardware MPEG in the form of a
ZV PC card.
Item Specification
Chipset TI 1250A
Supported card type Type-II / Type-III
Number of slots Two Type-II or one Type-III
Access location Left side
ZV (Zoomed Video) port support Yes
1.4.15 Touchpad
Item Specification
Vendor & model name Synaptics TM3202TPD-226
Power supply voltage (V) 5 ± 10%
Location Palm-rest center
Internal & external pointing device work simultaneously Yes
Support external pointing device hot plug Yes
X/Y position resolution (points/mm) 20
Interface PS/2 (compatible with Microsoft mouse driver)
1.4.16 Keyboard
Item Specification
Vendor & model name SMK KAS1901-0161R (English)
Total number of keypads 84/85 keys
Windows 95 keys Yes, (Logo key / Application key):
Internal & external keyboard work simultaneously Yes
The keyboard has two keys that perform Windows 95-specific functions. See Table 1-26.
Key Description
Windows logo key Start button. Combinations with this key performs special functions, e.g.:
• Windows + Tab Activate next Taskbar button
• Windows + E Explore My Computer
• Windows + F Find Document
• Windows + M Minimize All
• Shift + Windows + M Undo Minimize All
• Windows + R Display Run dialog box
Application key Opens the application’s context menu (same as right-click).
1.4.17 FDD
Item Specification
Vendor & model name Mitsumi D353F2
Floppy Disk Specifications
Media recognition 2DD (720K) 2HD (1.2M, 3-mode) 2HD (1.44M)
Sectors / track 9 15 18
Tracks 80 80 80
Data transfer rate (Kbits/s) 250 300 500 500
Rotational speed (RPM) 300 360 360 300
Read/write heads 2
Encoding method MFM
Power Requirement
Input Voltage (V) +5 ± 10%
Item Specification
Vendor & Model Name Hitachi DK225A-21 IBM DTNA22160 IBM DDLA21620
Drive Format
Capacity (MB) 2160 2160 1620
Bytes per sector 512 512 512
Logical heads 16 16 16
Logical sectors 63 63 63
Logical cylinders 4889 4200 3152
Physical read/write heads 6 6 3
Disks 3 3 2
Spindle speed (RPM) 4464 4000 4000
Performance Specifications
Buffer size (KB) 128 96 96
Interface ATA-3(IDE) ATA-2 ATA-2
Data transfer rate 5.7 ~ 9.0 5 ~ 7.7 5 ~ 8.3
(disk-buffer, Mbytes/s)
Data transfer rate 16.6 /33.3 16.6 16.6
(host-buffer, Mbytes/s) (max., PIO mode 4) (max., PIO mode 4) (max., PIO mode 4)
DC Power Requirements
Voltage tolerance (V) 5 ± 5% 5 + 5% 5 ± 5%
1.4.19 CD-ROM
Item Specification
Vendor & Model Name Panasonic KMEUJDA110
Performance Specification
Speed (KB/sec) 2100 (14X ave. speed)
Access time (ms) 150 (Typ.)
Buffer memory (KB) 128
Interface Enhanced IDE (ATAPI) compatible
Applicable disc format CD-DA, CD-ROM, CD-ROM XA (except ADPCM), CD-I, Photo CD
(Multisession), Video CD, CD+
Loading mechanism Soft eject (with emergency eject hole)
Power Requirement
Input Voltage (V) 5
Item Specification
Battery gauge on screen Yes, by hotkey Yes, by hotkey
Vendor & model name Toshiba BTP-031 Sony BTP-T31
Battery type NiMH Li-Ion
Cell capacity (mAH) 3500 1400
Cell voltage (V) 1.2 3.6
Number of battery cell 9-cell 9-Cell
Package configuration 9 serial 3 serial, 3 parallel
Package voltage (V) 10.8 10.8
Package capacity (WAH) 3500 4200
Second battery No No
1.4.21 Charger
To charge the battery, place the battery pack inside the battery compartment and plug the AC
adapter into the notebook and an electrical outlet. The adapter has three charging modes:
• Rapid mode
The notebook uses rapid charging when power is turned off and a powered AC adapter is
connected to it. In rapid mode, a fully depleted battery gets fully charged in approximately two
hours.
• Charge-in-use mode
When the notebook is in use with the AC adapter plugged in, the notebook also charges the
battery pack if installed. This mode will take longer to fully charge a battery than rapid mode.
In charge-in-use mode, a fully depleted battery gets fully charged in approximately six to eight
hours.
• Trickle mode
The adapter charges the battery pack for two hours using trickle current 380mA, then shifts to
1/10 duty pulse trickle charge to keep the battery capacity at 100%.
Item Specification
Vendor & model name Ambit T62.069.C.00
Input voltage (from adapter, V) 0-24V
Output current (to DC/DC converter, A) 3 (max.)
Battery Low Voltage
Battery Low 1 level (V) 10.16 (typ., for NiMH)
8.566 (typ., for LIB)
Battery Low 2 level (V) 10.279 (typ., for NiMH)
8.185 (typ., for LIB)
Battery Low 3 level (V) 9.137 (typ., for NiMH)
7.709 (typ., for LIB)
Charge Current
Background charge (charge even system is still operative, A) 0.8 (typ.)
Normal charge (charge while system is not operative, A) 2.0 (typ.)
Charging Protection
Maximum temperature protection (ºC) 60
Maximum voltage protection (V) 16.7V±0.2V
Over voltage protection 13V±0.15
DC-DC converter generates multiple DC voltage level for whole system unit use.
Item Specification
Vendor & model name Ambit T62.041.C.00
Input voltage (Vdc) 8~21
Output Rating 5V 3.3V 2.9V +12V +6V 5VSB
(2.9 /3.1 /3.3V)
Current (w/ load, A) 0~3.2 0~3.3 0~4.2 0~0.15 0~0.1 0.005
Voltage ripple (max., mV) 50 50 50 100 300 75
Voltage noise (max., mV) 100 100 100 200 500 250
OVP (Over Voltage Protection, V) 6.1~8.0 4.2~6.2 3.3-5.2 V - - -
DC-AC inverter is used to generate very high AC voltage, then supply to LCD CCFT backlight use,
and is also responsible for the control of LCD brightness. Avoid touching the DC-AC inverter area
while the system unit is turned on.
Item Specification
Vendor & model name Ambit T62.071.C.00
Input voltage (V) 6.8(in.) - 22(max.)
Input current (mA) - - 750 (max.)
Output voltage (Vrms, no load) 1000 (min.) - 1600 (max.)
Output voltage frequency (kHz) 40 (min.) - 65 (max.)
Output current (mArms) 1.0~5.5 (min.) 1.5~6.1 (typ.) 2.0~6.7 (max.)
1.4.24 LCD
Item Specification
Vendor & model name HITACHI TORiSAN HITACHI
LMG9980ZWCC-01 LM-JK53-22NFR-A TX31D21VC
Mechanical Specifications
LCD display area 12.1 12.1 12.1
(diagonal, inch)
Display technology STN STN TFT
Resolution SVGA (800x600) VGA (800x600) SVGA (800x600)
Supported colors -- -- 262,144 colors
Optical Specification
Contrast ratio 35 (typ.) 40 (typ.) 80 (typ.)
2
Brightness (cd/m ) 70 (typ.) 70 (typ.) 70 (typ.)
Brightness control keyboard hotkey keyboard hotkey keyboard hotkey
Contrast control using keyboard using keyboard none
hotkey hotkey
Electrical Specification
Supply voltage for LCD 3.3 or 5 (typ.) 3.3 or 5 (typ.) 3.0 ~ 3.6 (typ.)
display (V)
Supply voltage for LCD 650 (typ.) 630 (typ.) 595(typ.), 660(max)
backlight (Vrms)
Item Specification
Vendor & model name Delta ADP-45GB Rev. E3, E5
Input Requirements
Nominal voltages (Vrms) 90 - 264
Nominal frequency (Hz) 47 - 63
Frequency variation range (Hz) 47 - 63
Maximum input current (A, @90Vac, full load) 1.5 A
Inrush current The maximum inrush current will be less than 50A and
100A when the adapter is connected to 115Vac(60Hz)
and 230Vac(50Hz) respectively.
Efficiency It should provide an efficiency of 83% minimum, when
measured at maximum load under 115V(60Hz).
Output Ratings (CV mode)
DC output voltage (V) +19.0V~20.5V
Noise + Ripple (mV) 300mvp-pmax (20Mhz bandwidth)
Load (A) 0 (min.) 2.4 (max.)
Output Ratings (CC mode)
DC output voltage (V) +12 ~+19
Constant output (A) 2.75 ± 0.2
Dynamic Output Characteristics
Turn-on delay time (s, @115Vac) 2
Hold up time (ms; @115 Vac input, full load) 5 (min.)
Over Voltage Protection (OVP, V) 26
Short circuit protection Output can be shorted without damage
Electrostatic discharge (ESD, kV) ±15 (at air discharge)
Dielectric Withstand Voltage
Primary to secondary 3000 Vac (or 4242 Vdc), 10 mA for 1 second
Leakage current 0.25 mA maximum @ 254 Vac, 60Hz.
Regulatory Requirements
Internal filter meets:
1. FCC class B requirements. (USA)
2. VDE 243/1991 class B requirements. (German)
3. CISPR 22 Class B requirements. (Scandinavia)
4. VCCI class II requirements. (Japan)
1.5.1 BIOS
The BIOS is compliant to PCI v2.1, APM v1.2, E-IDE and PnP specification. It also defines the
hotkey functions and controls the system power-saving flow.
Fn-F3 Display Toggle Switches display from LCD to CRT to both LCD and CRT.
Fn-F4 Battery Gauge Displays the battery gauge.
Fn-F5 Volume Control Press the scale hotkeys (Fn-→ and Fn-←) to increase and
decrease the output level.
When the available hotkey is toggled, the system will issue a beep to enter the
assigned process.
The system can boot from the FDD, External FDD, HDD, CD-ROM. The user can select the
desired booting process to boot the system. If the CD-ROM is bootable, the BIOS will override the
other process to boot the system directly.
This computer has a built-in power management unit that monitors system activity. System activity
refers to any activity involving one or more of the following devices: keyboard, mouse, floppy drive,
hard disk, peripherals connected to the serial and parallel ports, and video memory. If no activity is
detected for a period of time (called an inactivity time-out), the computer stops some or all of these
devices in order to conserve energy.
This computer employs an innovative power management technique called Heuristic Power
Management or HPM. HPM allows the computer to provide maximum power conservation and
maximum performance at the same time.
Power management methods used by most computers are timer-based. You set inactivity time-out
values for the display, hard disk, and other devices. The computer then "sleeps" when these time-
outs elapse. The problem with this is that no two users are alike. Each of us has his or her own
habits when using the computer, which makes timer-based power management ineffective.
With HPM, your computer manages its power according to the way you use your computer. This
means the computer delivers maximum power when you need it, and saves power when you don’t
need the maximum — all without your intervention. There are no timers to set, because the HPM
system figures out everything for you.
STANDBY MODE
The computer consumes very low power in standby mode. Data remain intact in the system
memory until battery is drained.
Warning: Unstored data is lost when you turn off the computer power in standby
mode or when the battery is drained.
Condition Description
The condition There are two necessary conditions for the computer to enter standby mode:
to enter
• Heuristic Power Management Mode must be set to [ENABLED].
Standby Mode
• System Sleep State must be set to [STANDBY].
In this situation, the following are ways to enter standby mode:
• Pressing the sleep hot key Fn-F7
• If the waiting time determined by the computer’s HPM unit elapses without any
system activity.
• Closing the display cover.
• With the System Sleep State is set to [HIBERNATION], the computer also enters
standby mode if the hibernation file (Sleep Manager) is invalid or not present.
• “Hard Disk Drive” is [Disabled] in System Security of BIOS SETUP.
• “Hard Disk 0” is [None] in Basic System Configuration of BIOS SETUP.
Note: If the computer detects a PC I/O card installed in the PC card slots, the computer
"sleeps" (light green mode) to maintain your communications connection. It will not enter
standby mode.
The condition • Issue a beep.
of Standby • Light standby LED with 1 Hz frequency.
Mode
• Disable the mouse, serial and the parallel port.
• The keyboard controller, HDD and VGA enter the standby mode.
• Stop the CPU internal clock.
• All the functions are disabled except the keyboard, battery low warning and modem
ring wake up from standby (if enabled).
The condition Any one of following activities will let system back to Normal Mode:
back to On • Any keystroke (Internal KB or External KB)
Mode
• Any active pointing device (internal or external, PS/2 or serial or USB)
• Resume Timer matched
• Opening the display cover if you closed the display cover to enter Standby mode.
• Modem ring
The notebook consumes very low power in light green mode. Data and I/O connections remain
intact in the system memory until battery is drained.
Condition Description
The condition to enter • PCMCIA I/O Card detected and occupy resources (Non Cardbus mode).
Light Green Mode • HPM timer times out or cover close or APM standby / suspend function calls.
The condition of Light • Issue a beep.
Green Mode • Only HDD, VGA enter standby
The condition back to Any one of following activities will let system back to Normal Mode:
On Mode • Any keystroke (Internal KB or External KB)
• Modem ring.
HIBERNATION MODE
In hibernation mode, all power shuts off (the computer does not consume any power). The
computer saves all system information onto the hard disk before it enters hibernation mode. Once
you turn on the power, the computer restores this information and resumes where you left off upon
leaving hibernation mode.
If the computer beeps but does not enter hibernation mode after pressing the sleep
hot key, it means the operating system will not allow the computer to enter the
power saving mode.
Do not change any devices (such as add memory or swap hard disks when the
computer is in hibernation mode.
If the computer detects a PC I/O card installed in the PC card slots, the computer
enters light green mode to maintain your communications connection. It will not
enter standby nor hibernation mode.
Condition Description
The condition to There are two necessary conditions for the computer to enter standby mode:
enter Hibernation • Heuristic Power Management Mode must be set to [ENABLED].
Mode
• System Sleep State must be set to [HIBERNATION].
• The hibernation file created by Sleep Manager must be present and valid.
In this situation, the following are ways to enter hibernation mode:
• Pressing the sleep hot key Fn-F7
• “Hard Disk Drive” is not [Disabled] in System Security of BIOS SETUP.
• “Hard Disk 0” is not [None] in Basic System Configuration of BIOS SETUP.
• If the waiting time determined by the computer’s HPM unit elapses without any
system activity.
• If a battery low condition takes place, the computer enters hibernation mode in
about three minutes. The Sleep Upon Battery-low parameter in Setup must be
set to [ENABLED].
• Invoked by the operating system power saving modes
The condition of • Except the RTC, KB controller and power switch, all the system components are
Hibernation Mode off.
The condition back • Pressing the power switch.
to On Mode
• Resume Timer matched
Screen activity is determined by the keyboard, the built-in touchpad, and an external PS/2 pointing
device. If these devices are idle for the period determined by the computer’s HPM unit, the display
shuts off until you press a key or move the touchpad or external mouse.
Condition Description
The condition to enter • Pointing device is idle until Display Standby Timer times-out or LCD cover
Display Standby Mode is closed.
The condition of • All the system components are on except LCD backlight and CRT
Display Standby Mode horizontal frequency output (if CRT is connected)
The condition back to • Any keystroke (Internal KB or External KB)
On Mode
• Pointing device activity
The VGA BIOS should support DPMS (Desktop Power Management System) for
the standby and hibernation mode function call. When the Display Standby Timer
expires, the system BIOS will execute the DPMS service routines.
The hard disk enters standby mode when there are no disk read/write operations within the period
of time determined by the computer’s HPM unit. In this state, the power supplied to the hard disk is
reduced to a minimum. The hard disk returns to normal once the computer accesses it.
Condition Description
The condition to enter HDD Standby Display Standby HPM timer times-out or LCD cover is
Mode closed.
The condition of HDD Standby Mode All the system components are on except HDD spindle
motor
The condition back to On Mode Any access to HDD
BATTERY LOW
When the battery capacity is low and no adapter is plugged in, the system will generate the
following battery low warning:
• If the AC adapter does not plug in within 3 minutes and the “Standby/Hibernation upon
Battery-low” in BIOS SETUP is enabled, the system will enter Standby/0-Volt Hibernation
Mode. The battery low warning will stop as soon as the AC adapter is plugged into the
system.
The notebook has a unique “automatic dim” power saving feature. When the notebook is using
AC power and you disconnect the AC adapter from the notebook, the system “decides” whether or
not to automatically dim the LCD backlight to save power.
If the LCD backlight is too bright, the system automatically adjusts it to a manageable level;
otherwise, the level stays the same. If you want a brighter picture, you can then adjust the
brightness and contrast level using hotkeys (Fn-F2).
If you reconnect AC power to the system, the system automatically adjusts the LCD backlight to its
original level — the brightness and contrast level before disconnecting the AC adapter. If you
adjusted the brightness and contrast level after disconnecting AC power, the level stays the same
after you reconnect the AC adapter.
There are two reasons for the notebook to have the LCD AutoDim feature. The first is to save the
power during the notebook is operating under the DC mode. The second is to save the “favorite”
brightness parameter set by the user.
1. If the original brightness is over 75% and the AC power is on-line, the BIOS will change the
brightness to 75% after the AC power is off-line.
2. If the original brightness is below 75%, the brightness maintains the same level even if the AC
power is off-line.
3. If the brightness is already changed by the hotkey under DC power, it will not be changed after
the AC power is plugged in.
4. If the brightness is not changed by the hotkey under DC power, the brightness will be changed
back to the old setting — the previous brightness parameter under AC power.
5. If the previous brightness parameter does not exist, the brightness will not be changed in
process 4.
• Windows 953
3
In some areas, a different operating system may be pre-loaded instead of Windows 95.
4
The system utilities and application software list may vary.
Drivers for Windows 3.x and Windows NT are also found in the System Utility CD if you should
need them.
1.6.1
Figure 1-12
CPU P55C
System
System Introduction
CPU Bus
Cache M1531
DIMM2 Socket
VGA
PCMCIA CD-ROM C&T
ALI & HDDD
TI USB 65555
PCI1250A Conn. M1533 Conn.
ISA Bus
1-31
1-32
1.6.2
Figure 1-13
Clock
DIMM1 YMF715
SGRAM CLK DIMM2 37C672
MODEM
72 38813
Service Guide
1.7 Environmental Requirements
Table 1- 38 Environmental Requirements
Item Specification
Temperature
Operating (ºC) +5~ +35
Non-operating(ºC) -20 ~ +60
Humidity
Operating (non-condensing) 20% ~ 80%
Non-operating (non-condensing) 20% ~ 80%
Operating Vibration (unpacked)
Operating 5 - 25.6Hz, 0.38mm; 25.6 - 250Hz, 0.5G
Sweep rate 0.5 octave / minute
Number of test cycles 2 / axis (X,Y,Z)
Non-operating Vibration (unpacked)
Non-operating 5 - 27.1Hz, 0.6G; 27.1 - 50Hz, 0.41mm; 50-500Hz, 2G
Sweep rate 0.5 octave / minute
Number of text cycles 4 / axis (X,Y,Z)
Non-operating Vibration (packed)
Non-operating 5 - 62.6Hz, 0.51mm; 62.6-500Hz, 4G
Sweep rate 0.5 octave / minute
Number of text cycles 4 / axis (X,Y,Z)
Shock
Operating 5G peak, 11±1ms, half-sine
Non-operating (unpacked) 40G peak, 11±1ms, half-sine
Non-operating (packed) 50G peak, 11±1ms, half-sine
Altitude
Operating 10,000 feet (5°C ~ 40°C)
Non-operating 40,000 feet (-10°C ~ 60°C)
ESD
Air discharge 8kV (no error)
12.5kV (no restart error)
15kV (no damage)
Contact discharge 4kV (no error)
6kV (no restart error)
8kV (no damage)
Item Specification
Weight (includes battery)
FDD model 2.77 kg. (6.11 lb.)
CD-ROM model 2.8 kg. (6.2 lb.)
Dimensions WxDxH
(main footprint) 311.5mm x 236/246mm x 46.5mm (12.26” x 9.29”/9.69” x 1.83”)
The PCI1250A is compliant with the PCI Local Bus Specification Revision 2.1, and its PCI
interface can act as either a PCI master device or a PCI slave device. The PCI bus mastering is
initiated during 16-bit PC Card DMA transfers, or CardBus PC Card bridging transactions.
All card signals are internally buffered to allow hot insertion and removal without external
buffering. The PCI1250A is register compatible with the Intel 82365SL-DF ExCA controller. The
PCI1250A internal data-path logic allows the host to access 8-, 16-, and 32-bit cards using full
32-bit PCI cycles for maximum performance. Independent buffering and a pipeline architecture
provide an unsurpassed performance level with sustained bursting. The PCI 1250A can also be
programmed to accept fast posted writes to improve system-bus utilization.
The PCl1250A provides an internally buffered zoom video path. This reduces the design effort of
PC board manufacturers to add a ZV compatible solution and guarantees compliance with the
CardBus loading specifications. Multiple system interrupt signaling options are provided including:
parallel PCI, parallel ISA, serialized ISA, and serialized PCI. Furthermore, general purpose inputs
and outputs are provided for the board designer to implement sideband functions. Many other
features are designed into the PCI1250A such as socket activity LED outputs, and are discussed in
detail throughout the design specification.
An advanced CMOS process is used to achieve low system power consumption while operating at
PCI clock rates up to 33MHz. Several low-power modes allow the host power management system
to further reduce power consumption.
2.1.1 Features
• PCI Power Management Compliant
• 3.3 Volt Core Logic with Universal PCI Interfaces Compatible with 3.3 Volt and 5 Volt PCI
Signaling Environments
• Mix and Match 5V/3.3V PC Card16 Cards and 3.3V CardBus Cards
• Supports Two PC Card or CardBus Slots with Hot Insertion and Removal
• Pipelined Architecture allows Greater than 130 Mbytes per second throughput from CardBus
to PCI and from PCI to CardBus
• Multi-function PCI Device with Separate Configuration Space for each Socket
• Five PCI Memory Windows and Two l/O Windows Available to each PC Card16 Socket
• Two I/O Windows and Two Memory Windows Available to each CardBus Socket
• Provides VGA / Palette Memory and I/O, and Subtractive Decoding Options
A simplified block diagram of the PCI1250 is provided in following figure. The PCI interface
includes all address/data and control signals for PCI protocol. The interrupt interface includes
terminals for parallel PCI, parallel ISA, and serialized PCI & ISA signaling. The ring indicate
terminal is included in the interrupt interface, since it's function is to perform system wake-up on
incoming PC Card modem rings. Miscellaneous system interface terminals include GPIO signals,
PC/PCI DMA support signals, and socket activity LED signals.
This section describes the PCI1250A terminal functions. The terminals are grouped in tables by
functionality such as PCI system function, power supply function, etc. for quick reference. The
terminal numbers are also listed for convenient reference.
1
Terminal name for slot A is preceded with A_. For example, the full name for terminal T04 is A_A25.
2
Terminal name for slot B s preceded with B_. For example, the full name for terminal C14 is B_A25.
3
Terminal name for slot A is preceded with A_. For example, the full name for terminal W01 is A_ESET
4
Terminal name for slot B s preceded with B_. For example, the full name for terminal B13 is B_RESET
5
Terminal name for slot A is preceded with A_. For example, the full name for terminal N03 is A_CPAR.
6
Terminal name for slot B s preceded with B_. For example, the full name for terminal A19 is B_CPAR.
2.2.1 M1531
• Higher CPU bus frequency (up to 83.3 MHz) interface for the incoming Cyrix M2 and AMD K6,
PBSRAM and Memory Cache L2 controller
• Internal MESI tag bits (8K x 2) to reduce cost and enhance performance
• Smart deep buffer design for CPU-to-DRAM, CPU-to-PCI, and PCI-to-DRAM to achieve the
best system performance
• The most flexible 32/64-bit memory bus interface for the best DRAM upgrade ability and
ECC/parity design to enhance the system reliability
With the concurrent bus design, PCI-to-PCI access can run concurrently with CPU-to-L2 and CPU-
to-DRAM access, while PCI-to-DRAM access can run concurrently with CPU-to-L2 access. The
M1531 also supports the snoop ahead feature to achieve the PCI master full-bandwidth access
(133 MB) and provides the enhanced power management features including ACPI support,
suspend DRAM refresh, and internal chip power control to support the Microsoft’s On Now
technology OS.
The M1533 offers the best power management system solution. It integrates ACPI support, deep
green function, two-channel dedicated Ultra-33 IDE master controller, two-port USB controller,
SMBus controller, and PS2 keyboard/mouse controller.
The M1543 provides the best desktop system solution. It integrates ACPI support, green function,
two-channel dedicated Ultra-33 IDE Master controller, two-port USB controller, SMBus controller,
PS/2 keyboard/mouse controller and the Super I/O (Floppy Disk Controller, two serial port/one
parallel port) support.
The Aladdin-IV gives a highly-integrated system solution and a most up-to-date architecture to
provide the best cost/performance system solution for desktop and notebook vendors.
• Supports all Intel/Cyrix/AMD/TI/IBM 586 processors. Host bus at 83.3, 75, 66, 60 and 50 MHz
at 3.3V/2.5V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
A NC PHLDAJ AD3 AD6 AD8 AD12 PAR TRDYJ AD17 AD22 AD25 AD30 REQJ3 GNTJ2 GNTJ3 MPD2 MPD0 MD61 MD29 MD62
B BEJ0 PHLDJAD2 AD5 AD7 AD11 CBEJ1 DEVSELJ AD16 AD21 AD24 AD29 REQJ2 GNTJ1 MPD5 MPD1 MD63 MD27 MD60 MD28
C BEJ3 BEJ2 BEJ1 AD4 CBEJ0 AD10 AD15 STOPJ CBEJ2 AD20 CBEJ3 AD28 REQJ1 GNT0J MPD4 MD30 MD25 MD58 MD26 MD59
D BEJ6 BEJ5 BEJ4 AD0 AD1 AD9 AD14 LOCKJ FRAMEJ AD19 AD23 AD27 REQJ0 MPD7 MPD3 MD55 MD23 MD56 MD24 MD57
E DCJ HITMJ EADSJ BEJ7 RSTJ PCIMRQJ AD13 SERRJ IRDYJ AD18 PCLKIN AD26 AD31 MPD6 MD31 MD20 MD53 MD21 MD54 MD22
F BRDYJ BOFFJ SMIACTJ HLOCKJ ADSJ VCC_B VCC_C VCC_C MD50 MD18 MD51 MD19 MD52
G HD63 CACHEJ AHOLD KENJ NAJ VCC_A M1531 VCC_C MD15 MD48 MD16 MD49 MD17
H HD60 HD61 HD62 WRJ MIOJ GND GND GND GND GND GND MD45 MD13 MD46 MD14 MD47
J HD55 HD56 HD57 HD58 HD59 GND GND GND GND GND GND MD10 MD43 MD11 MD44 MD12
K HD51 HD52 HD53 HD54 HCLKIN GND GND GND GND GND GND MD40 MD8 MD41 MD9 MD42
L HD46 HD47 HD48 HD49 HD50 GND GND GND GND GND GND MD5 MD38 MD6 MD39 MD7
M HD41 HD42 HD43 HD44 HD45 GND GND GND GND GND GND MD35 MD3 MD36 MD4 MD37
N HD36 HD37 HD38 HD39 HD40 GND GND GND GND GND GND VDD5S REQJ4 GNTJ4 MD1 MD34 MD2
P HD31 HD32 HD33 HD34 HD35 VCC_A VCC_C 32K SUSPEND MD32 MD0 MD33
R HD26 HD27 HD28 HD29 HD30 VDD5 VCC_A VCC_B VCC_C RASJ6 RASJ7 CASJ2 CASJ7 CASJ3
T HD21 HD22 HD23 HD24 HD25 HD0 A12 A5 GWEJ COEJ CADVJ TWEJ MAA0 MAA1TIO8 TIO9 TIO10 RASJ1 RASJ0 CASJ6
U HD16 HD17 HD18 HD19 HD20 HD1 A13 A8 CCSJ BWEJ CADSJ TIO0 TIO1 MAB0 MAB1 MA5 MWEJ RASJ4 RASJ3 RASJ2
V HD15 HD14 HD13 HD6 HD3 A17 A14 A10 A4 A29 A25 A24 A23 TIO2 MA2 MA4 MA8 CASJ5 CASJ1 RASJ5
W HD12 HD11 HD10 HD5 HD2 A18 A15 A11 A7 A30 A31 A22 A21 TIO4 TIO6 MA3 MA7 MA10 CASJ0 CASJ4
Y HD9 HD8 HD7 HD4 A20 A19 A16 A9 A6 A3 A28 A26 A27 TIO3 TIO5 TIO7 MA6 MA9 MA11 NC
BRDYJ O Burst Ready. The assertion of BRDYJ means the current transaction is
Group A complete. The CPU terminates the cycle by receiving 1 or 4 active BRDYJs
depending on different types of cycles.
NAJ O Next Address. This signal is asserted by the M1531 to inform the CPU that
Group A pipelined cycles are ready for execution.
AHOLD O CPU AHold Request Output. It connects to the input of CPU's AHOLD pin
Group A and is actively driven for inquiry cycles.
EADSJ O External Address Strobe. This signal is connected to the CPU EADSJ pin.
Group A During PCI cycles, the M1531 asserts this signal to proceed snooping.
BOFFJ O CPU Back-Off. If BOFFJ is sampled active, CPU will float all its buses in the
Group A next clock. M1531 asserts this signal to request CPU floating all its output
buses.
HITMJ I Primary Cache Hit and Modified. When snooped, the CPU asserts HITMJ to
Group A indicate that a hit to a modified line in the data cache occurred. It is used to
prohibit another bus master from accessing the data of this modified line in
the memory until the line is completely written back.
MIOJ I Host Memory or I/O. This bus definition pin indicates the current bus cycle is
Group A either memory or input/ output.
DCJ I Host Data or Code. This bus definition pin is used to distinguish data access
Group A cycles from code access cycles.
WRJ I Host Write or Read. When WRJ is driven high, it indicates the current cycle is
Group A a write. Inversely, if WRJ is driven low, a read cycle is performed.
HLOCKJ I Host Lock. When HLOCKJ is asserted by the CPU, the M1531 will recognize
Group A the CPU is locking the current cycles.
CACHEJ I Host Cacheable. This pin is used by the CPU to indicate the system that CPU
Group A wants to perform a line fill cycle or a burst write back cycle. If it is driven
inactive in a read cycle, the CPU will not cache the returned data, regardless
of the state of KENJ.
HD[63:0] I/O Host Data Bus Lines. These signals are connected to the CPU's data bus.
Group A HD[63] applies to the most significant bit and HD[0] applies to the least
significant bit.
MPD[7:0] I/O DRAM Parity /ECC check bits. These are the 8 bits for parities/ECC check
Group C bits over DRAM data bus. MPD[7] applies to the most significant bit and
MPD[0] applies to the least significant bit.
RASJ[7] / O Row Address Strobe 7, (FPM/EDO) of DRAM row 7.
SRASJ[0] Group C SDRAM Row Address Strobe (SDRAM) copy 0. It connects to SDRAM RASJ.
This is a multifunction pin and determined by Index-5Ch bit0.
RASJ[6] / O Row Address Strobe 6, (FPM/EDO) of DRAM row 6.
SCASJ[0] Group C SDRAM Column address strobe (SDRAM) copy 0. It connects to SDRAM
CASJ. This is a multifunction pin and determined by Index-5Ch bit0.
RASJ[5:0] O Row Address Strobes. These signals are used to drive the corresponding
Group C RASJs of FPM/EDO DRAMs. In SDRAM, they are used to drive the
corresponding SDRAM CSJs.
CASJ[7:0] / O Column Address Strobes or Synchronous DRAM Input/Output Data Mask.
DQM[7:0] Group C These CAS signals should be connected to the corresponding CASJs of each
bank of DRAM. The value of CASJs equals that of HBEJs for write cycles.
During DRAM read cycles, all of CASJs will be active. In SDRAM, these pins
act as synchronized output enables during a read cycle and the byte mask
during write cycle, these pins are connected to SDRAM DQM[7:0].
MA[11:2] O DRAM Address Lines. These signals are the address lines[11:2] of all
Group C DRAMs. The M1531 supports DRAM types ranging from 256K to 64Mbits.
MAA[1:0] O Memory Address copy A for [1:0]. These signals are the address lines[1:0]
Group C copy 0 of all DRAMs.
MAB[1:0] O Memory Address copy B for [1:0]. These signals are the address lines[1:0]
Group C copy 1 of all DRAMs.
MWEJ[0] O DRAM Write Enable. This is the DRAM write enable pin and behaves
Group C according to the early-write mechanism, i.e. , it activates before the CASJs do.
For refresh cycles, it will remain deasserted.
MD[63:0] I/O Memory Data. These pins are connected to DRAM’s data bits. MD[63]
Group C applies to the most significant bit and MD[0] applies to the least significant bit.
CLKEN[0]/ I/O SDRAM Clock Enable Copy 0 or PCI Master Request. This signal is used as
REQJ[4] Group C SDRAM clock enable copy 0 to do self refresh during suspend. It can also be
used as bus request signal of the fifth PCI master. This function is controlled
by Index -5Dh bit 1.
GWEJ O Synchronous SRAM Global Write Enable. This signal will write all the byte
Group A lanes data into PBSRAM/Memory Cache.
COEJ O Synchronous SRAM Output Enable. This signal will enable the data output
Group A driving of PBSRAM/Memory Cache.
BWEJ O Synchronous SRAM Byte-Write Enable. This signal connects to byte write
Group A enable of PBSRAM/Memory Cache.
TIO[10]/ I/O SRAM Tag[10] or another copy of MWEJ or DRAM Cache MKREFRQJ. This
MWEJ[1]/ Group C pin is used for multifunction. It can be SRAM tag address bit 10, or another
MKREFRQJ copy of MWEJ connected to DRAM, or MKREFRQJ connected to DRAM
Cache. Refer to Register Index-41h bit 6, bit3 and bit0 description.
TIO[9]/ I/O SRAM Tag[9] or Synchronous DRAM (SDRAM) RAS copy 1. This pin is used
SRASJ[1] Group C for multifunction. It can be SRAM tag address bit 9, or another copy of
SRASJ connected to SDRAM. Refer to Register Index-41h bit3 and bit0
description.
TIO[8]/ I/O SRAM Tag[8] or Synchronous DRAM (SDRAM) CAS copy 1. This pin is used
SCASJ[1] Group C for multifunction. It can be SRAM tag address bit 8, or another copy of
SCASJ connected to SDRAM. Refer to Register Index-41h bit3 and bit0
description.
TIO[7:0] I/O SRAM Tag[7:0]. This pin contains the L2 tag address for 256-KB L2 caches.
Group B TIO[6:0] contain the L2 tag address and TIO7 contains the L2 cache valid bit
for 512-KB caches. TIO[5:0] contain L2 tag address, TIO7 contains L2 cache
valid bit and TIO6 contains the L2 cache dirty bit for 1-MB cache. Refer to
index-41h cache configuration table.
TAGWEJ O Tag Write Enable. This signal, when asserted, will write into the external tag
Group B new state and tag addresses.
CBEJ[3:0] I/O PCI Bus Command and Byte Enables. Bus commands and byte enables are
Group B multiplexed in these lines for address and data phases, respectively.
FRAMEJ I/O Cycle Frame of PCI Buses. This indicates the beginning and duration of a
Group B PCI access. It will be as an output driven by M1531 on behalf of CPU, or as
an input during PCI master access.
IRDYJ I/O Initiator Ready. This signal indicates the initiator is ready to complete the
Group B current data phase of transaction.
TRDYJ I/O Target Ready. This pin indicates the target is ready to complete the current
Group B data phase of transaction.
STOPJ I/O Stop. This signal indicates the target is requesting the master to stop the
Group B current transaction.
LOCKJ I/O Lock Resource Signal. This pin indicates the PCI master or the bridge intends
Group B to do exclusive transfers.
REQJ[3:0] I Bus Request signals of PCI Masters. When asserted, it means the PCI
Group B Master is requesting the PCI bus ownership from the arbiter.
GNTJ[3:0] O Grant signals to PCI Masters. When asserted by the arbiter, it means the PCI
Group B master has been legally granted to own the PCI bus.
PHLDJ I PCI bus Hold Request. This active low signal is a request from M1533/M1543
Group B for the PCI bus.
PHLDAJ O PCI bus Hold Acknowledge. This active low signal grants PCI bus to
Group B M1533/M1543.
PAR I/O Parity bit of PCI bus. It is the even parity bit across PAD[31:0] and CBEJ[3:0].
Group B
SERRJ/ I/O System Error or PCI Clock RUN. If the M1531 detects parity errors in
CLKRUNJ Group B DRAMs, it will assert SERRJ to notify the system. As CLKRUNJ, this signal
will connect to M1533 CLKRUNJ to start, or maintain the PCI CLOCK. It is a
multifunction pin and determined by Index-77h bit0.
Clock, Reset, and Suspend
HCLKIN I CPU bus Clock Input. This signal is used by all of the M1531 logic that is in
Group A the Host clock domain.
RSTJ I System Reset. This pin, when asserted, resets the M1531 state machine, and
Group B sets the register bits to their default values.
PCIMRQJ O Total PCI Request. This signal is used to notify M1533/M1543 that there is
Group B PCI master requesting PCI bus.
SUSPENDJ I Suspend. When actively sampled, the M1531 will enter the I/O suspend
Group C mode. This signal should be pulled high when the suspend feature is
disabled.
OSC32KO I The refresh reference clock of frequency 32 KHz during suspend mode. This
Group C signal should be pulled to a fixed value when the suspend feature is disabled.
2.2.2 M1533
The M1533 is a bridge between PCI and ISA bus, providing full PCI and ISA compatible functions.
This chip has Integrated System Peripherals (ISP) (2 x 82C59 and serial interrupt, 1 x 82C54),
advanced features (Type F and Distributed DMA) in the DMA controller (2 x 82C54), PS/2
keyboard/mouse controller, two-channel dedicated IDE master controller with Ultra-33
specification, System Management Bus (SMB), and two OpenHCI 1.0a USB ports. The ACPI
(Advanced Configuration and Power Interface) and PCI 2.1 (Delayed Transaction & Passive
Release) specification have also been implemented. Furthermore, this chip supports the
Advanced Programmable Interrupt Controller (APIC) interface for Multiple-Processors system.
The M1533 also supports the deep flexible green function for the best green system. It can
connect to the ALi Pentium North Bridge (M1521/M1531/M1541) and ALi Pentium Pro North Bridge
(M1615) to provide the best system solution. One eight-byte bidirectional line buffer is provided for
ISA/DMA master memory read/writes; one 32-bit wide posted write buffer is provided for PCI
memory write & I/O write (for audio) cycles to the ISA bus, to provide a PCI to ISA IRQ routing
table, and
level-to-edge trigger transfer.
The M1533 supports Super Green function for Intel and Intel compatible CPUs. It implements SMI
or SCI (System Controller Interrupt) to meet the ACPI specification. It also meets the requirement
for OnNow design initiative. It also features powerful power management for power saving
including On, Standby, Sleeping, SoftOff, and Mechanical Off states. To control the CPU power
consumption, it provides CPU clock control (STPCLKJ). The STPCLKJ can be active (low) or
inactive (high) in turn by throttling control. In addition, the M1533 offers the most flexible system
clock design. It can be programmed to stop the CPU Clock, PCI Clock, the Clock cell, or to reduce
the Clock frequency. The PBSRAM (Pipelined-burst SRAM) doze mode is also supported.
The M1533 is includes a PS/2 keyboard/mouse controller, SMBus, two OpenHCI 1.0a USB ports,
and the dedicated GPIO (General Purpose Input/Output) pins. These components enable the chip
to implement the best green and cost/performance system.
2.2.2.1 Features
• Provides a bridge between the PCI bus and ISA bus for both Pentium and Pentium Pro
systems
• PCI interface
• PCI master and slave interface
• PCI master and slave initiated termination
• PCI spec. 2.1 compliant (Delayed Transaction support)
• Buffers control
• 8-byte bidirectional line buffers for DMA/ISA memory read/write cycles to PCI bus
• 32-bit posted write buffer for PCI memory write and I/O data write (for sound card) to ISA
bus
• Interrupt controller
• Provides 14 interrupt channels
• Counter/Timers
• 8254 compatible timers for System Timer, Refresh Request, Speaker Output Use
• PMU features
• Full-support for ACPI and OS directed power management
• CPU SMM Legacy mode and SMI feature supported
• Supports programmable STPCLKJ: throttle/CKONSTP/CKOFFSTP control
• Supports I/O trap for I/O restart feature
• PMU operation states :
− On
− Standby
− Sleeping ( Power-On Suspend )
− Suspend ( Suspend to DRAM)
− Suspend to HDD
− Soft Off
− Mechanical Off
• APM state detection and control logic supported
• Global and local device power control logic
• Ten Programmable Timers: Standby / LB / LLB / APMA / APMB / Global_Display /
Primary_IDE / Secondary_IDE / SIO&Audio / Programmable IO Region
• Provides system activity and display activity monitorings, including:
− Video
− Audio
• USB interface
• One root hub with two USB ports based on OpenHCI 1.0a specification
• Supports FS (12Mbits/sec) and LS (1.5Mbits/sec) serial transfer
• Supports Legacy keyboard and mouse software with USB-based keyboard and mouse
• SMBus interface
• System Management Bus interface which meets the v1.0 specification
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
A NC AD21 AD18 CBEJ2 STOPJ AD14 AD9 AD5 AD0 SIDED7 SIDED10 SIDED2 SIDED15 SIDEAKJ SIDECS3J PIDED6 PIDED10 PIDED3 NC NC
B NC AD22 AD19 AD16 DEVSELJ AD15 AD10 AD6 AD1 PHLDJ SIDED5 SIDED12 SIDED0 SIDEIRDY SIDECS1J PIDED9 PIDED11 PIDED13 PIDED2 PIDED14
C CBEJ3 AD23 AD20 AD17 TRDYJ CBEJ1AD11 AD7 AD2 PHLDAJ SIDED9 SIDED3 SIDED14 SIDEIORJ SIDEA2 PIDED5 PIDED4 PIDED1 PIDED15PIDED0
D AD26 AD25 AD24 PCIRSTJ IRDYJ PAR AD12 CBEJ0 AD3 CLKRUNJ SIDED6 SIDED11 SIDED1 SIDEIOWJ SIDEA0 PIDED8 PIDED12 PIDEA1 PIDEA0 PIDEA2
E AD29 AD28 AD27 AD30 FRAMEJ SERRJ AD13 AD8 AD4 PCICLK SIDED8 SIDED4 SIDED13 SIDEDRQ SIDEA1 PIDED7 PIDEAKJ PIDECS1J PIDECS3J INTR
F USBCLK GPO8 AD31 INTAJ INTBJ VCC_B VCC_D VCC_E PIDEIOWJ PIDEIRDY NMI SMIJ IGNNEJ
G USBP0- USBP0+ GPO4 INTCJ INTDJ VCC_B M1533 VCC_3C PIDEDRQ PIDEIORJ CPURST A20MJ INIT
H USBP1- USBP1+ GPI3 GPO3 GPO2 GND GND GND GND GND GND IRQ13 STPCLK SMBDATA SMBCLK RI
J SD7 RSTDRV IOCHKJ GPI1 GPI0 GND GND GND GND GND GND GPO1 GPO20 GPIO19 GPIO18 GPIO17
K SD5 IRQ9 SD6 MSCLK MSDATA GND GND GND GND GND GND LLBJ DOCKJ GPIO16 GPIO15 GPIO14
L SD3 DREQ2 SD4 KBCLK KBDATA GND GND GND GND GND GND IRQ8J SUSTAT1J PWRBTNJ GPIO13 GPIO12
M IOCHRDY SD0 SD1 NOWSJ SD2 GND GND GND GND GND GND PWG HOTKEYJ RSMRSTJ LBJ LID
N IOWJ SA19 SMEMRJ AEN SMEMWJ GND GND GND GND GND GND VDD5S SIRQI SIRQII OSC32KII OSC32KI OSC32KO
P SA16 DACKJ3 SA17 IORJ SA18 VCC_A VCC_C GPO19 GPO18 GPO23 GPO22 GPO21
R DREQ1 SA14 DACKJ1 SA15 DREQ3 VDD5 VCC_A Vcc_3A VCC_A GPO17 GPO16 GPO15 GPO14 GPO13
T REFSHJ SA13 IRQ6 IRQ4 DACKJ2 BALE LA23 LA20 DACKJ0 MEMWJ DREQ6 ROMKBCSJ RTCAS RTCRW IRQ1I GPO12GPO11 GPO10 GPO9 GPO7
U SA12 IRQ7 IRQ5 IRQ3 TC OSC14M IRQ10 IRQ15 LA17 DREQ5 SD10 SD12 RTCDS XD0 XD4 EJECT GPIO11 GPO6 GPO5 GPO0
V SYSCLK SA10 SA8 SA5 SA2 M16J LA22 LA19 DREQ0 SD8 DACKJ7 SD13 SPKR XD1 XD5 ACPWR GPI6 GPIO8 GPIO9 GPI010
W SA11 SA9 SA7 SA4 SA1 SBHEJ IRQ11 IRQ14 MEMRJ DACKJ6 SD11 SD14 SPLED XD2 XD6 SETUPJ GPI4 GPI7 GPI8 NC
Y NC NC SA6 SA3 SA0 IO16J LA21 LA18 DACKJ5 SD9 DREQ7 SD15 EXTSW XD3 XD7 THRMJ CRT GPI2 GPI5 NC
2.3.1 Features
• 5 Volt Operation
• PC97 Compliant
• Keyboard Controller
• 8042 Software Compatible
• 8it Microcomputer
• 2k Bytes of Program ROM
• 256 Bytes of Data RAM
• Serial Ports
• Two Full Function Serial Ports
• High Speed NS16C550 Compatible UARTs with Send/Receive 16yte FlFOs
• Supports 230k and 460k Baud Programmable Baud Rate Generator Modem Control
Circuitry
• 480 Address and Eight IRQ Options
• Infrared Port
• Multiprotocol Infrared Interface
• 128yte Data FIFO
• IrDA 1.1 Compliant
• TEMIC/HP Module Support * Consumer IR
• SHARP ASK IR
• 480 Address, Up to Eight IRQ and Three DMA Options
The FDC37C67x with Consumer IR and IrDA v 1.1 support incorporates a keyboard interface,
SMC's true CMOS 765B floppy disk controller, advanced digital data separator, two 16C550
compatible UARTs, one Multi-Mode parallel port which includes ChiProtect circuitry plus EPP and
ECP, on-chip 24 mA AT bus drivers, two floppy direct drive support, Intelligent power management
and SMI support. The true CMOS 765B core provides 100% compatibility with IBM PC/XT and
PC/AT architectures in addition to providing data overflow and underflow protection. The SMC
advanced digital data separator incorporates SMC's patented data separator technology, allowing
for ease of testing and use. Both on-chip UARTs are compatible with the NS16C550. The parallel
port is compatible with IBM PC/AT architecture, as well as IEEE 1284 EPP and ECP. The
FDC37C67x incorporates sophisticated power control circuitry (PCC). The PCC supports multiple
low power down modes.
The FDC37C67x supports the ISA Plug-and-Play Standard (Version 1.0a) and provides the
recommended functionality to support Windows '95. The l/O Address, DMA Channel and Hardware
IRQ of each logical device in the FDC37C67x may be reprogrammed through the internal
configuration registers. There are 480 I/O address location options, 8 parallel IRQs, an optional
Serialized IRQ interface, and three DMA channels.
The FDC37C67x does not require any external filter components and is therefore easy to use and
offers lower system costs and reduced board area. The FDC37C67x is software and register
compatible with SMC's proprietary 82077AA core
Note 0: The interrupt request is output on one of the IRQx signals as an 024 buffer type. If EPP or ECP
Mode is enabled, this output is pulsed low, then released to allow sharing of interrupts. In this case, the
buffer type is OD24. Refer to the configuration section for more information.
Note 1: For 1 2it addressing, SAO:SA11 only, nCS should be tied to GND. For 1 6it external address
qualification, address bits SA11:SA15 can be "ORed" together and applied to nCS. The nCS pin functions
as SA11 in full 1 6it Internal Address Qualification Mode.CR24.6 controls the FDC37C67x addressing
modes.
Note 2: The "n" as the first letter of a signal name indicates an "Active Low" signal.
2.4.1 Features
• Highly integrated design Flat Panel and CRT GUI Accelerator & Multimedia Engine,
Palette/DAC, and Clock Synthesizer
• PCI Bus with Burst Mode capability and BIOS ROM support
• High Performance:
• Deep write buffers
• CRT Support
• 135 MHz RAMDAC
• Game Acceleration
• Source Transparent BLT
• Destination Transparent BLT
• Double buffer support for YUV and 15/16bpp Overlay Engine
• Instant Full Screen Page Flip
• Read back of CRT Scan line counters
• 36-bit direct interface to color and monochrome, single drive (SS), and dual drive (DD), STN &
TFT panels
• Flexible On-chip Activity Timer facilitates ordered shutdown of the display system
• Power Sequencing control outputs regulate application of bias voltage, +5V to the panel and
+12V to the inverter for backlight operation
• Multimedia Software
• Video Port Mana8er for ZV Port
• PCVideo DLL plus Tuner with DK Board
• Software Utilities
• DebugVGA
• Auto testing of all video modes
• ChipsVGA
• ChipsEXT
• Software Documentation
• BIOS OEM Reference Guide
• Display Driver User's Guide
• Utilities User's Guide
• Release Notes for BIOS, Drivers, and Utilities
• BIOS Features
• VGA Compatible BIOS
• PCI Bus Support
• PnP Support
• VESA VBE 2.0 (incl. DPMS)
• DDC 1, DDC 2AB
• Text and Graphics Expansion
• Auto Centering
• 44 (40) K BIOS
• CRT, LCD, Simultaneous display modes
• Auto Resolution Switch
• Multiple Refresh Rates
• NTSC/PAL support
• Extended Modes
• Extended BIOS Functions
• 1024x768 TFT, DSTN Color Panels
• Multiple Panel Support ( 8 panels built in)
• Get Panel Type Function
• HW Popup Interface
• Monitor Detect
• Pop Up Support
• SMI and Hot Key support
The HiQVideo family of high performance multimedia flat panel/CRT GUI accelerators extend
CHIPS' offering of high performance flat panel controllers for full-featured notebooks and sub--
notebooks. The HiQVideo family offers 64-bit high performance and new hardware multimedia
support features.
2.4.3.1 Technology
HiQColor
The 65555 integrates CHIPS breakthrough HiQColor technology. Based on a new proprietary
TMED (Temporal Modulated Energy Distribution) algorithm, HiQColor technology is a unique
process that enables the display of 16.7M colors on STN panels without dithering. TMED reduces
the need for panel turning associated with current FRC-based algorithms.
Independent of panel response times, the TMED algorithm eliminates all flaws such as shimmer,
Mach banding and crawling currently seen on STN panels. Combined with the new fast response
high contrast and low-crosstalk technology found in new STN panels. HiQColor technology enables
TF^T quality viewing on an STN panel. The 65555 provides the best color fidelity for the widest
variety of active and passive panels in the market.
The television output circuitry supports both NTSC and PAL television formats. The 65555
provides filtering circuitry to reduce the flicker circuitry to reduce the flicker seen when displaying
CRT resolution images on television screens. The television circuitry scales images to fit both PAL
and NTSC televisions.
The 65555 supports the ZV port PCMCIA standard for video input. The ZV port video data is fed
directly to the graphics memory to reduce traffic on the PCI Bus.
The HiQVideo family uses independent multimedia capture and display systems on-chip. The
capture system places data in display memory (usually off screen) and the display system places
the data in a window on the screen.
The capture system can receive data from either the system bus or from the ZV enabled video
port in either RGB or YUV format. The input data can also be scaled down before storage in
display memory. Capture of input data may also be double buffered for smoothing and to prevent
image tearing.
When the system writes to the video YW memory, the 65555 uses its PCI Bust Mode capabilities
to allow for a higher frame rate. Video capture input through the ZV port is scaled and stored into
memory allowing frame capture for video conferencing. In addition, the 65555 will use vertical
interpolation of video data up to 720 pixels wide to enable smooth zooming to full screen MPEG II
video. Double buffering is used to prevent image tearing.
The HiQVideo family supports a wide variety of monochrome and color Single-Panel, Single-Drive
(SS) and Dual-Panel, Dual Drive (DD) standard and high-resolution passive STN and acfive matrix
TFT/MIM LCD, and EL panels. For monochrome panels, up to 64 gray scales are supported. With
the help of HiQColor Technology, STN panels can afford 256 gray shades per primary resulting in
16M colors for an improved image representation. Additionally, the HiQVPro also supports TFT
panels up to 36-bit interface. The HiQVideo family offers a variety of programmable features to
optimize display quality. Vertical centering and stretching are provided for handling modes with
less than 480 lines on 480line panels. Horizontal and vertical stretching capabilities are also
available for both text and graphics modes for optimal display of VGA text and graphics modes on
800x600 and 1024x768 panels. Three selectable color-to-gray scale reduction techniques and
SMARTMAP are available for improving the ability to view color applications on monochrome
panels.
The HiQVideo family uses a variety of advanced power management features to reduce power
consumption of the display sub-system and to extend battery life. Although optimized for 3.3V
operation, the HiQVideo controller's internal logic, memory interface, bus interface, and panel
interfaces can be independently configured to operate at either 3.3V or 5V.
The HiQVideo controllers are fully compatible with VGA at the register, and BIOS levels. CHIPS
and third-party vendors supply fully VGA-compatible BIOS, end-user utilities and drivers for
common application programs such as Microsoft Windows and OS/2.
The 65555 BIOS and drivers are an evolutionary step from the 65554 software. The Windows
drivers provided for the 65555 are compliant with both Microsoft WHQL and PC97 standards.
The 65555 supports the following 32-bit wide and 64-bit wide memory configuration show below:
The figure below shows the display memory configurations using and external STN-DD buffer:
2.4.4.1 Introduction
The following pages contain the BGA ball assignments and a list of all the pins for the 65555 GUI
Accelerator. The pins are divided into the following groups:
• PCI Bus
All signals listed above are powered by BVCC and GND. ROMOE# is powered by
MVCC and GND.
Mono Mono Mono Color Color Color Color Color Color Color Color Color
Pin# Pin 8-bit 8=bit 16 bit 9/12/16bit 18/24 bit 36 bit 18/24 bit 8-it(4bP) 8-bit(4bp) 8-bit(4bp) 8-bit(4bp) 8-bit
Name
Note: HSYNC, VSYNC, GPIO2, and gpio3 are powered by CVCC and GND. RED, GREEN, BLUE and
RSET are powered by AVCC and AGND.
Note: All signals listed above are powered by VVCC and GND.
Boundary Scan
A1 TMS In High Test mode select for boundary scan
B2 TCLK(DCLKIN) In High Test clock for boundary scan. Can be configured to
be used as an input for an externally provided
DCLK through a strapping option. See the
descriptions for registers XR70 and XRCF for
complete details
Note: TMS, TCLK, TDI, TDO and TRST#, are powered by BVCC and GND.
Miscellaneous
E4 STNDBT# In Low Standby Control Pin. Pull this pin low to place the
chip in Standby Mode. A low to high transition on
the pin will cause change to exit standby mode,
host standby mode. and panel off mode.
C3 REFCLK(MCLKIN) In High Reference Clock Input. This pin serves as the input
for an external reference oscillator (usually
14.31818 MHz). All timings of the 65555 are
derived from this primary clock input source. Can
be configured to be used as an input for an
externally provided MCLK through a strapping
option and register programming. For normal
operation. TDI should be used as the input for an
externally provided MCLK
V1 GPIO0(ACTI) I/O High General Purpose l/O pin, or ACTI (Activity
Indicator).
T4 GPIO1(32KHz) I/O High General Purpose l/O pin, or 32KHz input: clock
input for refresh of non-self-refresh DRAMs and
panel power sequencing
D6 N/C n/a n/a These pins should be left open.
C5 N/C n/a n/a
A12 N/C n/a n/a
K19 N/C n/a n/a
Y20 Reserved n/a n/a These pins are reserved for future use, and should
D8 Reserved n/a n/a not be connected.
D17 Reserved n/a n/a
A4 Reserved n/a n/a
B5 Reserved n/a n/a
D4 Reserved n/a n/a
U16 Reserved n/a n/a
C20 Reserved n/a n/a
E17 Reserved n/a n/a
Note: STANDBY#, RCLK, GPIO0, and GPIO1 are powered by DVCC and GND.
2.5.1 Overview
• Serial l/O function (either clock synchronous or UART method selectable in software)
• 8-bit timers
• 8-bit Comparator
2.5.2 Description
The functions of the M38813M4-XXXHP are outlined in Table1.1.1. In this manual, the suffix HP
indicates a 0.5mm-lead pitch QFP.
Parameter Function
Basic instructions 71
Instruction execution time 0.5µs (shortest instruction, at 8MHz oscillation frequency)
Oscillation frequency 8MHz (max.)
Memory size ROM 16384 bytes of user area
RAM 512 bytes
Input/output ports P0-P4 8-bit X 5
P5 4-bit X 1
P6 2-bit X 1
Serial l/O Clock synchronous or asynchronous
Timers 8-bit prescaler x 2 and 8-bit timer x 3
Comparator 4-bit resolution x 8 channels
Bus interface Two 8-bit Master CPU bus interface
Key on wake up 8 inputs
Interrupts 8 external, 9 internal, 1 software
Clock generation circuit Built-in (connect to external ceramic resonator or quartz crystal oscillator)
Supply voltage f(XIN)=8MHz 4.0 to 5.5V
Parameter Function
Output current 10mA (15mA for P24-P27)
Operating temperature range -20 to 85°C
Device structure CMOS silicon gate
Package M38813M4-XXXHP 64-pin plastic molded QFP (0.5mm-
lead pitch)
2.6.1 Features
• Built-in OPL3
• Built-in Joystick
• Supports multi-purpose pin function (Support 16-bit address decode, DAC interface for OPL4-
ML, Zoomed Video port, EEPROM interface, MODEM interface, IDE CD-ROM interface)
• Supports Power Management(power down, power save, partial power down, and
suspend/resume) ..
• +5V/ +3.3V power supply for digital, 5V power supply for analog.
Your computer is already properly configured and optimized, and you do not need to run this utility.
However, if you encounter configuration problems, you may need to run Setup. Please also refer
to Appendix E, BIOS Post Checkpoints when a problem arises.
To activate the Setup Utility, press F2 after you hear a beep while the Extensa logo is being
displayed.
When Silent Boot (described later in this chapter) is disabled, a message displays telling you when
you can press F2 to run the Setup Utility.
BIOS V3.0
------------------------------------------------------------------------------------------------------
016384 KB Memory Good
SETUP Utility
Press ↑ and ↓ to move the highlight bar; press → and ← to change the setting of the highlighted
parameter. To exit this screen and return to the main screen, press Esc.
The following table describes the parameters in this screen. Settings in boldface are the default
and suggested parameter settings.
Startup Configuration
Press ↑ and ↓ to move the highlight bar; press → and ← to change the setting of the highlighted
parameter. To exit this screen and return to the main screen, press Esc.
The following table describes the parameters in this screen. Settings in boldface are the default
and suggested parameter settings.
Press ↑ and ↓ to move the highlight bar; press → and ← to change the setting of the highlighted
parameter. To exit this screen and return to the main screen, press Esc.
The following table describes the parameters in this screen. Settings in boldface are the default
and suggested parameter settings.
System Security
Press ↑ and ↓ to move the highlight bar; press → and ← to change the setting of the highlighted
parameter. To exit this screen and return to the main screen, press Esc.
The following table describes the parameters in this screen. Settings in boldface are the default
and suggested parameter settings.
Press ↑ and ↓ to move the highlight bar; press → and ← to change the setting of the highlighted
parameter. To exit this screen and return to the main screen, press Esc.
The following table describes the parameters in this screen. Settings in boldface are the default
and suggested parameter settings.
Pressing Fn-F6 during normal computer operation (after POST) also brings up the power
management screen. An additional page, shown below, is added to this function which appears
only via Fn-F6.
Esc=Exit
The System Information Reference screen gives a summary of your computer’s BIOS information.
These items are easy to understand and are self-explanatory.
Note: The Serial Number and BIOS Versions are important information about your
computer. If you experience computer problems, this data helps our service
personnel know more about your computer.
[Yes] [No]
• Wrist grounding strap and conductive mat for preventing electrostatic discharge
• Flat-bladed screwdriver
• Phillips screwdriver
• Hexagonal screwdriver
• Tweezers
• Plastic stick
The screws for the different components vary in size. During the disassembly
process, group the screws with the corresponding components to avoid
mismatch when putting back the components.
Before proceeding with the disassembly procedure, make sure that you do the following:
2. Unplug the AC adapter and all power and signal cables from the system.
3. Press the battery compartment cover release button and slide out the cover.
4. Pull out the battery pack using the pull loop at the end.
Removing all power sources from the system prevents accidental short circuit
during the disassembly process.
The cables used here are special FPC (flexible printed-circuit) cables, which are
more delicate than normal plastic-enclosed cables. Therefore, to prevent
damage, make sure that you unlock the connectors before pulling out the cables.
Do not force cables out of the connectors.
Unplugging Plugging
the Cable the Cable
Unplugging
the Cable
Plugging
the Cable
The disassembly procedure described in this manual is divided into four major sections:
The following table lists the components that need to be removed during servicing. For example, if
you want to remove the motherboard, you must first remove the keyboard, then disassemble the
inside assembly frame in that order.
The flowchart on the succeeding page gives a clearer and more graphic representation on the
entire disassembly sequence. Please refer to it from time to time, together with the screw list
below.
SCREW LIST
Unplug K/B
Modem conector
Battery DIMM HDD
Module
Remove Remove
K/B LED Cover
Bx2
Remove Unplug
LED Cover Inverter Cable
Bx1
Cx4 Dx4
Remove Display
Heat Sink Module
Dx8 Ex4
Gx2
Display
Unplug CPU Lower Release
Bazel
Cables Heat Sink Case Latches
Ix2
Fx3
Ix3
Ix4
Jx1
Audio Touch
Speaker M/B
Board Pad
Bx2
Hx2
PCMCIA Charger
Socket Board
1. Turn off the computer. Then turn the computer over to access its base.
2. Remove three screws from the memory door; then lift up and remove the memory door.
4. Align the connector edge of the memory module with the key in the connector. Insert the edge
of the memory module board into the connector. Use a rocking motion to fully insert the
module. Push downward on each side of the memory module until it snaps in place.
To remove the memory module, release the slot locks found on both ends of the memory slot
to release the DIMM. Then pull out the memory module.
Sleep Manager must be run after installing additional memory for the
computer to hibernate properly. If Sleep Manager is active, it will
automatically adjust the hibernation file on your notebook.
If you are using an operating system other than Windows 95 or DOS, you
may need to re-partition your hard disk drive to allow for the additional
memory. Check with your system administrator.
1. Turn the computer over and locate the hard disk drive bay cover.
2. Press the hard disk drive bay cover release and slide the cover out to remove it. Set aside the
cover.
3. Pull the hard disk drive tab to remove the hard disk drive from the hard disk drive bay.
If you want to install a new hard disk drive, reverse the steps described above.
1. Slide out the two display hinge covers on both sides of the notebook.
2. Using a pointed instrument, unlock the keyboard locks. Then pull out and flip down the
keyboard to expose the keyboard connectors.
2. Remove the five screws that secure the heat sink assembly to the housing.
1. Remove two screws on the bottom and two screws on the rear of the unit.
2. Open the display and remove two screws; then pull up the display cable (CN9) and unplug the
inverter cable (CN8).
2. Unplug the two internal drive cables (CN17 for FDD; CN17 and CN20 for CD-ROM).
Ensure the drive cables do not become hooked on the inside frame assembly
when removing and reinstalling the drive.
Gently pull out the CPU heat sink and the CPU board (CN21) from the mainboard.
Follow these steps to detach the top cover from the bottom cover:
1. Unplug the touchpad cable (CN6) from the keyboard/touchpad board, and the audio board
cable (CN14), speaker cables (CN13 and CN15) and optionally, the fan connector found just
above the speaker cables (CN12) from the mainboard.
1. Remove the screws found on the lower case (ten total screws, two screws shorter than the rest
found on the front corners of the computer).
2. Remove the keyboard/touchpad board (CN18). Remove two screws and remove the plate
that covers the DC-DC converter board.
Figure 4-21 Removing the Keyboard/Touchpad Board and DC-DC Converter Board Cover
4. Unplug the battery charger connector (CN22) and remove four screws that secure the
motherboard to the base assembly. Then pull up to remove the mainboard.
Unplug the charger board (containing the power switch, DC-in jack and PS/2 port).
The PC Card Connector Module is normally part of the motherboard spare part. The following
removal procedure is for reference only.
The touchpad, speakers, audio board are connected to the top cover. The sections below describe
the removal process of these components.
Pull up to remove the hard disk drive heat sink from the top cover.
1. Remove four screws and lift up the metal plate and touchpad buttons.
2. Unplug the touchpad cable (J1) and remove the touchpad main sensor and connector unit.
2. The flip up the wire that holds the speaker in place and remove the speaker.
1. Remove the two oval LCD bumpers at the top of the display; use a pointed instrument to
remove the two mylar stickers on the bottom of the display.
STN and TFT LCDs use the same bezel but different panels.
390XX - X X X X
Brand
T: TI
CPU/Media Bay/Memory/Battery
0: W/O CPU,W/O CD-ROM,W/O Memory,W/O Battery Uniload Model
(Bulk pack)
1: P55C-166+CD-ROM+16MB RAM+Li-Ion Battery+Modem
2: P55C-166+CD-ROM+16MB RAM+Ni-MH Battery+Modem
3: P55C-150+CD-ROM+16MB RAM+Ni-MH Battery+Modem
4: P55C-133+CD-ROM+16MB RAM+Ni-MH Battery+Modem
5: P55C-133+FDD+16MB RAM+Ni-MH Battery
6: P55C-200+CD-ROM+16MB RAM+Li-Ion Battery+Modem
7: P54C-150+FDD+16 MB RAM + Ni-MH Battery
HDD:
0: No Hard Disk 3: 340MB A: 1GB
1: 120MB 5: 520MB C: 1.35GB
2: 200MB 8: 810MB D: 1.4GB/1.6GB
B: 250MB 9: 1.3GB E: 2.0GB
LCD:
C:12.1" SVGA DSTN
CX:12.1" SVGA TFT
No. Description
B-1 System assembly
B-2 CD-ROM Drive assembly
B-3 LCD Module assembly
B-4 Upper Case assembly
B-5 Lower Case assembly
B-6 LCD Bezel assembly
Schematics
This appendix shows the schematic diagrams of the notebook.
No. Description
D-1 CPU Connector
D-2 M1531
D-3 M1533
D-4 ISA Pull High and Pull Low
D-5 Cache RAM and TAG RAM
D-6 DIMM Socket 1
D-7 DIMM Socket 2
D-8 CY2272 Clock Generator
D-9 VGA Controller Chip 65555 and VRAM
D-10 CRT and LCD Connector
D-11 PCMCIA Controller Chip PCI 1250
D-12 PCMCIA Socket and Power Controller TPS2206
D-13 M38813 and LED and Charger SMBUS
D-14 Super I/O SMC672 and RS232 MAX3243
D-15 Parallel and Serial Port
D-16 USB and FIR and Buzzer and Fan
D-17 Audio Chip YMF715
D-18 OP AMP LM4863 and Datarace and Jack
D-19 RTC and BIOS ROM
D-20 IDE Connector
D-21 Golden Finger and Modem Connector
D-22 DC-DC and Charger and Battery Connector
D-23 Port Replicator
Schematics
+2.9V
1
C379 C352 C351 C361 C360 C355 C354
2 ST100U10VDM SCD1U SCD1U SC1KP SC1KP SCD1U SC1KP
2,5 $CPUD[0..63]
$CPUA[3..31] 2,5
1 |LINK CPU BOARD CONN.
2 |PCI.SCH M1531
3 |ISA.SCH M1533
4 |ISA_1.SCH M1533 BYPASS CAP&PULL HIGH RISSITOR
5 |CACHE.SCH CACHE RAM & TAG RAM & AVAILABLE TTL GATE
6 |DIMM1.SCH DIMM SOCKET#1
7 |DIMM2.SCH DIMM SOCKET#2
8 |CLKGEN.SCH CLOCK GEN CY2272
IO_VOLTAGE 9 |VGA.SCH 65555 VGA CONTROLLER CHIP
10 |VIDEO.SCH CRT&LCD CONN
11 |PCI1250.SCH PCI1250 PCMCIA CONTROLLER CHIP
12 |PWCON.SCH TPS2206 PCMCIA POWER CONTROL & SOCKET
RP59 RP62 13 |KBC.SCH KB CONTROLLER 38813 CHIP
$CPUADS#
1 10 $INV 1 10 14 |SIO.SCH SUPER IO SMC672&RS232 MAX3243
$HITM# 2 9 $D/C# $KEN# 2 9 $WB/WT# 15 |PORT.SCH PARELL PORT&SERIAL PORT
$W/R# 3 8 $FERR# $BRDY# 3 8 $SMIACT# 16 |USB.SCH USB&FIR&FAN CONTROLL&BUZZER
$A20M# 4 7 $M/IO# $STPCLK#4 7 $IGNNE# 17 |AUDIO.SCH AUDIO CHIP YMF715
5 6 $CACHE# 5 6 $SMI# 18 |AUDIO_1.SCH AUDIO AMP LM4863
19 |RTCROM.SCH RTC(BQ3285)&FLASH ROM
SRP10K SRP10K 20 |IDE.SCH HDD&CD_ROM&INTERNAL FDD CONN
21 |FINGER.SCH GOLD FINGER & MODEM MODULE
22 |POWER.SCH CHARGER & DC-DC & BAT CONN
23 |DOCK.SCH PORT REPLICATOR
RSTDRV
4
4,14,17,19,21
SRN33
NOCON 15
16 FIR_EN# $AD10 AD10 IRQ3 IRQ3 4,11,14,17,21
$AD9 A7 AD9 IRQ4T4 IRQ4 4,11,14,21
1 CPU_COM $AD8 E8 AD8 IRQ5U3 IRQ5 4,11,14,17,21
$AD7 C8 T3
13 COVERSW
13 HOTKEY1
$AD6
$AD5
$AD4
B8
A8
E9
AD7
AD6
AD5
AD4
M1533 IRQ6
IRQ7
IRQ9
IRQ10
U2
K2
U7
IRQ6
IRQ7
IRQ9
IRQ10
4,14
4,14,17
4,11,17
4,11,14,17,21
MODEM_EN#
FLASH_ON
21
19,21
$AD3 D9 AD3 IRQ11 W7 IRQ11 4,11,14,17,21
2,9,11 $CBE#[0..3] $AD2 C9 AD2 IRQ14 W8 IRQ14 4 USB_O/I USB_OUT/IN 16,23
$AD1 B9 AD1 IRQ15 U8 IRQ15 4,11
$AD0 A9 AD0 LA17U9 LA17 SLEEP# 22
$CBE#3 C1 CBEJ3 LA18Y8 LA18
$CBE#2 A4 CBEJ2 LA19V8 LA19 USB_ON# 16
$CBE#1 C6 CBEJ1 LA20T8 LA20
+3.3V $CBE#0 D8 CBEJ0 LA21Y7 LA21 GPIO16 BUFFER_EN 23
2,9,11 $FRAME# E5 FRAMEJ LA22V7 LA22
1 2,9,11 $TRDY# C5 TRDYJ LA23T7 LA23 GPIO15 ENAUDIO# 18
R94 2,9,11 $IRDY# D5 IRDYJ Y5
SA0 SA0
10KR3 2,9,11 $STOP# A5 STOPJ W5
SA1 SA1 +3.3V BAT_IN# 4
2,9,11 $DEVSEL# B5 DEVSELJ V5
SA2 SA2
2 E6 SERRJ Y4
SA3 SA3 ZVA_ON 18
2,9,11 $PAR D6 PAR W4
SA4 SA4 1
2 $INTA# F4 INTAJ_MI V4
SA5 SA5 RX4 ZVB_ON 18
9,11 $SERR# 2 $INTB# F5 INTBJ_S0 Y3
SA6 SA6 47KR3
2,11 $INTC# G4 INTCJ_S1 W3
SA7 SA7 XDIR 4,19
2,11 $INTD# G5 INTDJ_S2 V3
SA8 SA8 DX1 2
2 $PHLDA# C10 PHLDAJ W2
SA9 SA9 $32K 2 1 $32KO 2,9
B10 PHOLDJ SA10V2 SA10
RX41 8 $P33CLK E10 PCICLK SA11W1 SA11 S1N4148 $AMSTAT# $AMSTAT# 4
+3.3V 1 2 2,11 $CLKRUN# D10 CLKRUNJ SA12U1 SA12
1 $CPUINIT G20 INIT SA13T2 SA13 +3.3V $PWRBTN# $PWRBTN# 4
2K7R3 +3.3V 1 $CPURST G18 CPURST SA14R2 SA14
1 $IGNNE# F20 IGNNEJ SA15R4 SA15
1 1 $INTR E20 INTR SA16P1 SA16 1
R153 1 $NMI F18 NMI SA17P3 RZ3
10KR3 1 $A20M# G19 A20MJ SA18P5 33KR3
1 $FERR# H16 FERRJ/IRQ13 SA19N2
2 $PHOLD# 2 1 $STPCLK# H17 STPCLKJ U14
XD0 XD0 DZ1 2
19 RTC256 J17 SLEEPJ/GPO20 V14
XD1 XD1 $SUS# 2 1 $SUSPEND# 2,11
5 $ZZ J16 ZZ/GPO1 W14
XD2 XD2
DSD15 C19 PIDE_D15 Y14
XD3 XD3 S1N4148 VOLUP# 17
NORMAL MODE DSD14 B20 PIDE_D14 U15
XD4 XD4
DSD13 B18 PIDE_D13 V15
XD5 XD5 VOLDWN# 17
DSD12 D17 PIDE_D12 W15
XD6 XD6
DSD11 B17 PIDE_D11 Y15
XD7 XD7 IRQ12 13
DSD10 A17 PIDE_D10 SD0/GPIO0 M2 CHKPW
DSD9 B16 PIDE_D9 SD1/GPIO1 M3 MATRIX1 IRQ1 13
20 DSD[0..15] DSD8 D16 PIDE_D8 SD2/GPIO2 M5 MATRIX2
DSD7 E16 PIDE_D7 SD3/GPIO3 L1 DISCHG 22 $PCISTP# $PCISTP# 8
DSD6 A16 PIDE_D6 SD4/GPIO4 L3 W_PROTEC# 22
DSD5 C16 PIDE_D5 SD5/GPIO5 K1 NTSC/PAL# 23 $CPUSTP# $CPUSTP# 8
DSD4 C17 PIDE_D4 SD6/GPIO6 K3 EXT_FDD_5V_ON 23
DSD3 A18 PIDE_D3 SD7/GPIO7 J1 DISABLE 22
DSD2 B19 PIDE_D2 V10
SD8 SD8 $PCIREQ# $PCIREQ# 2
DSD1 C18 PIDE_D1 Y10
SD9 SD9
DSD0 C20 PIDE_D0 SD10U11 SD10
20 PDSA2 D20 PIDE_A2 SD11W11 SD11 CONTRAT CONTRAST 10
20 PDSA1 D18 PIDE_A1 SD12U12 SD12
20 PDSA0 D19 PIDE_A0 SD13V12 SD13 +3.3V
20 PIDECS3# E19 PIDE_CS3J SD14W12 SD14 POWER_LED 4,22
20 PIDECS1# E18 PIDE_CS1J SD15Y12 SD15 1
PIDEDQ G16 PIDE_DRQ A20
NC R151
20 PIDE_DACK# E17 PIDE_AKJ A19
NC 15KR3 SERIRQ 4
PIDERY F17 OO Y20
G17 PIDE_RDY VV NC
W20 2
20 PIDIOR# PIDE_IORJ P
I SSSSSS S
I S
I SSSS I S
I C
RCR NC
D I I I I I I SS SSSS SSS SSSS DDI I I DD J J $SMBCLK $SMBCLK 1,7,8,12
E DDDDDDI I I I I I I I I I I I I EE DDDEEUUUUU0 1 VV V
_ EEE EE EDDDDDDDDDDDDD_ _ EEE _ _ SSS SS/ / V VVVCCVVV VDV +3.3V
I S _ _ _ _ _ _ EE EEEE EEE EEEE CC_ _ _ I I BBB BBGG CCCCCCDCCCDC
OMDDD DD D_ _ _ _ _ _ _ _ _ _ _ _ _ S S DA R OOCP P P P P P G GGGG GGG GGG GGGGG G GGGGG GGG GGG GGGG GG GGC CCC_ _ DCC C_ C
R291 WI 1 1 1 1 1 1 D D D D D D D D D D A A A 3 1 R K D R WL 0 0 1 1 I I N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N _ _ _ _ 3 3 _ _ _ _ 5 _ N N N N 1
1 2 PIDEDQ J J 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 2 1 0 J J QJ Y J J K + - + - 0 1 D DDDD DDD DDD DDDDD D DDDDD DDD DDD DDDD DD DDB B DE C A 5 A C A S A C C CC R152
20 PIDEDRQ
33R3 F F A C E B D A C E A D B E C A D B C E D A B E A B C D F G G H H J J J J J J K K K K L L L L M M M M N N N N N N M M L L K K J J H H H H H H F G F F G R R R P R N P A B Y Y M1533 15KR3
1 111 1111 111 11 1111 1111 111 11 1112 121 5491 119 11 1911 191 11111 1981 8 1818 1811 119 866 111 167 1116 1112
6 933 3221 110 11 2223 3555 554 44 44 0 12 01 2 01 2 0 12321 0 3 3 3 3 32 10 455 4 555 2
R304 20 PIDIOW# SSSSSSSSSSSSSSSSSSS S S $SMBDATA $SMBDATA 1,7,8,12
20 SIDEDRQ 1 2 SIDEDQ I I I I I I I I I I I I I I I I I I I I I
DDDDDDDDDDDDDDDDDDD D D 1 RX3 2 +3.3V
33R3 1 $SMI# 1 2 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0 AAA E E 100KR3 +3.3V
20 PIDERDY PIDERY RX8 543 210 210 D R
0R3 Q D $OVCR#0 16 +3.3V +5V
SIDERDY Y
20 SIDERDY 20 SIDECS3#
20 SIDECS1# 1 RZ2 2 8 76 5
RP24
22 PWR_SW# 20 SIDE_DACK#
20 SIDIOR# 1 10KR3 2 $USBP00 4,16,23 CX12 CX13 SRN10K
+3.3V 20 SIDIOW# RZ1 SCD1U SC1KP
10KR3 ACER TAIPEI TAIWAN R.O.C
20 SID[0..15] R132 1 23 4
1 1 2 IO_VOLTAGE M1533
RZ4 20 SIDA[0..2] 8 $USBCLK SW1 Title
33KR3 R138 33R3 OEM 1 8 390 ACERNOTE LIGHT
4,16,23 $USBP01 1 2 CHKPW 2 7
2 DZ2 C164 MATRIX1 3 6 Size Document Number REV
9,23 $STANDBY# 1 2 STDBY# 33R3 SC33P C160 MATRIX2 4 5 A2 96183 SD
SC33P
S1N4148 KHS04 Date: August 21, 1997 Sheet 3 of 23
M1533 BYPASS CAPACITORS
R116
3 SMEMW# 1 2 RP67
+5v 3,11,14,17,21 IRQ3 IRQ3 1 8
DUMMY-R3 3,11,14,21 IRQ4 IRQ4 2 7
3,11,14,17,21 IRQ5 IRQ5 3 6
3,14 IRQ6 IRQ6 4 5
1 +5V
C171 C173 3 SMEMR# SRN10K
2 ST4D7U SC1KP RP69
3 N0WS# 1 10
3,21 IOCHK# 2 9 M16# 3 R110
3 REFSH# 3 8 3 $AMSTAT# 1 2
Near pin [R7] 3,21 SBHE# 4 7
+5V 5 6 DUMMY-R3
SRP10K
+5V 3 SYSCLK RP66
USE +5V 3,14,17 IRQ7 IRQ7 1 8
3,11,17 IRQ9 IRQ9 2 7
RP18 3,11,14,17,21 IRQ10 IRQ10 3 6
C161 1 10 3,11,14,17,21 IRQ11 IRQ11 4 5
SCD1U 3,14 DACK#5 DACK#5 2 9 DACK#3 DACK#3 3,14
3,14 DACK#6 DACK#6 3 8 DACK#0 DACK#0 3,14 SRN10K
3,14 DACK#7 DACK#7 4 7 DACK#2 DACK#2 3,14
+5V 5 6 DACK#1 DACK#1 3,14
CLOSE TO PIN [P6] SRP4K7
+3.3V
R328
USE 1 2
+5V RP8 RN8 0R3
4,14,17 DRQ1 DRQ1 1 10 13 IRQ1 1 8
4,14,17 DRQ3 DRQ3 2 9 DRQ0 DRQ0 4,14,17 13 IRQ12 2 7
3 8 DRQ5 DRQ5 3,4 3 IRQ14 3 6
4,14,17 DRQ2 DRQ2 4 7 DRQ6 DRQ6 3,4 3,11 IRQ15 4 5
C179 C159 5 6 DRQ7 DRQ7 3,4
SCD1U SCD1U SRN10K
SRP4K7
R83
1 1 U32A 2 1 CCFT CCFT 3
C170 C153 4
2 ST4D7U SC1KP 47KR3 +5V
3 RSTDRV 1 2 RSTDRV# 13,20 R333
R96 3,14,21 IOCHRDY IOCHRDY# 1 2
CLOSE TO PIN [N15] 7 SSHCT14 1 2 POSSTA 3 1KR3
10KR3
+5V
+5v
R324
3,21 IO16# 1 2
R273
1 2 $USBP00 3,16,23 1KR3
C169 C172
SC1KP SCD1U 10KR3
R274
1 2 $USBP01 3,16,23 R106
3 $PWRBTN# 1 2 PWR_SW# 22
10KR3
CLOSE TO PIN [R6] +5V 0R3
+3.3V
1
RX10
+3.3V 47KR3 1
+5V RX31
2 1 U9A 100KR3
4
1 10 VSW1 1 2
C133 C134 3 CRT 13 BAT_IN# 3
SCD1U 2 ST4D7U 10 VSW3 2
7 SSHCT08 UX1
1 1 OUT NC 5
RX11 +5V RZ5
NEAR PIN [P15],[G15] 47KR3 R334 BT+ 1 2 2 VDD
1 2 ROMKBCS# 3
2 1KR3 3 GND NC 4
10KR3 2
+3.3V +3.3V S-80750SN
+5V DZ3
NORMAL MODE MMBZ5246B
+3.3V 1 +5V
C132 C152 +5V
SCD1U SCD1U 1 U11A R111
4 1 1 2 XDIR 3 1
R105 R119
3 DISPLAY 2 3 1 2 $DISPLAY 10 10KR3 100KR3
CLOSE TO PIN [F15] CLOSE TO PIN [G6]
100R3 PENTIUM CPU 2
1 7 SSLVT125
R104 3 GPI10
47KR3 3 SPLED
+3.3V
2 1
1 R127
R97 DUMMY-R3
1 +5V 1KR3
C131 C135 +5V R211
SCD1U 2 ST4D7U R160 3 POWER_LED 1 2 2 2
3 SERIRQ 1 2
10KR3
10KR3
APIC DISABLE FOR 256K ROM
CLOSE TO PIN [R14]
PULL HIGH NORMAL CACHE
+5V
+3.3V +5V
1 PULL LOW DRAMCACHE
+5V +5V 1 R155
R161 R222 R109 10KR3
3 TV_EN 1 2 3,10 ID_DATA 1 2 10KR3
C142 2
SCD1U 10KR3 15KR3 2 ACER TAIPEI TAIWAN R.O.C
INTEL CPU RX9 TC SPKR ISA PULL HIGH & PULL LOW
1 2 3 TC 3 SPKR Title
CLOSE TO PIN [F6] 3 ID_CLK
15KR3 390 ACERNOTE LIGHT
INT. SD DISABLE INT. KBC DISABLE Size Document Number REV
A2 96183 SD
Date: August 7, 1997 Sheet 4 of 23
256K L2 PIPELINE BURST CACHE +5V
+5V
4 U43A
$CPUD[0..63] 1,2 14 VCCP Q 5 CY2 1 U47A
$$$$ $$$$$$$ $$$ $$$$$$$ $$$$ $ 2 D R SCD1U4
CCCCCCCCCCCCCCCCCCCCCCCCCC 1
PPPP PPPPPPP PPP PPPPPPP PPPP P 3 CLK 3
UUUUUUUUUUUUUUUUUUUUUUUUUU
DDDDDDDDDDDDDDDDDDDDDDDDDD 7 GNDC Q 6 2
0123 4567891 111 1111112 2222 2 L 7 TSHCT08
0 123 4567890 1234 5 SOAC74
1
66
6 7686970717273747576798081828384858687889192939495 U44 +5V
+3.3V
I IOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIOIO 1 U47B
45 VCC O IO27 96 $CPUD26 1
0 U43B 4
C209 C208 C210 C211
58
109 VCC 1 2 3 4 5 6 7 8 9 1 011121314151617181920212223242526 IO28 97
98
$CPUD27
$CPUD28 14 VCCP Q 9
4
6
IO_VOLTAGE SCD1U SC2D2U16V5ZY SCD1U SC1KP 122 VCC IO29 99 $CPUD29 12 D R 5
13 VCC IO30 100 $CPUD30
25 VCCQ IO31 101 $CPUD31 C378 11 CLK 7 TSHCT08
38 VCCQ IO32 2 $CPUD32 SCD1U
64 VCCQ IO33 3 $CPUD33 7 GNDC Q 8
C214 C213 C204 C205 C207 C206 C215 C212 77 VCCQ IO34 4 $CPUD34 L
SC1KP SC1KP SCD1U SCD1U SCD1U SC2D2U16V5ZY SCD1U SC1KP 89 VCCQ IO35 5 $CPUD35 SOAC74
102 VCCQ IO36 6 $CPUD36 1
3
R18010KR3 128 VCCQ IO37 7 $CPUD37
1 2 41 VCCQ IO38 8 $CPUD38
IO_VOLTAGE MODE IO39
1,2 $CPUA18 1 2 42
114 NC IO40 9
10
$CPUD39
$CPUD40 U46
+5V
2 $BWE# $BE#0 107 BWE# IO41 11 $CPUD41 1
R184
$BE#1 108 BW1# IO42 12 $CPUD42 2 SH_DOWNHP-IN 16
DUMMY-R3
$BE#2 111 BW2# IO43 15 $CPUD43 3 GND GND 15
$BE#3 112 BW3# IO44 16 $CPUD44 4 +OUTA +OUTB 14
$BE#4 117 BW4# IO45 17 $CPUD45 5 VDD VDD 13 C377
$BE#5 118 BW5# IO46 18 $CPUD46 6 -OUTA -OUTB 12 SCD1U
$BE#6 119 BW6# IO47 19 $CPUD47 7 -INA -INB 11
$BE#7 120 BW7# IO48 20 $CPUD48 8 GND BYPASS 10
$CPUA10 53 BW8# IO49 21 $CPUD49 +INA +INB 9
1,2 $BE#[0..7] $CPUA9 54 A7 IO50 22 $CPUD50 LM4863
$CPUA8 55 A6 IO51 23 $CPUD51
$CPUA7 56 A5 IO52 24 $CPUD52 +5V
$CPUA6 57 A4 IO53 27 $CPUD53 U42
$CPUA5 60 A3 IO54 28 $CPUD54 1
61 A2 IO55 29 2 SH_DOWNHP-IN 16
R179
$CPUA4
62 A1 IO56 30
$CPUD55
3 GND GND 15
1 2
$CPUA3
52 A0 IO57 31
$CPUD56
$CPUD57 4 +OUTA +OUTB 14
1 $W/R# $CPUA11 51 NC IO58 32 $CPUD58 5 VDD VDD 13 C367
DUMMY-R3 $CPUA12 50 A8 IO59 33 $CPUD59 6 -OUTA -OUTB 12 SCD1U
49 A9 IO60 34 7 -INA -INB 11
$CPUA13
$CPUA14 48 A10 IO61 35
$CPUD60
$CPUD61 8 GND BYPASS 10
$CPUA15 47 A11 A A IO62 36 $CPUD62 +INA +INB 9
$CPUA16 44 A12 DAS DSDGOCE CECCCC A GGGGN GNGN GNGNGNGNGNG IO63 37 $CPUD63 LM4863
1,2 $CPUA[3..17] A13 VPCWEE2 3 EE L Z 1 NNNNNDDDDDDDD IO64
# # # # # # # # 2 3 KZ 4 CDDDDQQQQQQQQ
1 11 11 11 11 11 64411 5 419 7 6321 S32K64-7
0
40 50613162124252627153302 3109 60 308 59641 +5V
$
2 $CADV# C
1 $CPUADS# P
2 $CADS# U 1
2 $GWE# A 0 U37B
2 $COE# 1 14
2 $CCS# 7
12 VCCP Q 9
R182 D R
IO_VOLTAGE 1 2 11 CLK
Q 8
10R3
R183
7 GNDCL
3 $PCIRST# 1 2 1 SSHCT74
3
0R3
8 $L2CLK
3 $ZZ R188 +3.3V
2 $MKR# 1 2
DUMMY-R3
1 1 U11B
RX12 4 4
0R3
5 6
2
U45
RX13 1 A14 VCC 28 +3.3V 7 SSLVT125
$CPUA18 1 2 26 A13 D7 19 $TAG7
$CPUA5 10 A0 D6 18 $TAG6
DUMMY-R3 $CPUA6 9 A1 D5 17 $TAG5 C364 C368
$CPUA7 8 A2 D4 16 $TAG4 SC1KP SCD1U
$CPUA8 7 A3 D3 15 $TAG3
$CPUA9 6 A4 D2 13 $TAG2
$CPUA10 5 A5 D1 12 $TAG1
$CPUA11 4 A6 D0 11 $TAG0
$CPUA12 3 A7 $TAG[0..7] 2
$CPUA17 2 A12
$CPUA13 25 A8 CS1* 2220
$CPUA14 24 A9 OE*
$CPUA16 23 A11 WE* 27 $TWE# 2
$CPUA15 21 A10 GND 14 AVAILABLE TTL GATE
S32K8-15
ACER TAIPEI TAIWAN R.O.C
CACHE RAM & TAG RAM
Title
390 ACERNOTE LIGHT
Size Document Number REV
A3 96183 SD
Date: August 21, 1997 Sheet 5 of 23
+3.3V
C392 C394 C397 C398 C391 C390 C399 C393 C396 C395
SC4D7U16V6ZY SCD1U SCD1U SCD1U SC4D7U16V6ZY SC4D7U16V6ZY SCD1U SCD1U SCD1U SCD1U
CN26
145
1 2
$MD0 3 4 $MD32
$MD1 5 6 $MD33
$MD2 7 8 $MD34
2 $CAS#[0..7] $MCAS#[0..7] 7 $MD3 9 10 $MD35
11 12
$MD4 13 14 $MD36
$MD5 15 16 $MD37
$MD6 17 18 $MD38
RP39 $MD7 19 20 $MD39
$CAS#01 8 $MCAS#0 21 22
$CAS#12 7 $MCAS#1 $MCAS#0 23 24 $MCAS#4
$CAS#23 6 $MCAS#2 $MCAS#1 25 26 $MCAS#5
$CAS#34 5 $MCAS#3 27 28
$MAA0 29 30 $MA3
SRN10 $MAA1 31 32 $MA4
RP37 $MA2 33 34 $MA5
$CAS#41 8 $MCAS#4 35 36
$CAS#52 7 $MCAS#5 $MD8 37 38 $MD40
$CAS#63 6 $MCAS#6 $MD9 39 40 $MD41
$CAS#74 5 $MCAS#7 $MD10 41 42 $MD42
$MD11 43 44 $MD43
SRN10 45 46
$MD12 47 48 $MD44
$MD13 49 50 $MD45
$MD14 51 52 $MD46
$MD15 53 54 $MD47
55 56
57 58
RP40 59 60
2 $A12 1 8 $MA12
2 $A13 2 7 $MA13
2 $AA0 3 6 $MAA0 7
2 $AA1 4 5 $MAA1 7 8 $SDRAM_CLK0 61 62 $CLKEN02 EDO_A12 7
63 64
SRN10 2 $MSRAS#0 65 66 $MSCAS#02 RX17
2 $MWE# 67 68 $CLKEN12
2 $MRAS#0 69 70 1 0R3 2 $MA12
2 $A[2..11] 2 $MRAS#1 71 72 1 2 $MA13
$MA[2..11] 7 73 74 $SDRAM_CLK18 RX16
1 75 76 0R3
R336 77 78
RP38 DUMMY-R3 79 80 EDO_A13 7
$A2 1 8 $MA2 81 82 1
$A3 2 7 $MA3 $MD16 83 84 $MD48 R337
$A4 3 6 $MA4 2 $MD17 85 86 $MD49 DUMMY-R3
$A5 4 5 $MA5 $MD18 87 88 $MD50
$MD19 89 90 $MD51
SRN10 91 92 2
RP36 $MD20 93 94 $MD52
$A6 1 8 $MA6 $MD21 95 96 $MD53
$A7 2 7 $MA7 $MD22 97 98 $MD54
$A8 3 6 $MA8 $MD23 99 100 $MD55
$A9 4 5 $MA9 101 102 SDRAM_A12 7
$MA6 103 104 $MA7
SRN10 $MA8 105 106 $MA11 RX15
R187 107 108
$A10 1 2 $MA10 $MA9 109 110 1 0R3 2 $MA12
$MA10 111 112 1 2 $MA13
10R3 113 114 RX14
R186 $MCAS#2 115 116 $MCAS#6 0R3
$A11 1 2 $MA11 $MCAS#3 117 118 $MCAS#7
119 120 SDRAM_A13 7
10R3 7 $DIM2_MD24 121 122 $MD56
7 $DIM2_MD25 123 124 $MD57
7 $DIM2_MD26 125 126 $MD58
7 $DIM2_MD27 127 128 $MD59
129 130
$MD28 131 132 $MD60
$MD29 133 134 $MD61
$MD30 135 136 $MD62
$MD31 137 138 $MD63
139 140
7 $SMBDATA_DIM1 141 142 $SMBCLK_DIM1 7
143 144
146
SDIMM144
C380 C388 C385 C386 C381 C382 C387 C384 C389 C383
SC4D7U16V6ZY SCD1U SCD1U SCD1U SC4D7U16V6ZY SC4D7U16V6ZY SCD1U SCD1U SCD1U SCD1U
CN25
145
1 2
$MD0 3 4 $MD32
$MD1 5 6 $MD33
$MD2 7 8 $MD34
$MCAS#[0..7] 6 $MD3 9 10 $MD35
11 12
$MD4 13 14 $MD36
$MD5 15 16 $MD37
$MD6 17 18 $MD38
$MD7 19 20 $MD39
$MA[2..11] 6 21 22
$MCAS#0 23 24 $MCAS#4
$MCAS#1 25 26 $MCAS#5
27 28
6 $MAA0 29 30 $MA3
6 $MAA1 31 32 $MA4
+5V $MA2 33 34 $MA5
35 36
$MD8 37 38 $MD40
$MD9 39 40 $MD41
$MD10 41 42 $MD42
$MD11 43 44 $MD43
C315 45 46
1 U10A SCD1U $MD12 47 48 $MD44
4 $MD13 49 50 $MD45
$SMBDATA 1 2 $SMBDATA_DIM1 6 $MD14 51 52 $MD46
$MD15 53 54 $MD47
55 56
57 58
7 1
3 SO4066 59 60
3 SDRAM
8 $SDRAM_CLK2 61 62 $CLKEN02
1 U10B 63 64
4 2 $MSRAS#1 65 66 $MSCAS#12
11 10 $SMBDATA_DIM2 2 $MWE# 67 68 $CLKEN12
2 $MRAS#2 69 70 EDO_A126
2 $MRAS#3 71 72 EDO_A136
73 74 $SDRAM_CLK38
7 1
2 SO4066 1 75 76
R331 77 78
DUMMY-R3 79 80
81 82 1
$MD16 83 84 $MD48 R332
1 U10C 2 $MD17 85 86 $MD49 DUMMY-R3
4 $MD18 87 88 $MD50
1,3,8,12 $SMBCLK 4 3 $SMBCLK_DIM1 6 $MD19 89 90 $MD51
91 92 2
$MD20 93 94 $MD52
$MD21 95 96 $MD53
7 5 SO4066 $MD22 97 98 $MD54
$MD23 99 100 $MD55
101 102
$MA6 103 104 $MA7
$MA8 105 106 $MA11
1 U10D 107 108
4 $MA9 109 110 SDRAM_A126
+5V 8 9 $SMBCLK_DIM2 $MA10 111 112 SDRAM_A136
113 114
$MCAS#2 115 116 $MCAS#6
1 U38D $MCAS#3 117 118 $MCAS#7
4 1
3 7 6 SO4066 RNZ1 119 120
6 $DIM2_MD24 1 8 $MD24 121 122 $MD56
12 11 6 $DIM2_MD25 2 7 $MD25 123 124 $MD57
6 $DIM2_MD26 3 6 $MD26 125 126 $MD58
6 $DIM2_MD27 4 5 $MD27 127 128 $MD59
7 SSAHCT1251 129 130
R98 SRN33 $MD28 131 132 $MD60
100KR3 $MD29 133 134 $MD61
$MD30 135 136 $MD62
2 $MD31 137 138 $MD63
139 140
$SMBDATA_DIM2 141 142 $SMBCLK_DIM2
143 144
146
SDIMM144
CLKDWN
+5V
+5V
+3.3V
+3.3V
1 1
C334 CX16 R91 R245
SCD1U SC1KP 100KR3 1 1 U11D 47KR3
4 3
2 2 RX39
+5V 4 U37A 1,13 CLK_SEL1 12 11 1 2 SEL1
CLK_SEL1 CLK_SEL0 FREQ. R124
14 VCCP Q 5 1 2 CLK7M 13 0R3
0 0 60.0MHZ 2 D R 7 SSLVT125
33R3 1
0 1 66.6MHZ KBD14M 3 CLK RX32
Q 6 DUMMY-C3
7 GNDCL
SSHCT74 2
1
ACER TAIPEI TAIWAN R.O.C
+5V CY2272 CLOCK GENERATOR
Title
390 ACERNOTE LIGHT
Size Document Number REV
A3 96183 SD
Date: August 7, 1997 Sheet 8 of 23
RP6
$VAA8 1 8 +3.3V
$VAA7 2 7
$VAA6 3 6
$VAA5 4 5
SRN33 C62 C49
RP9 SCD1U SCD1U
$VAA4 1 8
$VAA3 2 7 U4
$VAA2 3 6 $$ $$$ $$$$ $$$$ $$$ $ $$$$ $$$ $$$ $$$$$ 1 VCC VSS 44
$VAA1 4 5 VVVVVVVVVVVVVVVV VVVVVVVVVVVVVVVV $VMAD0 2 DQ0 DQ15 43 $VMAD15
MM MMM MMMM MMMM MMM M MMMM MMM MMM MMMMM $VMAD1 3 DQ1 DQ14 42 $VMAD14
SRN33 AAAAAAAAAAAAAAAA BBBBBBBBBBBBBBBB $VMAD2 4 DQ2 DQ13 41 $VMAD13
R88 DDDDDDDDDDDDDDDD DDDDDDDDDDDDDDDD $VMAD3 5 DQ3 DQ12 40 $VMAD12
$VAA0 1 2 01 234 5678 9111 111 0 1234 567 891 11111 6 VCC VSS 39
012 345 0 12345 $VMAD4 7 DQ4 DQ11 38 $VMAD11
33R3 DCBCABAB CD DABC DBACABCA BCA BDCA B L L L $VMAD5 8 DQ5 DQ10 37 $VMAD10
1 121 2111 11 1 1 1 1 A BACB ACB ACBA 1 111 1111 111 1111 1L 111 U24 $VMAD6 9 36 $VMAD9
8 908 0998 76 0 0009 9898 787 6765 5 675 6545 434 3223 29 012 $VMAD7 10 DQ6 DQ9 35 $VMAD8
M9 11 DQ7 DQ8 34
AAAAAAAAAA MM MMM MMMMM M MMM MM MM MMM MMM MMM MMM MMG GGG GND M10 12 N.C N.C 33
AAAAAAAAAA AAAAAAAAAAAAAAAA BB BBB BBB BBB BBB BBNNNN GND N.C N.C
R48 01 234 56 789 01 234 56789 1 111 11 0 1 2 3 4 5 6 7 8 9 1 1 1 1 1 1 DDDD M11 13 32
$AD22 1 2 G2 / / / / / / / / / / / / / / / / / / / / 0 123 45 / / / / / / / / / / 0 123 45 GND M12 14 N.C N.C 31 $VCASAL#
IDSEL CCCCCCCCCC T T CCCCCCRR/ / / / / / RRRRRRRRRR/ / / / / / GND N.C LCAS
RNZ2 SRN33 FFFFFFFFFF MM F F F F F F MM R R R R R R MM MMM MMM MMR R R R R R $VWEA# 15 WE UCAS 30 $VCASAH#
33R3 K2 GG GGG GG GGG 0 1 GGG GGGD D M MMM MM A A A A A A A A A A M MMM MM $VRAS#0 16 29
2,3,11 $FRAME# FRAME 01 234 56 789 1 1 1 1 1 1 0 1 DDDDDD 0 1 2 3 4 5 6 7 8 9 AAAAAA RAS OE
2,3,11 $IRDY# 1 8 K1 IRDY 012 345 2 345 67 1 111 11 MC0 J18 $VMCD0 17 N.C A8 28 $VAA8
2 7 K4 0 123 45 J17 $VMCD1 $VAA0 18 27 $VAA7
2,3,11 $TRDY# 3 6 L4 TRDY MC1 H19 $VMCD2 $VAA1 19 A0 A7 26 $VAA6
2,3,11 $DEVSEL# 4 5 L1 DEVSEL MC2 G20 $VMCD3 $VAA2 20 A1 A6 25 $VAA5
2,3,11 $STOP# M1 STOP MC3 H18 $VMCD4 $VAA3 21 A2 A5 24 $VAA4
2,3,11 $PAR PAR MC4 G19 $VMCD5 22 A3 A4 23
2,3,11 $CBE#[0..3] $CBE#0 P3 MC5 F20 $VMCD6 VCC VSS
$CBE#1 M2 C/BE0 MC6 G18 $VMCD7 S256K16-50
$CBE#2 K3 C/BE1 MC7 F19 $VMCD8 +3.3V
+3.3V $CBE#3 F1 C/BE2 MC8 E20 $VMCD9
C/BE3 MC9 F18 $VMCD10
C1 MC10 D20 $VMCD11
3 $PCIRST# D2 RESET MC11 E19 $VMCD12
8 $VGACLK 1 RY1 2 C3 BCLK MC12 F17 $VMCD13 C33 C251
C109 C103 C92 8 $VGA14M RCLK MC13 E18 $VMCD14 SCD1U SCD1U
SC1KP SCD1U SCD1U 33R3 E4 MC14 D19 $VMCD15
3 $STANDBY# STNDBY MC15 U16
3 $SERR# L3 SERR MD0/CA0 R20 $VMDD0 1 VCC VSS 44
2,11 $PERR# L2 PERR MD1/CA1 P19 $VMDD1 $VMBD0 2 DQ0 DQ15 43 $VMBD15
BVCC BYPASS CAP MD2/CA2 N18 $VMDD2 $VMBD1 3 DQ1 DQ14 42 $VMBD14
MD3/CA3 P20 $VMDD3 $VMBD2 4 DQ2 DQ13 41 $VMBD13
2,3,11 $AD[0..31] MD4/CA4 N19 $VMDD4 $VMBD3 5 DQ3 DQ12 40 $VMBD12
$AD0 U2 AD0 MD5/CA5 M17 $VMDD5 6 VCC VSS 39
$AD1 T3 AD1 MD6/CA6 M18 $VMDD6 $VMBD4 7 DQ4 DQ11 38 $VMBD11
$AD2 R4 AD2 MD7/CA7 N20 $VMDD7 $VMBD5 8 DQ5 DQ10 37 $VMBD10
$AD3 T2 AD3 MD8/CA8 M19 $VMDD8 $VMBD6 9 DQ6 DQ9 36 $VMBD9
+3.3V $AD4 U1 AD4 MD9 M20 $VMDD9 $VMBD7 10 DQ7 DQ8 35 $VMBD8
+3.3V $AD5 R3 AD5 MD10 L18 $VMDD10 11 N.C N.C 34
$AD6 T1 AD6 MD11/RMA16 L19 $VMDD11 12 N.C N.C 33
$AD7 R2 AD7 MD12/RMA17 L20 $VMDD12 13 N.C N.C 32
C60 C87 $AD8 R1 AD8 MD13 L17 $VMDD13 14 N.C LCAS 31 $VCASBL#
SC1KP SCD1U C108 C113 $AD9 P2 AD9 MD14 K17 $VMDD14 $VWEB# 15 WE UCAS 30 $VCASBH#
SCD1U SC1KP $AD10 N3 AD10 MD15 K20 $VMDD15 $VRAS#0 16 RAS OE 29
$AD11 P1 AD11 R74 17 N.C A8 28 $VAA8
CVCC BYPASS CAP VVCC BYPASS CAP $AD12 N2 AD12 RAS0 C11 1 2 $VRAS#0 $VAA0 18 A0 A7 27 $VAA7
$AD13 M4 AD13 RAS1/CRAS K18 1 33R3 2 $VAA1 19 A1 A6 26 $VAA6
$AD14 M3 AD14 R79 33R3 1 RP48 SRN33 $VAA2 20 A2 A5 25 $VAA5
$AD15 N1 AD15 DQMAH A11 8 $VCASAH# $VAA3 21 A3 A4 24 $VAA4
$AD16 J1 AD16 DQMAL D11 2 7 $VCASAL# 22 VCC VSS 23
$AD17 J2 AD17 DQMBH B17 3 6 $VCASBH#
+3.3V $AD18 H1 AD18 DQMBL C16 4 5 $VCASBL# S256K16-50
$AD19 J3 AD19 DQMCH J19 1 8 $VCASCH# +3.3V
$AD20 J4 AD20 DQMCL H20 2 7 $VCASCL#
$AD21 H2 AD21 DQMDH R19 3 6 $VCASDH#
1 $AD22 G1 AD22 DQMDL P18 4 5 $VCASDL#
C90 C102 C112 C89 $AD23 H3 AD23 RP10 SRN33
2 SCD1U SCD1U SCD1U SC1KP $AD24 G3 B11 1 8 $VWEA# C309 C289
$AD25 F2 AD24 SWE A18 2 7 $VWEB# SCD1U SCD1U
C64 $AD26 E1 AD25 SCAS J20 3 6 $VWEC#
ST10U16VBM MVCC BYPASS CAP $AD27 F3 AD26 AA10 T20 4 5 $VWED# U26
$AD28 D1 AD27 SCKE 1 44
AD28 RP47 SRN33 VCC VSS
$AD29 E2 AD29 NC/COE K19 C53 $VMCD0 2 DQ0 DQ15 43 $VMCD15
$AD30 F4 AD30 $VMCD1 3 DQ1 DQ14 42 $VMCD14
$AD31 E3 AD31 GP0/ACTI V1 R75 2 +5V $VMCD2 4 DQ2 DQ13 41 $VMCD13
+3.3V GP1/C32KHZ T4 1 $32KO 3 1 +3.3V SCD1U $VMCD3 5 DQ3 DQ12 40 $VMCD12
0R3 6 VCC VSS 39
D4 RSRVD DDDA V3 DDC_DATA 10 R46 U48 $VMCD4 7 DQ4 DQ11 38 $VMCD11
Y20 RSRVD DDCK U4 DDC_CLK 10 47KR3 1 8 $LCDPWR 10 $VMCD5 8 DQ5 DQ10 37 $VMCD10
1 D17 RSRVD 2 7 $VMCD6 9 DQ6 DQ9 36 $VMCD9
C91 C111 C115 C76 D8 U6 1 R61 2 0R3 2 3 6 $VMCD7 10 35 $VMCD8
SC1KP SCD1U SCD1U 2 ST10U16VBM RP4 SRN10K RSRVD EBKL Y5 4 5 11 DQ7 DQ8 34
1 8 A1 SHCLK V6 $SHFCLK 10 12 N.C N.C 33
2 7 B2 TMS M Y4 $MOD 10 SI4435DY 13 N.C N.C 32
IVCC BYPASS CAP 3 6 B1 TCLK LP W5 $LP 10 3 C55 14 N.C N.C 31 $VCASCL#
4 5 C2 TDI FLM $FLM 10 1 Q4 SC1U10V5KX $VWEC# 15 N.C LCAS 30 $VCASCH#
1 2 D3 TDO V5 2N7002 $VRAS#0 16 WE UCAS 29
+3.3V TRST EVDD W4 2 17 RAS OE 28 $VAA8
R47 10KR3 H4 EVEE ENAVEE 3,10 $VAA0 18 N.C A8 27 $VAA7
N4 BVCC W2 1 R52 2 +5V $VAA1 19 A0 A7 26 $VAA6
+3.3V BVCC RSET $VAA2 20 A1 A6 25 $VAA5
+3.3V W1 Y3 A2 A5
L6 CVCC RED V4 $RED 10 560R3 U2C
$VAA3 21
22 A3 A4 24
23
$VAA4
GREEN $GREEN 10 1 1 VCC VSS
1 2 U5 AVCC BLUE W3 $BLUE 10 CRT_GND 4 0
FB-1 R201 +3.3V S256K16-50
1 CX21 U8 U3 9 8 1 2
L4 C280 C78 DVCC HSYNC/CSYNC V2 HSYNC 10
2 ST47U10VDM SCD1U SC1KP U13 VSYNC 33R3
FB-1 VVCC
1 2 VREF V16 $ZV_VREF 11 7 SSABT125
CX18 L12 N17 MVCC HREF W17 $ZV_HREF 11 1 1 U2D C104 C125
+3.3V 1 2 H17 MVCC VCLK Y18 $ZV_HCLK 11 4 3 SCD1U SCD1U
D13 MVCC VRDY U16 R207
SC1KP FB-1 C97 C114 V17 12 11 1 2 U6
CRT_GND SC1KP SCD1U W12 IVCC PCLK VSYNC 10 1 44
+3.3V D9 C20 33R3 $VMDD0 2 VCC VSS 43 $VMDD15
L7 IVCC SGCLK E17 1 2 7 SSABT125 $VMDD1 3 DQ0 DQ15 42 $VMDD14
1 2 D5 SGCKI $VMDD2 4 DQ1 DQ14 41 $VMDD13
C4 PVCC B5 R84 0R3 5 DQ2 DQ13 40
CX22 PVCC MPRI $VMDD3 DQ3 DQ12 $VMDD12
FB-1 1 SC1KP B4 PGND MGNT A4 6 VCC VSS 39
L8 C279 C88 A3 PGND MREQ C6 $VMDD4 7 DQ4 DQ11 38 $VMDD11
FB-1 2 ST47U10VDM SCD1U $VMDD5 8 DQ5 DQ10 37 $VMDD10
1 2 B3 SVCC VP0 R18 $ZV_Y0 $VMDD6 9 DQ6 DQ9 36 $VMDD9
CX17
A2 VP1 U20 $ZV_Y1 $VMDD7 10 DQ7 DQ8 35 $VMDD8
SGND VP2 T19 $ZV_Y2 11 N.C N.C 34
SC1KP G4 VP3 R17T18
$ZV_Y3
$ZV_Y4
12
13 N.C N.C 33
32
P_GND P4 GND VP4 U19 $ZV_Y5 14 N.C N.C 31 $VCASDL#
+3.3V S_GND U7 GND VP5 V20 $ZV_Y6 $VWED# 15 N.C LCAS 30 $VCASDH#
L9 U14 GND VP6 T17 $ZV_Y7 $VRAS#0 16 WE UCAS 29
1 2 P17 GND VP7 J9 17 RAS OE 28 $VAA8
G17 GND GND J10 $ZV_Y[0..7] 11 $VAA0 18 N.C A8 27 $VAA7
FB-1 1 D14 GND GND J11 $VAA1 19 A0 A7 26 $VAA6
C281 C74 CX19 D7 GND RA VVVVVV GND J12 $VAA2 20 A1 A6 25 $VAA5
L11 GND GG P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P V V GGG
2 ST47U10VDM SCD1U SC1KP N N N N N P P P P P P P P P P 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 1 1 1 1 1 1 P P N N N GND A2 A5
1
FB-1
2 C C C D D 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 5 4 3 2 1 0 9 8 D D D GND K12 $VAA3 21
22 A3 A4 24
23
$VAA4
CX20 VCC VSS
D 65555-1
6 C
5A1Y1Y2 W
6V7Y6 W
7V8Y7W8 U
9V9Y8 W
9Y9 V
1W1Y1U1 U
1Y1W1V1 Y
1Y1V1 U
1W1Y1V1 W
1Y1 V1W1Y 1 V
1Y1W
1 1U W1Y1 V
1U1W1W2 V
1 1U 9K 1K 1K S256K16-50
2 0000 1111 232 2343 45 456 5765 89 8790 98 01
SC1KP $$$$ $$$ $$$ $$$ $$$ $$$$ $$$$
S_GND PPPPPPPPPPPPPPPPPPPPPPPP $$ $$$$$ $
0123 456 789 111 111 1111 2222 ZZZZZZZZ ACER TAIPEI TAIWAN R.O.C
012 345 6789 0123 VVVVVVVV VGA CONTROLLER CHIP 65555 & VRAM
CRT_GND $P[0..23] 10_ _ _ _ _ _ _ _ Title
UUUUUUUU
VVVVVVVV 390 ACERNOTE LIGHT
76 54321 0
$ZV_UV[0..7] 11 Size Document Number REV
A2 96183 SD
Date: August 7, 1997 Sheet 9 of 23
+5V DOCK_HSYNC 23
1 $DOCK_B 23
R199
15KR3 DOCK_VSYNC 23
2 DOCK_VSW3 23
1R2062
9 DDC_CLK DOCK_DDC_CLK23
100R3 C26
SC47P 9 $P[0..23]
R203
4 VSW3 1 2
5 CN9
1KR3 C234 1
SC47P
R200
9 VSYNC VSYNC 1 2 CN4 $R0 1 2 $DISPLAY 4
16 $R1 3 4
10R3 C235 $R3 5 6 $LCD_HSYNC
SC47P 5 U21 7 8 CX23
L2 15 1 20 RP42 $R6 9 10 $DOTCLK SC1KP
9 $BLUE $BLUE 1 2 10 $P0 2 19 1 8 $B0 11 12
NL322522T-2R2 4 $P1 3 18 2 7 $B1 $G0 13 14 $LCD_VSYNC
1 R19 2 C247 14 $P3 4 17 3 6 $B3 15 16
75R3 SC47P 9 $P6 5 16 4 5 $B6 $G1 17 18 $R2
CRT_GND R202 3 $P2 6 15 19 20 $R4
9 HSYNC HSYNC 1 2 CRT_GND 13 $P4 7 14 SRN47 $G3 21 22 $R5
8 $P5 8 13 RP45 23 24 $R7
10R3 C236 2 $P7 9 12 1 8 $B2 $G6 25 26
L3 SC47P 12 10 11 2 7 $B4 27 28 $G2
NL322522T-2R2 7 3 6 $B5 $B0 29 30 $G4
9 $GREEN $GREEN 1 2 1
11
IPEC330-470FS 4 5 $B7
$B1
31
33
32
34
$G5
$G7
1 R28 2 C261 6 SRN47 35 36
SC47P U25 RP46 $B3 37 38 $B2
CRT_GND 75R3 R18 17 1 20 1 8 $G0 $B6 39 40 $B4
9 DDC_DATA 1 100R32
CRT_GND $P8 2 19 2 7 $G1 41 42 $B5
R8 VIDEO-15-4-D $P9 3 18 3 6 $G3 LCDVEE 43 44 $B7
+5V 1 2 C245 CRT_GND $P11 4 17 4 5 $G6 45 46
L1 SC47P $P14 5 16 47 48 $TFT_DE
15KR3 NL322522T-2R2 CRT CONNECTOR $P10 6 15 SRN47 9 $LCDPWR 49 50 $LCDPWR
9 $RED $RED 1 2
C237
$P12
$P13
7
8
14
13 1
RP43
8 $G2
1 R9 2 SC47P $P15 9 12 2 7 $G4
75R3 R3 10 11 3 6 $G5 5
2 AMP-CONN50A
CRT_GND 4 5 $G7
4 VSW1 CRT_GND1 1KR32 DOCK_VSW1 23 IPEC330-470FS
C218 SRN47
$DOCK_R 23 U30 RP41 C262 C246 C257
SC47P 1 20 1 8 $R0 SC2D2U16V5ZY SCD1U SC1KP
DOCK_DDC_DATA23 $P16 2 19 2 7 $R1
$P17 3 18 3 6 $R3
$DOCK_G 23 $P19 4 17 4 5 $R6
$P22 5 16 UZ1
$P18 6 15 SRN47 3 CCFT 1
OE#
$P20 7 14 RP44 VCC 5 +5V
$P21 8 13 1 8 $R2 A 2
$P23 9 12 2 7 $R4 Y 4
10 11 3 6 $R5 3
GND CZ1
4 5 $R7 1 SCD1U
IPEC330-470FS NC7SZ125
SRN47
RZ7 RZ8
510R32 2 33R3
+5V 1
3,4 ID_DATA
R224 CX24 1 CN8
100R32 SC1KP 6 1
9 ENAVEE 1 1
7 2 1 R223 2
R2702 +5V 8 3 100R3
$ $ $ V H 3 ID_CLK 1 9 4 LCDVEE
R G B S S R220 100R3 DCBATOUT 10 5
E R L Y Y 10R3 22R3
D E U N D7 N 9 $FLM 1 R702 1 2 $LCD_VSYNC 1HRS-CONN10B
ED9 E C C 9 $LP 1 R60 2 1 R217
2 $LCD_HSYNC C243 2
N BAV99LT1 1 2 10R3 22R3 1 2 $TFT_DE SC1U25V5MY
D6 3BAV99LT1 D8 3 9 $MOD R234 R65 C248
ESD DISCHARGE 10R3 22R3
BAV99LT1 BAV99LT1 SC2D2U16V5ZY
3 3 3 C242 +5V
1 2 1 2 D5 SC10U35V0ZY
BAV99LT1 C93 C69 C105 CZ2
SC33P SC33P SC33P
1 2 1 2 1 2 +5V SCD1U
UZ2
3 CONTRAST 1 OE#
5
2 A VCC
R213 RX42 L15 4
9 $SHFCLK 1 2 1 2 1 2 $DOTCLK 3 GND Y
1
33R3 33R3 BK1608LL121 NC7SZ125RZ10
100R3
C258
SC39P RZ9 2
+5V 1 2
5K1R3D
ACER TAIPEI TAIWAN R.O.C
CRT & LCD CONN
Title
390 ACERNOTE LIGHT
Size Document Number REV
A3 96183 SD
Date: August 21, 1997 Sheet 10 of 23
R92 R144
12 ACCLK 1 33R32 1 33R32 BCCLK 12
12 ACCBE#[0..3] BCCBE#[0..3] 12
12 ACAD[0..31] A AAA BBBB BCAD[0..31] 12
AAAAAAA AAA AAAA AAA AAAAAAA AAAAAAA A CCCC CCCC B BBBBB BBBBB BBBBBBB BBB BBBBBBB BBB B
CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC CCCC CCCC CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC
AAAAAAA AAA AAAA AAA AAAAAAA AAAAAAA A B BBB BBBB A AAAAA AAAAA AAAAAAA AAA AAAAAAA AAA A
+3.3V
DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD E EEE EEEE DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD
0 1 2 3 4 5 6 7 8 9 1 1 11 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 # ### #### 3 32222 22222 2111111 111 1987654 321 0
0 1 23 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 0 123 3210 1 09876 54321 0987654 321 0
G A BD BD CB AC AB AC AB CC BE DC DE EG GF GF HG H
2H3G
1H1H2 J3 J4 J1 K
3L1L
2L3M1L4M3M2M4U2V1T4V2V3W2W3W4V4U5Y6V7W7Y7W8 K 1N1T 3Y2 T
1 1
7 121 4192 0 B
7C8B8A8D9111112121313141415151819201718201918191718191920182019 U36 C149 C163 C162 C157
SCD1U SCD1U SCD1U SCD1U
AA
_ _ A
_ A
_ A
_ A
_ A
_ A
_ A
_ A
_ A
_ A
_ A
_ A
_ A
_ A
_ A
_ A
_ A
_ A
_ A
_ A
_ A
_ A
_ A
_ A
_ A
_ A
_ A
_ A
_ A
_ A
_ A
_ A
_ A
_ A
_ A
_ B
_ B_
_ B_ B_B B_ B
_ B
_ B
_ B
_ B
_ B
_ B
_ B
_ B
_ B
_ B
_ B
_ B
_ B
_ B
_ B
_ B
_ B
_ B
_ B
_ B
_ B
_ B
_ B
_ B
_ B
_ B
_ B
_ B
_ B
_ B
_
C
AD
D
C
01 D
C
A ADC
23D
C
AAD C
45 D
C
A AD C
AAD
67D
C C
89D
C
AAD
1
01
C
AD
11
C
AD
21
C
AD
31
C
AD
41
C
AD
51
C
AD
61
C
AD
71
C
AD
81
C
AD
92
C
AD
02
C
AD
12
C
AD
22
C
AD
32
C
AD
42
C
AD
52
C
AD
62
C
AD
72
C
AD
82
C
AD
93
C
AD
03
C
A C
1 B
C
/C
EB
C
/C
EB
C
/C
EB
C C
/ C
L
E K
C
C C
L CC
K /B
EB
CC
/C/C
EBEB
C
AC
/C D
E 3
13
AC
D
02
AC
D
92
AC
D
82
AC
D
72
AC
D
62
AC
D
52
AC
D
42
AC
D
32
AC
D
22
AC
D
12
AC
D
01
AC
D
91
AC
D
81
AC
D
71
AC
D
61
AC
D
51
AC
D
41
AC
D
31
AC
D
21
AC
D
11
AC
D AC
D AC
D AC
D AC
D AC
D AC
D
0 9876 543210
AC
D AC
D AC
D A
D VCCP BYPASS CAP
Y5 A_CAUDIO 0
#1#2 #3# 3 2
#### 1 0
12 ACAUDIO P1 A_CBLOCK# B_CAUDIO D10 BCAUDIO12
12 ACBLOCK# R2 A_CDEVSEL# B_CBLOCK#B18 BCBLOCK# 12
12 ACDEVSEL# U1 A_CFRAME# B_CDEVSEL#A18 BCDEVSEL# 12
12 ACFRAME# P3 A_CGNT# B_CFRAME#C15 BCFRAME# 12
12 ACGNT# Y4 A_CPAST# B_CGNT# D16 BCGNT# 12
12 ACINT# T2 A_CIRDY# B_CPAST# A10 BCINT# 12
12 ACIRDY# U7 A_CLKRUN# B_CIRDY# A16 BCIRDY# 12
12 ACLKRUN# N3 A_CPAR B_CLKRUN#B9 BCLKRUN# 12
12 ACPAR P2 A_CPERR# B_CPAR A19 BCPAR 12
12 ACPERR# Y1 A_CREQ# B_CPERR#B17 BCPERR# 12
12 ACREQ# W1 A_CRST# B_CREQ# D12 BCREQ# 12
A_SLOT_VCC 12 ACRST# V5 A_CSERR# B_CRST# C13 BCRST# 12
12 ACSERR# R1 A_CSTOP# B_CSERR#B10 BCSERR#12
12 ACSTOP# V6 A_CSTSCHG B_CSTOP# C17 BCSTOP# 12
12 ACSTSCHG P4 A_CTRDY# B_CSTSCHGA9 BCSTSCHG 12
12 ACTRDY# B_CTRDY# C16 BCTRDY# 12
C130 C129 12 ARSVD/D2 V8 A_RSVD/D2 B_CCD1# C9H20 BCCD1# 12
SCD1U SCD1U 12 ARSVD/A18 N2 A_RSVD/A18 B_CCD2# A11 BCCD2# 12
12 ARSVD/D14 J2 A_RSVD/D14 B_CVS1 B14 1 R137
B_CVS2 2 B_VS1 12
B_VS2 12,18 B_SLOT_VCC
12 ACCD1# G3 A_CCD1# 1KR3
12 ACCD2# W6 A_CCD2# A7
B_RSVD A20 BRSVD/D2 12
12 A_VS1 1 R93 2 Y3U3 A_CVS1 B_RSVD E20 BRSVD/A18 12
12,18 A_VS2
1KR3 W5 A_CVS2
B_RSVD BRSVD/D14 12
RP13SRN33 A_SLOT_VCC VCCB C10 B_SLOT_VCC C181 C182
17 $ZV_DATA 1 8 R3 VCCA B16 SCD1U SCD1U
17 $ZV_LRCLK 2 7 K2 VCCA
VCCA
VCCB F18
VCCB
3 6
17 $ZV_SCLK 4 5 E2
E3 ZV SDATA
VCC D6
$ZV_UV71 8 RP12SRN33 D3 ZV LRCLK
VCC D11
+3.3V
$ZV_UV62 7 C2 ZV MCLK
VCC D15 +3.3V
$ZV_UV53 6 D2 ZV SCLK
VCC F4
$ZV_UV44 5 C3 ZV UV7
ZV UV6 VCC F17
9 $ZV_UV[0..7] RP17 B1 ZV VCC K4
$ZV_UV31 8 SRN33 B2 ZV UV5
UV4 VCC L17
$ZV_UV22 7 A2 ZV UV3 VCC R4 C154 C158 C148 C165
$ZV_UV13 6 C4 ZV UV2 VCC R17 SCD1U SCD1U SCD1U SCD1U
$ZV_UV04 5 B3 ZV UV1 VCC U6
D5 ZV UV0 VCC U10
A3 ZV Y7 VCC U15 +3.3V
$ZV_Y7 1 8 B4 ZV Y6
$ZV_Y6 2 7 C5 ZV Y5 GND H4
$ZV_Y5 3 6 B5 ZV Y4 GND A1
$ZV_Y4 4 5 C6 ZV Y3 GND D4
9 $ZV_Y[0..7] RP19 D7 ZV Y2 GND D8 C167 C184 C183 C168
$ZV_Y3 1 8 SRN33 A5 ZV Y1 GND D13 SCD1U SCD1U SCD1U SCD1U
$ZV_Y2 2 7 B6 ZV Y0 GND D17
$ZV_Y1 3 6 C7 ZV VSYNC GND U17
$ZV_Y0 4 5 A6 ZV HREF GND U13 +3.3V
RP20SRN33 E1 ZV PCLK GND U8
9 $ZV_VREF 1 8 C1 ZV RSVD GND U4
9 $ZV_HREF 2 7 E4 ZV RSVD GND N17
9 $ZV_HCLK 3 6 F1 ZV RSVD GND N4
4 5 F2 GND H17
P P C166 C156 C186 C185
G4 ZV RSVD C C SCD1U SCD1U SCD1U SCD1U
RP11SRN33 F3 ZV RSVD
ZV RSVD L
E L
E L
O G
N R
E
D1 S S D
A D
A C
K T
/ Q
/
+3.3V +3.3V
A4 VCCZ DF C P U 12/G# IRIR IRIRIRIRIRIRIR
VCCZ /C/C /C/C IDEV R IR P P S S T L
K K
R S
P I_ /G
R /G P
A Q Q QQ QQ QQ CD L
C316 C318
SCD1U SCD1U D ADA ADAAD A AD AAD AADADADADADADADADADADADADADADADADADADADADADAD B EBEB EBE P
C S S
E A
M G
N D P E
R R
E R
S E
R T
O R
D R
U O
U E
N O IOP
P IOPIO V
C V
CVCV
C S
T Q
S M
U UM
M UMUMUMUMUMU V C L O TA
A T 1 1
01 D23D 45 D 67D 891 0111213141516171819202122232425262728293031 0 #1#2 #3# L
K L # # # # R# # # # # # # # # T 0 1 2 PPPP # R0 X
E L E T Y A R Q T R P Y N T D U C C CC A E X 1X2X3X4X5X6X7 C I KA
C NCH 2 2
C147 C187 C155
SC1KP SC1KP SC1KP
Y1 Y1
W1 V1W1Y1 U1 W1 V1 Y1
W1 U1V1W1Y1V1R1P1R2R1P2P1N1N1M1M2M1L1L2L1K1K 1 Y1W2 T1 J
M 1 N V T J2 T Y U K J1 U T U J1Y1Y1 Y1 V1 W1V 1V2W2 P V
K1 W Y U V W Y W U Y V U V W PCI1250 C177 C141
1
445 456 4667867 8988790 90898 90980 98 790 7 7 2 2 1 1 2 1 1 1 1 2 1
0090808 799 70 8013 119 50 08 3 3 1 1 8 9 9 9 9 1 1 1 1
0 12 0 222 1 1 1
ST10U16VBMST10U16VBM
$ $ $ $ $ $ $ $ $ $ $ $ $$ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $
$
S
VCC BYPASS CAP
$LATCH 12
$CLOCK $DATA 12
$CLOCK 12
+3.3V AAAAAAA AAA AAAA AAA AAAAAAA AAAAAAA A CCCC U +3.3V
DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD B BBB S
0 1 2 3 4 5 6 7 8 9 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 E EEE P +3.3V C150
R163 0 1 23 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 # # # # # SCD1U
$CLOCK1 2 2,3,9 $AD[0..31] 0 123 1 R2592 R140
2,3,9 $CBE#[0..3] 0R3 $SUSP# 1 2 $SUSPEND#3
10KR3 8 $CARDCLK IRQ15 3,4
$AD21 1 R1652 1 R1432 0R3
2,3,9 $DEVSEL# 33R3 0R3 1 IRQ11 3,4
2,3,9 $FRAME# R164 IRQ10 3,4,21
2 $GNT#3 DUMMY-R3 IRQ9 3,4
2,3,9 $IRDY# IRQ5 3,4,21
2,3,9 $PAR IRQ4 3,4,21
2,9 $PERR# 2 IRQ3 3,4,21
2 $REQ#3 $INTD# 2,3
3 $PCIRST# $INTC# 2,3
3 $SERR# $LOCK# 2 R129
2,3,9 $STOP# 1 2 ACER TAIPEI TAIWAN R.O.C
2,3,9 $TRDY#
2,3 $CLKRUN# $RI_OUT# 21 DUMMY-R3 PCMCIA CONTROLLER CHIP PCI 1250
16 SPKR_OUT 1 R301 2 Title
+3.3V 10KR3 390 ACERNOTE LIGHT
Size Document Number REV
A3 96183 SD
Date: August 4, 1997 Sheet 11 of 23
A_SLOT_VCC B_SLOT_VCC
1 1
C117 C116 C118 C319 C297 C326 C295 C296
SCD1U SCD1U SCD1U SCD1U 2 2 SCD1U SCD1U SCD1U SCD1U
C306 C305
ST10U16VBMST10U16VBM
+3.3V +5V +12V A_VPP B_VPP
C122 C313
SCD1U SCD1U
1 H
1 CN16
C127 C126 C119 C128 C140 C139 C145 C321 C138 C107 C302
SCD1U SCD1U SCD1U SC22U10V0ZY SCD1U SCD1U SCD1U 2 ST22U SCD1U SCD1U SC2D2U50V B1 A1
B2 A2
B3 A3
ACAD0 B4 A4 BCAD0
11 ACCD1# ACAD1 B5 A5
B6 A6 BCAD1 BCCD1# 11
ACAD2 B7 A7 BCAD2
ACAD3 B8 A8 BCAD3
ACAD4 B9 A9 BCAD4
ACAD5 B10 A10 BCAD5
ACAD6 B11 A11 BCAD6
ACAD7 B12 A12 BCAD7
B13 A13
11 ARSVD/D14 ACCBE#0 B14 A14
B15 A15 BCCBE#0 BRSVD/D14 11
ACAD8 B16 A16 BCAD8
ACAD9 B17 A17 BCAD9
U31 ACAD10 B18 A18 BCAD10
+3.3V 15 3.3V AVPP 8 A_VPP ACAD11 B19 A19 BCAD11
16 3.3V 9
AVCC 10 A_SLOT_VCC 11 A_VS1 ACAD12 B20 A20
17 3.3V AVCC 11 B21 A21 BCAD12 B_VS1 11
+5V 1 5V AVCC +3.3V ACAD13 B22 A22 BCAD13
2 5V B23 A23
30 5V BVCC 20 B_SLOT_VCC ACAD14 B24 A24 BCAD14
+12V 7 12V BVCC 21 ACAD15 B25 A25 BCAD15
24 12V BVCC 22 ACCBE#1 B26 A26 BCCBE#1
BVPP 23 B_VPP U12
C151
SCD1U
ACAD16 B27
B28
A27
A28
BCAD16
6 11 ACPAR BCPAR 11
14 RESET NC 25 1,3,7,8 $SMBDATA 1
2 SDA +VS 8 11 ARSVD/A18 B29 A29 BRSVD/A18 11
3 $PCIRST# RESET# 1,3,7,8 $SMBCLK 3 SCL A0 7 11 ACPERR# B30 A30 BCPERR# 11
3 3,16 SYS_COM 4 O.S. A1 6 11 ACBLOCK# B31 A31 BCBLOCK# 11
11 $DATA 4 DATA 1 GND A2 5 11 ACGNT# B32
B33
A32
A33 BCGNT# 11
11 $CLOCK 5 CLOCK
11 $LATCH LATCH NC 26 RX29 LM75CIMX-3 11 ACSTOP# B34 A34 BCSTOP# 11
NC 27 22KR3 11 ACINT# B35 A35 BCINT# 11
NC 28 11 ACDEVSEL# B36 A36 BCDEVSEL# 11
NC 29 2 B37 A37
19 GND 12 B38
B39
A38
A39
13 NC +3.3V B40 A40
18 NC B41 A41
OC# 11 ACCLK B42 A42 BCCLK 11
11 ACTRDY# B43 A43 BCTRDY# 11
TPS2206 11 ACIRDY# B44 A44 BCIRDY# 11
11 ACFRAME# ACCBE#2 B45 A45
B46 A46 BCCBE#2 BCFRAME# 11
ACAD17 B47 A47 BCAD17
ACAD18 B48 A48 BCAD18
ACAD19 B49 A49 BCAD19
ACAD20 B50 A50 BCAD20
A_VPP A_SLOT_VCC B_VPP B_SLOT_VCC 11,18 A_VS2 ACAD21 B51 A51
B52 A52 BCAD21 B_VS2 11,18
B53 A53
11 ACRST# ACAD22 B54 A54
1 1 1 1 1 1 B55 A55 BCAD22 BCRST# 11
C144 C322 C143 CX3 C121 C304 C120 C303 CX4 11 ACSERR# ACAD23 B56 A56
SCD1U 2 ST10U16VBM SCD1U 2 2 ST100U10VDM SCD1U 2 ST10U16VBM SCD1U 2 ST10U16VBM2 ST100U10VDM B57 A57 BCAD23BCSERR# 11
11 ACREQ#ACAD24 B58 A58
C323 B59 A59 BCAD24BCREQ# 11
ST10U16VBM ACCBE#3 B60 A60 BCCBE#3
B_SLOT_VCC B_SLOT_VCC ACAD25 B61 A61 BCAD25
11,18 ACAUDIO B62 A62 BCAUDIO 11,18
B63 A63
ACAD26 B64 A64 BCAD26
RP23 11 ACSTSCHG B65 A65
RP22 BCSTOP# 1 10 ACAD27 B66 A66 BCAD27BCSTSCHG 11
BCINT# 1 10 BCDEVSEL# 2 9 BCSTSCHG ACAD28 B67 A67 BCAD28
BCSERR# 2 9 BCPERR# BCTRDY# 3 8 ACAD29 B68 A68 BCAD29
BCREQ# 3 8 BCIRDY# BCRST# 4 7 ACAD30 B69 A69 BCAD30
BCAUDIO 4 7 BCLKRUN# 5 6 11 ARSVD/D2 ACAD31 B70 A70
5 6 BCBLOCK# B71 A71 BCAD31 BRSVD/D2 11
SRP10K 11 ACLKRUN# B72 A72 BCLKRUN#11
SRP10K B73 A73
11 ACCD2# B74 A74 BCCD2# 11
A_SLOT_VCC A_SLOT_VCC B75 A75
B76 A76
HAMP-CONN152
RP16 RP15 2
ACINT# 1 10 ACSTOP# 1 10
ACSERR# 2 9 ACPERR# ACDEVSEL# 2 9 ACSTSCHG
ACREQ# 3 8 ACIRDY# ACTRDY# 3 8 11 ACCBE#[0..3] BCCBE#[0..3] 11
ACAUDIO 4 7 ACLKRUN# ACRST# 4 7 11 ACAD[0..31] BCAD[0..31] 11
5 6 ACBLOCK# 5 6
+5V
SRP10K SRP10K
+3.3V
1 U9D
4
ACCD2# 12
RP14 11 CARD_IN# 3
ACCD1# 1 10 BCCD2# 13
ACCD2# 2 9 BCCD1#
A_VS1 3 8 BCCD2# 7 SSHCT08
A_VS2 4 7 B_VS1 ACER TAIPEI TAIWAN R.O.C
5 6 B_VS2
PCMCIA SOCKET & POWER CONTROLLER TPS2206
SRP10K Title
390 ACERNOTE LIGHT
Size Document Number REV
A3 96183 SD
Date: August 7, 1997 Sheet 12 of 23
CHGR_5VSB
C277
SCD1U
+5V
KKK KKK KK KKK KKK KK
CCCCCCCCCCCCCCCC
OOOOOOOOOOOOOOOO +5V +5V 1 U29A
LLL LLL LL LLL LLL LL 4
C146 123 456 78 911 111 11 3 CHGR_DATA 1 2 CHGR_S_DATA 22
SCD1U 01 234 56 1
1 R125
RY4 10KR3
4
8474645444342414039383736353433 U34
10KR3 7 1 SO4066
2 3
P P P P P P P P P P P P P P P 2
01
0 020304050607001112131415161P1
7
KROW8 49 P37 32
P20 31 HOTKEY# 3
KROW7 50 P36 P21 30 HOTKEY1 3
KROW6 51 P35 P22 29 1 U29B
KROW5 52 P34 P23 28 4
KROW4 53 P33 P24 27 3 CHGR_CLK 11 10 CHGR_S_CLK 22
KROW3 54 P32 P25 26 CLLED# CLLED# 22
KROW2 55 P31 P26 25 NLLED# NLLED# 22
KROW1 56 P30 P27 24
57 VCC VSS 23 7 1
2 SO4066
TDATA 58 P61/CNTR0 P XOUT 22
TCLK 59 P60/INT5/OBF2 4 XIN 21 CLK7M 8 R123
XD7 60 DQ7 5 P40 1 2 B_SMB_DATA
XD6 61 DQ6 /I P41/INT0 20
XD5 62 DQ5 P B 19
RESET# 18 RSTDRV#4 100R3
XD4 63 DQ4 5
3 P P P F P P R103 1 U29C
XD3 64 DQ3 /S 5
2
/S5
PP
1 54 76 40 #44
/O3
4 CNVSS 17
/I P42/INT1
1 2 B_SMB_CLK 4
D D D W R C R
D C /T 0
/R/IN/IN/OB B N 100R3
B_SMB_DATA 4 3 SMB_DATA 22
Q Q Q R D S A Y L X X T
2 1 0 # # # 0 # KDD4 3 1 0 2 T F F T
11 12 13 14 1516 1 M38813 7 5 SO4066
12 3456 789 0
XD2 KBDATA KBDATA 22,23
XD1 I I KS MMI I KBCLK KBCLK 22,23
XD0 OOB A SSRR
WRC2 DCQQ 1 U29D
##S AL 1 1 4
3,19 XD[0..7] 3 IOW# # T K2 B_SMB_CLK 8 9 SMB_CLK 22
3 IOR# A
3 ROMKBCS# 7 6 SO4066
3 SA2
1,8 CLK_SEL0 IRQ1 3,4 PWRGOOD
22 PWRGOOD
1,8 CLK_SEL1 IRQ12 3,4
4 CRT MSCLK 22,23 +5v
MSDATA 22,23 C307
+5v
SCD1U
1
TPZ2 R241
TP-1 47KR3 1 U9B
+5V 4
14 DR0# DR0# 2 4
6 MEDIA_LED# 22
RP21 5
KROW8 1 10
KROW6 2 9 KROW7 +5V pull-high R at source +5v 7 SSHCT08
KROW4 3 8 KROW5 1 U9C
KROW2 4 7 KROW3 1 4
5 6 KROW1 R269 20 HDD_LED# HDD_LED# 9
10KR3 8
+5V SRP10K 20 CDROM_LED# CDROM_LED#10
2
COVERSW3 7 SSHCT08
+5V
+5V +5V
1 C339 1
R282 CN18 SCD1U R290
10KR3 17 1 10KR3
18 2
TCLK 2 19 3 2 TDATA
20 4
C335 KROW2 21 5 KROW1 C340
SC47P KROW4 22 6 KROW3 SC47P
KROW6 23 7 KROW5
KROW8 24 8 KROW7
KCOL2 25 9 KCOL1
KCOL4 26 10 KCOL3
KCOL6 27 11 KCOL5
KCOL8 28 12 KCOL7
KCOL10 29 13 KCOL9
KCOL12 30 14 KCOL11
KCOL14 31 15 KCOL13
KCOL16 32 16 KCOL15
MOLEX-CONN32B
3 3MODE#
SCD1U
5
4 4
6 1
R197
2 P3_MODE XNOCON
2 2
1
R196
2 PNOCON
Serial Port COM1
33R3 100R3 CN3
7 SSABT125 10
R195 5
3 FDD/PRT# 1 2 PFDD/PRT# 9 PRI1# 14
4 PDTR1# 14
+5V U40A 100R3 8 PCTS1# 14
+5V 3 PSOUT1#14
1 SSHCT32 U47C +5V 7 PRTS1# 14
4 1 U47D 2 PSIN1 14
FDD5VON# 1 4 TSHCT08 1 6 PDSR1# 14
RZ142 3 9 4 TSHCT08 1 PDCD1# 14
+5V 1 2
10
8 12
11
11
10KR3 7 14 MTR0# 13 GPI9 3
DZ4 7 14 MTR1# RS232-9-4-D C14 C15 C16 C17 C18 C19 C220 SC680P
C221
PBUSY 2 1 RY2 RY3 7 SC680P SC680P SC680P SC680P SC680P SC680P SC680P
S1N4148 +5V 1 2 +5V 1 2 Wide GND line
D12 100KR3 100KR3
1 2
+5V +5V
S1N4148 1 U8F 1 U8A
4 4
XNOCON 1 R2332 13 12 1 2 NOCON NOCON 3
1MR3
C273 7 SSHCT14 7 SSHCT14
SC1U25V5MY +5V +5V CX1
1
R11 SCD1U
+5V +5V 10KR3 U13
1 U8E 1 U2A 1 GND OUT 8 FDD+5V
4 4 1 2 2 IN OUT 7
R10 3 IN OUT 6
FDD/PRT# 11 10 PNF 2 3 FDD5VON#1 2 4 EN# OUT 5 1
R205
100KR3 TPS2013D 1 100KR3 C222
7 SSHCT14 7 SSABT125 C223 SCD1U
ST10U16VBM2 2
PNF
ACER TAIPEI TAIWAN R.O.C
PARALLEL & SERIAL PORT
Title
390 ACERNOTE LIGHT
Size Document Number REV
A3 96183 SD
Date: August 5, 1997 Sheet 15 of 23
+5V
+5V
+5V
1 +5V
R254 C320
1 U38C 100KR3 SCD1U 1 U32E
4 1
1 CPU_COM 9
0
8
2
11
4
10 1
R244
2 1
3
Q6
FAN conn.
2SJ317
12 SYS_COM 100KR3 2
7 SSAHCT125 7 SSHCT14 C301 CN12
1 1
1 R112 2
DUMMY-R3 SCD1U C300
+5V R321 SCD1U CON2-10
DUMMY-R3
2
2
U14
1 GND OUT 8 USBPWR1
USBPWR123
2 IN OUT 7
3 IN OUT 6
4 EN# OC# 5 1
1 C3 C24 C216
SCD1U TPS2014 2 ST100U10VDM SCD1U
2
C233 1
ST10U16VBM C249 R17
1 SCD1U 0R3 +3.3V
R208
100KR3 RX22 2 CN1
+3.3V 1 2 $OVCR#0 3 1 6
2 R66 USBPWR1 1
3 USB_ON# 10KR3 100KR3 3,4,23 $USBP00 2
1 3,4,23 $USBP01 3
R209 2 4
DUMMY-R3 3,23 USB_OUT/IN 5
7
2 C217 BERG-USB
R31 SC470P
1 2 IRTX 14
1 82R3
R30
100KR3
R194 DIRECTLY CONNECTING TO CHASIS ( PIN 6 , 7 )
1 2 2
10R6
R193
+5V +5V 1 2
1
10R6 2 C22 C21
1 1 D1 2 ST4D7U SCD1U
R2 R38 S1N4148
100KR3 100KR3
U1 1
2 2 1 IRED CATH TX IN 7 R1 Q3 2SJ317
14 IRRX 2 RX OUT NC 5 1 2 +5V
8 IRED ANODE GND 4 R4
14 IRSEL0 6 SD/MODE VCC 3 DUMMY-R3 2 1 FIR+5V 2 3
9 GND PAD GND PAD 10 C30 C1 33R5 C2
SC2D2U16V5ZY SCD1U C29 1 SCD1U
TFDS6000 SCD47U50V6ZY C20
FIR GND to pin4 R16
SCD1U
3 FIR_EN# 1 2
10KR3
+5V +5V
2
C357 D11
21 RING_MODEM S1N4148 BZ1
1
SCD1U 1
R228
1 2 2
C276 R227 3 33R3 BUZZER-3
SPKR 1 2 1 Q12 C269
+5V 3 SPKR SMPSA13 SC22P
SCD1U 47KR3 2 2
+5V D10
1 S1N4148
RZ11
1KR3 1 U32F 1
4
2 C275
11 SPKR_OUT 13 12
SCD1U
7 SSHCT14
C287
OUTL SOUND_L 18
R64 C71
18 RDATA_RACE 1 2 SC1U25V5MY
C67 C77
10KR3 SCD22U16V3ZY C288 TRECL MIC MIC_IN 18
OUTR SOUND_R 18
C72 SCD01U50V3JX SCD1U
SC3300P50V3KX C86 SC1U25V5MY 1
C96 R54
7K5R5F
SCD22U16V3ZY C270
SC1U10V5KX TRECR 2
S S S S T T A A MMV V SCD01U50V3JX
B BYY RRUUI I RR C95 R53
F F NNEEXX CNE E V L L C COO SC1U10V5KX 1 2 VDDA
L L SS CC2 2 FF DI I DDUU
T T HHRL L R OI DNN_ _ T T C58 7K5R5F
RLLR A EEL RL R C286 SYNSHR C66
LR SCD01U50V3JX
SC1KP
SC1KP 1
1 C70
0 999 9999 999 888 888 888 8777 7 U20 2 ST10U16VBM
0 987 6543 210 987 654 321 0987 6 C266
S S S S T T A A MMV V A A L L A A OOV V V V A VDDD SYNSHL
B B Y Y R RUU I I R RV V I I U UUUO OO OD
F F NNE EXX CNE ESDNNX XT T CCCCF SC1KP
1 L L SSCC2 2 F F S D E E I I L RI I O OL C99
VDDA 2 AVSS TR TL H
LR
HRL L R OI L RL R L RRL T
L ADFLTR 75
3 AVDD 74 C59
4 GP0 DVSS 73 SC1KP SBFLTL
5 GP1 SEL0 72 ALL AUD-GND ARE SIGLE VIA TO GND
6 GP2 SEL1 71 SC1KP
7 GP3 SEL2 70
8 GP4 MP0 69
9 GP5 MP1 68 SA12 C267
10 GP6 MP2 67 SA13 SBFLTR
11 GP7 MP3 66 SA14
12 DVSS MP4 65 SA15 SC1KP
3 RSTDRV 13 RESET MP5 64
3 IOW# 14 IOW# MP6 63 $ZV_SCLK 11
3 IOR# VDDD 15 IOR# MP7 62 $ZV_LRCLK 11
AEN 16 DVDD MP8 61 $ZV_DATA 11
SA11 17 AEN MP9 60 VDDD
SA10 18 A11 DVDD 59
SA9 19 A10 VOLUP# 58 VOLUP# 3
20 A9 VOLDW# 57 SA0 VOLDWN# 3
3,4,21 IRQ3 21 IRQ3 A0 56 SA1
3,4,21 IRQ5 22 IRQ5 A1 55 SA2
3,4 IRQ7 23 IRQ7 A2 54
3,4 IRQ9 24 IRQ9 X33O 53 X33I
3,4,21 IRQ10 25 IRQ10 X33I 52
3,4 IRQ11 IRQ11 X24O 51 X24I
D D X24I
A D A
DCDADC DD D +5V
RKRCRK VV V RT
Q 0 QK Q 3 DD DDD S DD DDA A A A A A S X X +5V
0 # 1 1 3 # 0 1 2 3 DS4 5 6 7 8 7 6 5 4 3 S DD
2 222 3333 333 333 444 444 4444 5 YMF715
6 789 0123 456 789 012 345 6789 0 1
R108
100KR3
C137
2 U33 SCD1U
3,4 DRQ0 V SA12 1 A VCC 16
3,14 DACK#0 SSSSD SSSSSSSSSS SA13 2 B Y0 15 16BIT_AEN 16BIT_AEN 14,21
3,4 DRQ1 DDDDD DDDDA AAA AA SA14 3 C Y1 14
3,14 DACK#1 01 23D 45 678 765 43 Y2 13
3,4 DRQ7 6 G1 Y3 12
3,14 DACK#7 3 AEN 4 G2A Y4 11
SA15 5 G2B Y5 10
Y6 9
3,14,19,21 SD[0..7] 3 SA[0..15] 8 GND Y7 7
+5V
SSHCT138
VREFO
1
RZ12 1
100KR3 C283 C81
8 AUDIO14M SCD1U 2 ST10U16VBM
U28 2
1 X1 X2 8 R238 X33I
VDDD 2 VDD PD# 7 1 2 C268
3 GND 33.9M 6 MIN
4 16.9M 24.6M 5 33R3 C298 G1
C314 R237 SC10P SC1U10V5KX 1 2
SCD1U MK1422 1 2 X24I 1
R230 GAP-CLOSE
CX27 33R3 220KR3 VREFI
SCD1U CX25 C294
SC27P CX26 SC10P 2 1
SC27P C284 C82
SCD1U 2 ST10U16VBM
ACER TAIPEI TAIWAN R.O.C
AUDIO CHIP YMF715
Title
390 ACERNOTE LIGHT
Size Document Number REV
A2 96183 SD
Date: August 12, 1997 Sheet 17 of 23
+5V
R85
-INL 1 2 -OUTL
1
47KR3
+5V 2 R80 CZ5 C308
C290 17 SOUND_L 1 2 1 2 LINE_OUT_L
1 ST4D7U 33KR3 SC150P ST100U10VDM
RZ13 CN13
10KR3 -OUTL 1
+OUTL 2
2 U27
3 ENAUDIO# 1 SH_DOWN HP-IN 16 OP_HP_IN OP_HP_IN 23 CON2-10
2 GND GND 15 CX28 CX29
+OUTL 3 +OUTA +OUTB 14 +OUTR 1 SC1KP SC1KP
4 VDD VDD 13 R76
-OUTL 5 -OUTA -OUTB 12 -OUTR 100KR3
-INL 6 -INA -INB 11 -INR CN15
7 GND BYPASS 10 2 -OUTR 1
8 +INA +INB 9 +OUTR 2
LM4863 CON2-10
CX30 CX31
SC1KP SC1KP
R73
C291 -INR 1 2 -OUTR
SC1U25V5MY
47KR3
R77 CZ6 C299
17 SOUND_R 1 2 1 2 LINE_OUT_R
33KR3 SC150P ST100U10VDM
+5VA
OP_VREF
C264
SCD1U
+5VA C259
SCD1U
CN14
11 1 8 U5A
12 2 LINE_OUT_L LINE_OUT_L 23
13 3 LINE_OUT_R LINE_OUT_R 23 1 3 C50
14 4 OP_HP_IN R214 C75 R218 1 MODEM_MIC 21
15 5 +5V 20KR3 MIC_IN 1 2 2
16 6 LINE_IN_L LINE_IN_L 17,23 SCD1U
17 7 LINE_IN_R LINE_IN_R 17,23 2 SCD1U 20KR3 SLM1458
18 8 MIC_IN MIC_IN 17,23 4 C54
19 9 OP_VREF A_VS2 A_VS2 11,12
20 10
SCD1U
MOLEX-CON10-2 1
R215 C43
20KR3 SC1U25V5MY R219 C38
1 2 B_VS2 B_VS2 11,12
2
47KR3 SCD1U
AUDIO JACK BOARD FOR 390
C263
SC150P
C68 R36
21 MODEM_SPKR 1 2
SCD1U 20KR3
+5VA
C310 R23 R26
12 BCAUDIO 1 2 1 2 OP_VREF
SCD1U 10KR3 10KR3
1 C42 +5VA
R37 C63 SCD1U
3 20KR3 SCD1U
3 ZVB_ON 1 Q10 U5B
2N7002 2
1 2 5
R141 C265 R216 7
100KR3 1 2 6
2 SCD1U 20KR3 SLM1458
1
R29 C37
20KR3 SC3300P50V3KX
2
R35
C271 R40 R39 1 2
12 ACAUDIO 1 2 1 2
20KR3
SCD1U 10KR3 10KR3
C260
3 RDATA_RACE RDATA_RACE 17
3 ZVA_ON 1 Q11
2N7002 SC330P
1 2
R120
100KR3
2
+5V
RN6
3 SA[0..15] XD0 1 8 SD0
XD1 2 7 SD1
XD2 3 6 SD2
XD3 4 5 SD3
C312 SRN0
U7 SCD1U
SA0 12 A0 VCC 32
SA1 11 A1
SA2 10 A2 DQ0 13 XD0
SA3 9 A3 DQ1 14 XD1 RN7
SA4 8 A4 DQ2 15 XD2 XD4 1 8 SD4
SA5 7 A5 DQ3 17 XD3 XD5 2 7 SD5
SA6 6 A6 DQ4 18 XD4 XD6 3 6 SD6
SA7 5 A7 DQ5 19 XD5 XD7 4 5 SD7
SA8 27 A8 DQ6 20 XD6
SA9 26 A9 DQ7 21 XD7 SRN0
SA10 23 A10
SA11 25 A11
SA12 4 A12 PGM 31 MEMW#3 SKT1
SA13 28 A13
SA14 29 A14
SA15 3 A15 VSS 16 RESERVED
3 BIOSA16 2 A16 CONTROL FROM BOM
3 ROMKBCS# 22 CE VPP 1
3 MEMR# 24 OE A17/N.C 30
S128K8-150
3 C311
2 Q13 SCD1U
S2N3906 SSKT32
1
3 BIOSA17 1
R243 +12V
10KR3
PLCC ROM SOCKET
2
3
3 FLASH_ON 2 Q14
RN1424
1
L13
1 2 CDROM_5V
SCHOKE-D
1 1
4 CN19 C344 C346 C347 C341
3 ST10U16VBM 2 SCD1U SCD1U 2 ST10U16VBM
HDD_5V 42
RP25 1
DSD4 1 10 IDE_D8 2 21 RSTDRV# 4
DSD5 2 9 DSD0 IDE_D9 3 22 IDE_D7
DSD6 3 8 DSD1 1 IDE_D10 4 23 IDE_D6
DSD7 4 7 DSD2 R305 IDE_D11 5 24 IDE_D5
5 6 DSD3 5K6R3 IDE_D12 6 25 IDE_D4
IDE_D13 7 26 IDE_D3
SRP10K 2 IDE_D14 8 27 IDE_D2 CN20 CD-ROM 2 CONN.
HDD_5V IDE_D15 9 28 IDE_D1 R308 CDROM_5V 33 34
3 PIDEDRQ 10 29 IDE_D0 1 2 SIRQI 3
PIDEIOR# 11 30 1 1 2 SIDED8
R306 PIDRDY 12 31 PIDEIOW# 1 0R3 R317 SIDED9 3 4 SIDED10
3 PIDE_DACK# 2 1 13 32 R309 4K7R3 SIDED11 5 6 SIDED12
14 33 4K7R3 SIDED13 7 8 SIDED14
33R3 15 34 2 SIDED15 9 10 SIDEDRQ 3
PIDEA2 16 35 PIDEA1 2 SIDEIOR# 11 12
IDE_CS3# 17 36 PIDEA0 R280 13 14
HDD_5V 1 18 37 IDE_CS1# 3 SIDE_DACK# 2 1 15 16 SIDEA2 1
RP55 R307 19 38 HDD_LED# 13 CD_CS3# 17 18 CDROM_5V R320
DSD121 10 4K7R3 20 39 33R3 CDROM_5V 19 20 5K6R3
DSD132 9 DSD8 40 21 22
DSD143 8 DSD9 2 41 1 23 24 LED CDROM_LED# 13 2
DSD154 7 DSD10 R285 CD_CS1# 25 26 SIDEA0
5 6 DSD11 4K7R3 SIDEA1 27 28 INTR
4 HRS-CON40 SIDRDY 29 30 SIDEIOW#
SRP10K 4 2
HDD_5V +5V 2 31 32
L18 R318
1 2 HDD_5V 1KR3 MOLEX-CONN30A
SCHOKE-D 1
C342 C345 1
2 ST22U SCD1U CDROM_5V
CDROM_5V
2 R281
R319 INTR 1 2 SIRQII 3
CDROM_5V 4K7R3
0R3
RP65 CDROM_5V 1 1
SID4 1 10 RP64 R276
SID5 2 9 SID0 SID12 1 10 LED 4K7R3
SID6 3 8 SID1 SID13 2 9 SID8
SID7 4 7 SID2 SID14 3 8 SID9 2
5 6 SID3 SID15 4 7 SID10
5 6 SID11
CDROM_5V SRP10K
SRP10K
CDROM_5V
RP26
3 PDSA0 1 8 PIDEA0
3 PDSA1 2 7 PIDEA1 CD_AUDL 17
3 PDSA2 3 6 PIDEA2 CN17
3 PIDERDY 4 5 PIDRDY 41 44
SRN47 1 RX25 2 HDD_5V SIDED0 1 2 SIDED1
3 DSD[0..15] 3 SID[0..15] 4K7R3 SIDED2 3 4 SIDED3
SIDED4 5 6 SIDED5
SIDED6 7 8 SIDED7
RP49 RSTDRV# 9 10
3 SIDA0 1 8 SIDEA0 11 12
3 SIDA1 2 7 SIDEA1 17 CD_AUDR 13 14 +5V
3 SIDA2 3 6 SIDEA2 15 16 R267
RP53 RP57 3 SIDERDY 4 5 SIDRDY 14 HDSEL# 17 18 1 2
DSD0 1 8 IDE_D0 SID0 1 8 SIDED0 14 RDATA# RDATA# 19 20
DSD1 2 7 IDE_D1 SID1 2 7 SIDED1 SRN47 14 WRTPRT# WRTPRT# 21 22 CD/FDD# 3 100KR3
DSD2 3 6 IDE_D2 SID2 3 6 SIDED2 14 TRK0# TRK0# 23 24 R263
DSD3 4 5 IDE_D3 SID3 4 5 SIDED3 14 WGATE# 25 26 1 2 3MODE# 3
14 WDATA# 27 28
SRN100 SRN100 14 STEP# 29 30 0R3
14 FDIR# 31 32
RP54 RP34 14 MTR0# 33 34 +5V
DSD4 1 8 IDE_D4 SID4 1 8 SIDED4 14 DSKCHG# DSKCHG# 35 36
DSD5 2 7 IDE_D5 SID5 2 7 SIDED5 14 DR0# 37 38
DSD6 3 6 IDE_D6 SID6 3 6 SIDED6 R156 14 INDEX# INDEX# 39 40
DSD7 4 5 IDE_D7 SID7 4 5 SIDED7 3 SIDECS3# 1 2 CD_CS3#
43 42
SRN100 SRN100 47R3 1
MOLEX-CONN40A C317 C327 C324
RP29 RP60 R302 SC1KP SCD1U 2 ST10U16VBM
DSD8 1 8 IDE_D8 SID8 1 8 SIDED8 3 SIDECS1# 1 2 CD_CS1#
DSD9 2 7 IDE_D9 SID9 2 7 SIDED9
DSD10 3 6 IDE_D10 SID10 3 6 SIDED10 47R3
DSD11 4 5 IDE_D11 SID11 4 5 SIDED11
SRN100 SRN100 R159
3 PIDECS3# 1 2 IDE_CS3# FDD/CD-ROM CONN.
RP30 RP63
DSD12 1 8 IDE_D12 SID12 1 8 SIDED12 47R3
DSD13 2 7 IDE_D13 SID13 2 7 SIDED13
DSD14 3 6 IDE_D14 SID14 3 6 SIDED14 R293
DSD15 4 5 IDE_D15 SID15 4 5 SIDED15 3 PIDECS1# 1 2 IDE_CS1#
SRN100 SRN100 47R3
R303
3 SIDIOR# 1 2 SIDEIOR#
47R3 +5V
R154 R253
3 SIDIOW# 1 2 SIDEIOW# INDEX# 1 2
47R3 R255 1KR3
DSKCHG# 1 2
1KR3 R261
R157 TRK0# 1 2
3 PIDIOR# 1 2 PIDEIOR#
R266 1KR3
47R3 WRTPRT# 1 2
R292 1KR3 R275
3 PIDIOW# 1 2 PIDEIOW# RDATA# 1 2
47R3 1KR3 ACER TAIPEI TAIWAN R.O.C
THESE RESISTORS MUST BE CLOSED FDD CONN. IDE CONN
Title
390 ACERNOTE LIGHT
Size Document Number REV
A2 96183 SD
Date: August 5, 1997 Sheet 20 of 23
R338
XXDIR 1 2
+5V
DUMMY-R3
RP68
SD0 1 10
SD1 2 9 SD4
SD2 3 8 SD5
R339 SD3 4 7 SD6
DIS_ROM1 2 +5V 5 6 SD7
DUMMY-R3 +5V SRP10K
+5V
SD[0..15] GF1 SA[0..16] 3
SD5 35 A1 B1 1 RP70
SD6 36 A2 2
B2 3 SD8 1 10
SD7 37 A3 B3 4 SD9 2 9 SD15
SD8 38 A4 B4 5 SA0 SD10 3 8 SD14
SD9 39 A5 B5 6 SA1 SD11 4 7 SD13
SD10 40 A6 B6 7 SA2 +5V 5 6 SD12
SD11 41 A7 B7 8 SA3
SD12 42 A8 B8 9 SA4 SRP10K
SD13 43 A9 B9 SA5
SD14 44 A10 B10 10 SA6
SD15 45 A11 B11 11 SA7 +5V
46 A12 B12 12 SA8
XXDIR 47 A13 B13 13 SA9 RP71
22 PWRGIN 48 A14 B14 14 SA10 LA17 1 10
3 FLASH_ON DIS_ROM 49 A15 B15 15 SA11 LA18 2 9 SBHE#
50 A16 B16 16 SA12 LA19 3 8 LA21
MEMW# 51 A17 B17 17 SA13 LA20 4 7 LA23
MEMR# 52 A18 B18 18 SA14 +5V 5 6 LA22
3,21 LA20 LA20 53 A19 B19 19 SA15
3,21 LA21 LA21 54 A20 B20 20 SA16 SRP10K
3,21 LA22 LA22 55 A21 B21 21 LA17 LA17 3,21
3,21 LA23 LA23 56 A22 B22 22 LA18 LA18 3,21
3,4 IRQ11 IRQ11 57 A23 B23 23 LA19 +5V
58 A24 B24 24 SBHE# LA19SBHE#
3,21
3,4
3 BALE 59 A25 B25 25 BIOSA16 3 RP72
60 A26 B26 26 BIOSA17 3 MEMW# 1 10
3 IOR# IOR# 61
62 A27 B27 27 ROMKBCS# 3 MEMR# 2 9 IOCHK# IOCHK# 3,4
3 IOW# IOW# 63 A28 B28 28 MEMR# MEMR#3 3 8
3 AEN A29 B29 29 MEMW# MEMW#3 4 7 IOW#
3,4 IOCHRDY IOCHRDY 64
65 A30 B30 30 SD0 +5V 5 6 IOR#
3 RSTDRV RSTDRV 66 A31 B31 31 SD1
+5V 67 A32 B32 32 SD2 SRP10K
68 A33 B33 33 SD3
A34 B34 34 SD4 +5v
MS-DBG-GF68
C338
1 U40C SCD1U
4
14 RI_232# 9
8
MODEM_RI 10
7 SSHCT32
1
R279 +5v
+3.3V 100KR3 +5v 1 U40B
+5V 1 U32B 4
2 4 4
6 $RI 3
11 $RI_OUT# 3 4 5
1
1 C372 C373 1 7 SSHCT32
C366 C375 C374 2 SC1KP SCD1U R142 7 SSHCT14
2 ST2D2U25VBM SC1KP SCD1U C365 100KR3
ST2D2U25VBM
CN24 2
2 1
SA0 4 3 SD0
SA1 6 5 SD1 +5V
SA2 8 7 SD2
SA3 10 9 SD3
SA4 12 11 SD4
SA5 14 13 SD5 L17
SA6 16 15 SD6 1 2
SA7 18 17 SD7
SA8 20 19 SD8 CN23 BLM31A601S CN6
SA9 22 21 SD9 2 1 C285 GND 5
SA10 24 23 SD10 4 3 SC1KP1KV RV1 1 1 1
SA11 26 25 SD11 6 5 P3100SB 2 2
3,4,11,14,17 IRQ3 28 27 SD12 8 7 3 3
3,4,11,14 IRQ4 30 29 SD13 10 9 2 4 4
3,4,11,14,17 IRQ5 32 31 SD14 C94 RJ11_GND GND 6
3,4,11,14,17 IRQ10 IRQ11 34 33 SD15 SAM-CONN10D SC1KP1KV
36 35 16BIT_AEN 17 1 2 RJ11-11395
38 37 L10
IOW# 40 39 MODEM14M 8 BLM31A601S
IOR# 42 41
3 MODEM_EN# MODEM_RI 44 43 IOCHRDYIO16# 3,4 RJ11_GND
46 45 +5V
+12V 48 47 RSTDRV
50 49 RING_MODEM 16
18 MODEM_MIC 52 51 MODEM_SPKR 18
SAM-CONN52D
C371
SC1U25V5MY
+5V
3
BT_QCHG 2 Q5
RN1424
1 87 65
RN5
SRN10K
+5V +5V
1 U32C 1 U32D 12 34
4 4 KBCLK R25
13,23 KBDATA 1 2
PWRGIN 5 6 9 8 PWRGOOD3,13 CN10
47R3 2 1
4 3
7 SSHCT14 7 SSHCT14 R22 6 5
13,23 MSDATA 1 2 8 7 R42
10 9 1 2 KBCLK KBCLK 13
47R3
SAM-CONN10D 47R3
PWRGOOD#19 R21 C56
13 MSCLK 1 2 SC47P
47R3
BT+ CN22 C36
L14 BT+SENSE 1 SC47P
1 2 2
SCHOKE-D SMB_CLK
SMB_DATA
3
4
C35
SC47P
TH 5
6 C45
BT- BT-SENSE 7 SC47P
MOLEX-CON7-1
USING WIDE TRACE TO CHGR CONN GND C369
SC330P
C202
SCD1U
C362
SCD1U
CX5
SC1KP
C370
SC330P
C376
NOTE : BT+SENSE & BT-SENSE BOTH USE THIN TRACE FOR CONNECTION
BETWEEN CHARGER AND BATT CONN
SC1KP
METAL BT+SENSE ===> CHGR PIN 9 CONNECT TO BATT CONN PIN 1
PAD ACER TAIPEI TAIWAN R.O.C
BT-SENSE ===> CHGR PIN 6 CONNECT TO BATT CONN PIN 6
DC-DC & CHARGER & BAT CONN
USING WIDE TRACE TO THE CHASSIS GND Title
390 ACERNOTE LIGHT
Size Document Number REV
A3 96183 SD
Date: August 14, 1997 Sheet 22 of 23
CN5
1 2 DOCK_IN1#
14 PAUTOFD# 3 4 PSTROB#14
14 PERROR# 5 6 PPD0 14,15,23
7 8 PPD1 14,15,23
14,15,23 PPD2 9 10 PINIT# 14
11 12
R221 DOCK+5V 13 14 DOCK+5V
15 16
3 BUFFER_EN 1 100R32 17 18 1 R229
2 NTSC/PAL# 3
3 $STANDBY# 19 20 100R3
18 OP_HP_IN 21 22 LINE_OUT_L 18
18 LINE_OUT_R 23 24 LINE_IN_L 18
18 LINE_IN_R 25 26 MIC_IN 18
27 28
14 PDCD1# 29 30
31 32 TV_EN 3
15 EXT_FDD_SMI# 33 34
35 36
37 38
39 40
41 42
43 44 $VGA14M8
45 46
13 MSCLK 47 48 MSDATA 13,22
13 KBCLK 49 50 KBDATA 13,22
51 52
10 DOCK_DDC_DATA 53 54 DOCK_HSYNC10
10 DOCK_VSYNC 55 56
10 $DOCK_B 57 58 $DOCK_G10
10 $DOCK_R 59 60
61 62
63 64 DC_IN
65 66
22 DC_IN DC_IN 67
69
68
70
71 72 PSLCTIN# 14
14,15,23 PPD3 73 74
14,15,23 PPD4 75 76 PPD5 14,15,23
14,15,23 PPD6 77 78 PPD7 14,15,23
79 80 PACK# 14
14 PBUSY 81 82 PPE 14
14 PSLCT 83 84
14 PRI1# 85 86 PDTR1# 14
14 PCTS1# 87 88 PSOUT1#14
14 PRTS1# 89 90 PSIN1 14
14 PDSR1# 91 92
93 94 RDATA# 14
14 WRTPRT# 95 96 TRK0# 14
R55 14 WGATE# 97 98 HDSEL# 14
14 STEP# FDIR# 14
3 EXT_FDD_5V_ON 1 2 99
101
100
102 WDATA# 14
R43 100R3 14 3
DSKCHG#
3MODE# 103 104 MTR1# 14
DR1# 14
DOCK_OK 1 2 105 106 INDEX# 14
100R3 107 108 DOCK_VSW1 10
10 DOCK_DDC_CLK 109 110 DOCK_VSW3 10
111 112 USB_OUT/IN 3,16
113 114
16 USBPWR1USBPWR1 115
117
116
118
USBPWR1
DOCK_IN2# 3,4,16 $USBP00 119 120 $USBP01 3,4,16
BERG-CONN120 CRT_GND C250
SCD1U
+5V +5V
+5V U15
1 U8C 1 U8D 1 GND OUT 8 DOCK+5V
4 4 2 IN OUT 7
D4 R212 3 IN OUT 6 1
1 2 5 6 9 8 1 2 4 EN# OUT 5 RX26
47KR3
S1N4148 100KR3 TPS2013D
R166 7 SSHCT14 7 SSHCT14 2
1 2 1
C244 C240 C241
47KR3 C188 C32 1 ST10U16VBM2 SCD1U SC1KP
SCD1U
ST4D7U 2
+5V +5V DOCK_OK
1 1 +5V NEAR 120 PIN CONN
R278 R147
100KR3 100KR3
D14
2 2 +5V 1 2 NEAR TP2013
C110
R277 1 U40D S1N4148 SCD1U 1 U8B
4 4
DOCK_IN1# 1 1KR32 12 R167
11 1 2 3 4 DOCK_IN_SMI#DOCK_IN_SMI# 3
DOCK_IN2# 1 2 13
R146 100KR3
1KR3 7 SSHCT32 7 SSHCT14
C191
SCD1U
ACER TAIPEI TAIWAN R.O.C
PORT REPLICATOR
Title
390 ACERNOTE LIGHT
Size Document Number REV
A3 96183 SD
Date: August 5, 1997 Sheet 23 of 23
A p p e n d i x E
Checkpoint Description
04h • Dispatch Shutdown Path
Note: At the beginning of POST, port 64 bit 2 (8042 system flag) is read to determine
whether this POST is caused by a cold or warm boot. If it is a cold boot, a
complete POST is performed. If it is a warm boot, the chip initialization and
memory test is eliminated from the POST routine.
Checkpoint Description
20h • KB controller(8041/8042) testing
• KB type determination
• Write default command byte upon KB type
24h • PIC(8259) testing & initialization
30h • System Shadow RAM
34h • DRAM sizing
3Ch • Initialize interrupt vectors
4Bh • Identify CPU brand and type
35h • PCI pass 0
40h • Assign I/O if device request
41h • Assign Memory if device requested
44h • Assign IRQ if device request
45h • Enable command byte if device is OK
50h • Initialize Video display
52h • Download keyboard matrix
4Ch • ChipUp initialization for CPU clock checking
54h • Process VGA shadow region
58h • Set POST screen mode(Graphic or Text)
• Display Acer(or OEM) logo if necessary
• Display Acer copyright message if necessary
• Display BIOS serial number
59h • Hook int vector 1ch for POST quiet boot
5Ch • Memory testing
5Ah • SMRAM test and SMI handler initialization
4Eh • Audio initialization
60h • External Cache sizing
• External Cache testing(SRAM & Controller)
• Enable internal cache if necessary
• Enable external cache if necessary
64h • Reset KB device
• Check KB status
Note: The keyboard LEDs should flash once.
Checkpoint Description
80h • Set security status
84h • KB device initialization
• Enable KB device
6Ch • FDD testing & parameter table setup
Note: The FDD LED should flash once and its head should be positioned