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Transducer power gain of a terminated two port network is defined as the ratio of the power delivered
to the load to the power available from the source. Sometimes, the power available from the source is
also characterized as the incident power. For the purposes of this derivation, Figure 1 is provided below.
ZS V1+ V2-
+ [S] +
V1- V2+
ZL
Vs V1 V2
( Z0 )
- -
GS Gin Gout GL
The two port is terminated with source impedance 𝑍𝑆 and load impedance 𝑍𝐿 . The source reflectance
Γ𝑆 , input reflectance Γ𝑖𝑛 , output reflectance Γ𝑜𝑢𝑡 , and load reflectance Γ𝐿 are normalized with respect to
some impedance 𝑍0 . The two port network has two port s-parameters which are also normalized to 𝑍0 .
𝑍𝑆 − 𝑍0
Γ𝑆 =
𝑍𝑆 + 𝑍0
𝑍𝐿 − 𝑍0
Γ𝐿 =
𝑍𝐿 + 𝑍0
To solve for the input and output reflectances, we review the definition of S-parameters.
Also,
𝑉2+
Γ𝐿 =
𝑉2−
𝑉1−
Γ𝑖𝑛 =
𝑉1+
𝑉2−
= 𝑆11 + 𝑆12 Γ𝐿 +
𝑉1
𝑆12 Γ𝐿 𝑆21
= 𝑆11 +
1 − 𝑆22 Γ𝐿
𝑉1+
Γ𝑆 = −
𝑉1
𝑉1− 𝑆12
+ = (2)
𝑉2 1 − 𝑆11 Γ𝑆
𝑉2−
Γ𝑜𝑢𝑡 = +
𝑉2
𝑉1−
= 𝑆22 + 𝑆21 Γ𝑆
𝑉2+
𝑆21 Γ𝑆 𝑆12
= 𝑆22 +
1 − 𝑆11 Γ𝑆
𝑃𝑑
𝑇𝑃𝐺 =
𝑃𝑎𝑣𝑠
where 𝑃𝑑 is the power delivered to the load, and 𝑃𝑎𝑣𝑠 is the power available from the source. The power
available from the source is the maximum amount of power that the generator can deliver to a load.
1 𝑉2− 2 2
𝑃𝑑 = 1 − Γ𝐿
2 𝑍0
From (1), 𝑃𝑑 can be expressed as
2
𝑉1+ 2 𝑆21
𝑃𝑑 = (1 − Γ𝐿 2 ) (3)
2𝑍0 1 − 𝑆22 Γ𝐿
Separately, the power supplied to the input port of the network 𝑃𝑖𝑛 is given as
1 𝑉1+ 2 2
𝑃𝑖𝑛 = 1 − Γ𝑖𝑛
2 𝑍0
The maximum power that the source can supply, 𝑃𝑎𝑣𝑠 is equal to 𝑃𝑖𝑛 when 𝑍𝑖𝑛 = 𝑍𝑆∗, or equivalently,
when Γ𝑖𝑛 = Γ𝑆∗. Thus,
𝑉1+ 2
𝑃𝑎𝑣𝑠 = 1 − Γ𝑆 2 (4)
2𝑍0
At this stage, it may seem that the transducer power gain can be obtained by the ratio of (3) to (4), but
note that in the case of (4), the incident voltage 𝑉1+ is not the same as in (3), since it represents a
different circuit. Thus, 𝑉1+ must be expressed in terms of 𝑉𝑆 , which is common to the circuit represented
in (3) and the circuit represented in (4).
𝑍𝑖𝑛
𝑍𝑖𝑛 𝑍0
𝑉1 = 𝑉1+ + 𝑉1− = 𝑉1+ 1 + Γ𝑖𝑛 = 𝑉𝑆 = 𝑉𝑆
𝑍𝑖𝑛 + 𝑍𝑆 𝑍𝑖𝑛 𝑍𝑆
+
𝑍0 𝑍0
Also,
1 + Γ𝑖𝑛
𝑍𝑖𝑛 = 𝑍0
1 − Γ𝑖𝑛
And
1 + Γ𝑆
𝑍𝑆 = 𝑍0
1 − Γ𝑆
1 + Γ𝑖𝑛
𝑉1+ 1 + Γ𝑖𝑛 = 𝑉𝑆
1 + Γ𝑆 1 − Γ𝑖𝑛
1 + Γ𝑖𝑛 + 1 − Γ𝑆
𝑉𝑆 1 − Γ𝑆
𝑉1+ =
2 1 − Γ𝑆 Γ𝑖𝑛
Thus, (3) is rewritten as
2
𝑉𝑆 2 𝑆21 (1 − Γ𝑆 )
𝑃𝑑 = (1 − Γ𝐿 2 ) (5)
8𝑍0 1 − 𝑆22 Γ𝐿 (1 − Γ𝑆 Γ𝑖𝑛 )
For the case of the circuit in (4) where Γ𝑖𝑛 = Γ𝑆∗, we therefore have
𝑉𝑆 2 1 − Γ𝑆 2
𝑃𝑎𝑣𝑠 = (6)
8𝑍0 (1 − Γ𝑆 2 )
2
𝑆21 2 2
𝑇𝑃𝐺 = 1 − Γ𝐿 1 − Γ𝑆
1 − 𝑆22 Γ𝐿 1 − Γ𝑆 Γ𝑖𝑛