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5 4 3 2 1

?
SKL_ULT
UC1B

AU53
17 DDRA_DQ[0..63] DDRA_DQ0 AL71 DDR0_CKN[0] AT53 DDRA_CLK0# 17
DDRA_DQ1 AL68 DDR0_DQ[0] DDR0_CKP[0] AU55 DDRA_CLK0 17
DDRA_DQ2 AN68 DDR0_DQ[1] DDR0_CKN[1] AT55
DDRA_DQ3 AN69 DDR0_DQ[2] DDR0_CKP[1]
DDRA_DQ4 AL70 DDR0_DQ[3] BA56
DDRA_DQ5 AL69 DDR0_DQ[4] DDR0_CKE[0] BB56 DDRA_CKE0 17
D DDRA_DQ6 AN70 DDR0_DQ[5] DDR0_CKE[1] AW56 D
DDRA_DQ7 AN71 DDR0_DQ[6] DDR0_CKE[2] AY56
DDRA_DQ8 AR70 DDR0_DQ[7] DDR0_CKE[3]
DDRA_DQ9 AR68 DDR0_DQ[8] AU45
DDRA_DQ10 AU71 DDR0_DQ[9] DDR0_CS#[0] AU43 DDRA_CS0# 17
DDRA_DQ11 AU68 DDR0_DQ[10] DDR0_CS#[1] AT45
DDRA_DQ12 AR71 DDR0_DQ[11] DDR0_ODT[0] AT43 DDRA_ODT0 17
DDRA_DQ13 AR69 DDR0_DQ[12] DDR0_ODT[1]
DDRA_DQ14 AU70 DDR0_DQ[13] BA51
DDRA_DQ15 AU69 DDR0_DQ[14] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] BB54 DDRA_MA5 17
DDRA_DQ16 BB65 DDR0_DQ[15] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] BA52 DDRA_MA9 17
DDRA_DQ17 AW65 DDR0_DQ[16]/DDR0_DQ[32] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] AY52 DDRA_MA6 17
DDRA_DQ18 AW63 DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] AW52 DDRA_MA8 17
DDRA_DQ19 AY63 DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] AY55 DDRA_MA7 17
DDRA_DQ20 BA65 DDR0_DQ[19]/DDR0_DQ[35] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] AW54 DDRA_BG0 17
DDRA_DQ21 AY65 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] BA54 DDRA_MA12 17
DDRA_DQ22 BA63 DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] BA55 DDRA_MA11 17
DDRA_DQ23 BB63 DDR0_DQ[22]/DDR0_DQ[38] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# AY54 DDRA_ACT# 17
DDRA_DQ24 BA61 DDR0_DQ[23]/DDR0_DQ[39] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDRA_DQ25 AW61 DDR0_DQ[24]/DDR0_DQ[40] AU46
DDRA_DQ26 BB59 DDR0_DQ[25]/DDR0_DQ[41] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] AU48 DDRA_MA13 17
DDRA_DQ27 AW59 DDR0_DQ[26]/DDR0_DQ[42] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] AT46 DDRA_MA15_CAS# 17
DDRA_DQ28 BB61 DDR0_DQ[27]/DDR0_DQ[43] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] AU50 DDRA_MA14_WE# 17
DDRA_DQ29 AY61 DDR0_DQ[28]/DDR0_DQ[44] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] AU52 DDRA_MA16_RAS# 17
DDRA_DQ30 BA59 DDR0_DQ[29]/DDR0_DQ[45] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] AY51 DDRA_BS0# 17
DDRA_DQ31 AY59 DDR0_DQ[30]/DDR0_DQ[46] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] AT48 DDRA_MA2 17
DDRA_DQ32 AY39 DDR0_DQ[31]/DDR0_DQ[47] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] AT50 DDRA_BS1# 17
DDRA_DQ33 AW39 DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] BB50 DDRA_MA10 17
DDRA_DQ34 AY37 DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] AY50 DDRA_MA1 17
DDRA_DQ35 AW37 DDR0_DQ[34]/DDR1_DQ[2] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] BA50 DDRA_MA0 17
DDRA_DQ36 BB39 DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] BB52 DDRA_MA3 17
DDRA_DQ37 BA39 DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4] DDRA_MA4 17
C DDRA_DQ38 BA37 DDR0_DQ[37]/DDR1_DQ[5] AM70 DDRA_DQS#0 C
DDRA_DQ39 BB37 DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQSN[0] AM69 DDRA_DQS0
DDRA_DQ40 AY35 DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQSP[0] AT69 DDRA_DQS#1
DDRA_DQ41 AW35 DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQSN[1] AT70 DDRA_DQS1
DDRA_DQ42 AY33 DDR0_DQ[41]/DDR1_DQ[9] DDR0_DQSP[1] BA64 DDRA_DQS#2
DDRA_DQ43 AW33 DDR0_DQ[42]/DDR1_DQ[10] DDR0_DQSN[2]/DDR0_DQSN[4] AY64 DDRA_DQS2 DDRA_DQS#[0..7]
DDRA_DQ44 BB35 DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQSP[2]/DDR0_DQSP[4] AY60 DDRA_DQS#3 DDRA_DQS#[0..7] 17
DDRA_DQ45 BA35 DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQSN[3]/DDR0_DQSN[5] BA60 DDRA_DQS3 DDRA_DQS[0..7]
DDRA_DQ46 BA33 DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQSP[3]/DDR0_DQSP[5] BA38 DDRA_DQS#4 DDRA_DQS[0..7] 17
DDRA_DQ47 BB33 DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQSN[4]/DDR1_DQSN[0] AY38 DDRA_DQS4
DDRA_DQ48 AY31 DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQSP[4]/DDR1_DQSP[0] AY34 DDRA_DQS#5
DDRA_DQ49 AW31 DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQSN[5]/DDR1_DQSN[1] BA34 DDRA_DQS5
DDRA_DQ50 AY29 DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQSP[5]/DDR1_DQSP[1] BA30 DDRA_DQS#6
DDRA_DQ51 AW29 DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQSN[6]/DDR1_DQSN[4] AY30 DDRA_DQS6
DDRA_DQ52 BB31 DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQSP[6]/DDR1_DQSP[4] AY26 DDRA_DQS#7
DDRA_DQ53 BA31 DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQSN[7]/DDR1_DQSN[5] BA26 DDRA_DQS7
DDRA_DQ54 BA29 DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSP[7]/DDR1_DQSP[5]
DDRA_DQ55 BB29 DDR0_DQ[54]/DDR1_DQ[38] AW50
DDRA_DQ56 AY27 DDR0_DQ[55]/DDR1_DQ[39] DDR0_ALERT# AT52 DDRA_ALERT# 17
DDRA_DQ57 AW27 DDR0_DQ[56]/DDR1_DQ[40] DDR0_PAR DDRA_PAR 17
DDRA_DQ58 DDR0_DQ[57]/DDR1_DQ[41] SMVREF
AY25 AY67 WIDTH:20MIL
DDRA_DQ59 AW25 DDR0_DQ[58]/DDR1_DQ[42] DDR_VREF_CA AY68 DDR_SA_VREFCA 17
DDRA_DQ60 DDR0_DQ[59]/DDR1_DQ[43] DDR0_VREF_DQ SPACING: 20MIL
BB27 DDR CH - A BA67
DDRA_DQ61 BA27 DDR0_DQ[60]/DDR1_DQ[44] DDR1_VREF_DQ DDR_SB_VREFCA 18
DDRA_DQ62 BA25 DDR0_DQ[61]/DDR1_DQ[45] AW67 DDR_VTT_CNTL
DDRA_DQ63 BB25 DDR0_DQ[62]/DDR1_DQ[46] DDR_VTT_CNTL
DDR0_DQ[63]/DDR1_DQ[47]
1 OF 20
SKYLAKE-U_BGA1356
REV = 1 ?
@
B B

+3VALW

RC30
100K_0402_5%
2

CPU_DRAMPG_CNTL 55
+1.2V
1

C
RC3 1 2 2 QC18
1K_0402_5% B
E
3

MMBT3904WH_SOT323-3

DDR_VTT_CNTL
2

RC29 @
10K_0402_5%
1

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (DDR4)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
DG421 1.0

Date: Sunday, January 22, 2017 Sheet 5 of 60


5 4 3 2 1
5 4 3 2 1

?
SKL_ULT
UC1C
18 DDRB_DQ[0..63]

DDRB_DQ0 AF65 AN45


DDRB_DQ1 DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKN[0] DDRB_CLK0# 18
AF64 AN46
DDRB_DQ2 DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[1] DDRB_CLK1# 18
AK65 AP45
DDRB_DQ3 DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[0] DDRB_CLK0 18
AK64 AP46
DDRB_DQ4 DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1] DDRB_CLK1 18
AF66
D DDRB_DQ5 AF67 DDR1_DQ[4]/DDR0_DQ[20] AN56 D
DDRB_DQ6 DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKE[0] DDRB_CKE0 18
AK67 AP55
DDRB_DQ7 DDR1_DQ[6]/DDR0_DQ[22] DDR1_CKE[1] DDRB_CKE1 18
AK66 AN55
DDRB_DQ8 AF70 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKE[2] AP53
DDRB_DQ9 AF68 DDR1_DQ[8]/DDR0_DQ[24] DDR1_CKE[3]
DDRB_DQ10 AH71 DDR1_DQ[9]/DDR0_DQ[25] BB42
DDRB_DQ11 DDR1_DQ[10]/DDR0_DQ[26] DDR1_CS#[0] DDRB_CS0# 18
AH68 AY42
DDRB_DQ12 DDR1_DQ[11]/DDR0_DQ[27] DDR1_CS#[1] DDRB_CS1# 18
AF71 BA42
DDRB_DQ13 DDR1_DQ[12]/DDR0_DQ[28] DDR1_ODT[0] DDRB_ODT0 18
AF69 AW42
DDRB_DQ14 DDR1_DQ[13]/DDR0_DQ[29] DDR1_ODT[1] DDRB_ODT1 18
AH70
DDRB_DQ15 AH69 DDR1_DQ[14]/DDR0_DQ[30] AY48
DDRB_DQ16 DDR1_DQ[15]/DDR0_DQ[31] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDRB_MA5 18
AT66 AP50
DDRB_DQ17 DDR1_DQ[16]/DDR0_DQ[48] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDRB_MA9 18
AU66 BA48
DDRB_DQ18 DDR1_DQ[17]/DDR0_DQ[49] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDRB_MA6 18
AP65 BB48
DDRB_DQ19 DDR1_DQ[18]/DDR0_DQ[50] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] DDRB_MA8 18
AN65 AP48
DDRB_DQ20 DDR1_DQ[19]/DDR0_DQ[51] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] DDRB_MA7 18
AN66 AP52
DDRB_DQ21 DDR1_DQ[20]/DDR0_DQ[52] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDRB_BG0 18
AP66 AN50
DDRB_DQ22 DDR1_DQ[21]/DDR0_DQ[53] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDRB_MA12 18
AT65 AN48
DDRB_DQ23 DDR1_DQ[22]/DDR0_DQ[54] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] DDRB_MA11 18
AU65 AN53
DDRB_DQ24 DDR1_DQ[23]/DDR0_DQ[55] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDRB_ACT# 18
AT61 AN52
DDRB_DQ25 DDR1_DQ[24]/DDR0_DQ[56] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDRB_BG1 18
AU61
DDRB_DQ26 AP60 DDR1_DQ[25]/DDR0_DQ[57] BA43
DDRB_DQ27 DDR1_DQ[26]/DDR0_DQ[58] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] DDRB_MA13 18
AN60 AY43
DDRB_DQ28 DDR1_DQ[27]/DDR0_DQ[59] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] DDRB_MA15_CAS# 18
AN61 AY44
DDRB_DQ29 DDR1_DQ[28]/DDR0_DQ[60] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] DDRB_MA14_WE# 18
AP61 AW44
DDRB_DQ30 DDR1_DQ[29]/DDR0_DQ[61] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] DDRB_MA16_RAS# 18
AT60 BB44
DDRB_DQ31 DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] DDRB_BS0# 18
AU60 AY47
DDRB_DQ32 DDR1_DQ[31]/DDR0_DQ[63] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] DDRB_MA2 18
AU40 BA44
DDRB_DQ33 DDR1_DQ[32]/DDR1_DQ[16] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDRB_BS1# 18
AT40 AW46
DDRB_DQ34 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] DDRB_MA10 18
AT37 AY46
DDRB_DQ35 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDRB_MA1 18
AU37 BA46
DDRB_DQ36 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] DDRB_MA0 18
AR40 BB46
DDRB_DQ37 DDR1_DQ[36]/DDR1_DQ[20] DDR1_MA[3] DDRB_MA3 18
C AP40 BA47 C
DDRB_DQ38 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[4] DDRB_MA4 18
AP37
DDRB_DQ39 AR37 DDR1_DQ[38]/DDR1_DQ[22] AH66 DDRB_DQS#0
DDRB_DQ40 AT33 DDR1_DQ[39]/DDR1_DQ[23] DDR1_DQSN[0]/DDR0_DQSN[2] AH65 DDRB_DQS0
DDRB_DQ41 AU33 DDR1_DQ[40]/DDR1_DQ[24] DDR1_DQSP[0]/DDR0_DQSP[2] AG69 DDRB_DQS#1
DDRB_DQ42 AU30 DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQSN[1]/DDR0_DQSN[3] AG70 DDRB_DQS1
DDRB_DQ43 AT30 DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQSP[1]/DDR0_DQSP[3] AR66 DDRB_DQS#2
DDRB_DQ44 AR33 DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQSN[2]/DDR0_DQSN[6] AR65 DDRB_DQS2
DDRB_DQ45 AP33 DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQSP[2]/DDR0_DQSP[6] AR61 DDRB_DQS#3 DDRB_DQS#[0..7]
DDRB_DQ46 DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQSN[3]/DDR0_DQSN[7] DDRB_DQS3 DDRB_DQS#[0..7] 18
AR30 AR60
DDRB_DQ47 AP30 DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQSP[3]/DDR0_DQSP[7] AT38 DDRB_DQS#4 DDRB_DQS[0..7]
DDRB_DQ48 DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQSN[4]/DDR1_DQSN[2] DDRB_DQS4 DDRB_DQS[0..7] 18
AU27 AR38
DDRB_DQ49 AT27 DDR1_DQ[48] DDR1_DQSP[4]/DDR1_DQSP[2] AT32 DDRB_DQS#5
DDRB_DQ50 AT25 DDR1_DQ[49] DDR1_DQSN[5]/DDR1_DQSN[3] AR32 DDRB_DQS5
DDRB_DQ51 AU25 DDR1_DQ[50] DDR1_DQSP[5]/DDR1_DQSP[3] AR25 DDRB_DQS#6
DDRB_DQ52 AP27 DDR1_DQ[51] DDR1_DQSN[6] AR27 DDRB_DQS6
DDRB_DQ53 AN27 DDR1_DQ[52] DDR1_DQSP[6] AR22 DDRB_DQS#7
DDRB_DQ54 AN25 DDR1_DQ[53] DDR1_DQSN[7] AR21 DDRB_DQS7
DDRB_DQ55 AP25 DDR1_DQ[54] DDR1_DQSP[7]
DDRB_DQ56 AT22 DDR1_DQ[55] AN43
DDRB_DQ57 DDR1_DQ[56] DDR1_ALERT# DDRB_ALERT# 18
AU22 AP43
DDRB_DQ58 DDR1_DQ[57] DDR1_PAR CPU_DRAMRST#_R DDRB_PAR 18
AU21 AT13
DDRB_DQ59 AT21 DDR1_DQ[58] DRAM_RESET# AR18 SM_RCOMP_0 RC24 1 2 121_0402_1%
DDRB_DQ60 AN22 DDR1_DQ[59] DDR_RCOMP[0] AT18 SM_RCOMP_1 RC25 1 2 80.6_0402_1%
DDRB_DQ61 AP22 DDR1_DQ[60] DDR_RCOMP[1] AU18 SM_RCOMP_2 RC26 1 2 100_0402_1%
DDRB_DQ62 AP21 DDR1_DQ[61] DDR_RCOMP[2]
DDRB_DQ63 AN21 DDR1_DQ[62] DDR CH - B
DDR1_DQ[63]

SKYLAKE-U_BGA1356 1 OF 20
REV = 1 ?
B @ B

+1.2V
1

RC22
470_0402_5%
2

RC23 1 @ 2 0_0402_5% CPU_DRAMRST#_R


17,18 CPU_DRAMRST#

1
CC1
1000P_0201_50V7-K
EMC@
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (DDR4)


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG421
Date: Sunday, January 22, 2017 Sheet 6 of 60
5 4 3 2 1
5 4 3 2 1

+3VALW_PCH +3VS +3VS


?
SKL_ ULT
UC1E
SPI - FLASH

3
4

4
3
SMBUS, SMLINK
SPI_CLK_R AV2 R7 PCH_SMB_CLK RPC20 RPC24
D SPI_CLK SPI_CLK_R SPI_SO_R SPI0_CLK GPP_C0/SMBCLK PCH_SMB_DATA D

2
RC1539 1 2 15_0402_5% AW3 R8 DIMM, NGFF 2.2K_0404_4P2R_5% 2.2K_0404_4P2R_5%

G
44 SPI_CLK SPI_SI_R AV3 SPI0_MISO GPP_C1/SMBDATA R10 SMB_ALERT#
SPI_WP#_R AW2 SPI0_MOSI GPP_C2/SMBALERT#
SPI0_IO2

2
1

1
2
SPI_SO RC53 1 2 15_0402_5% SPI_SO_R SPI_HOLD#_R AU4 R9 SML0_CLK
44 SPI_SO SPI_CS0#_R AU3 SPI0_IO3 GPP_C3/SML0CLK W2 SML0_DATA PCH_SMB_CLK 6 1
QC2A
SPI0_CS0# GPP_C4/SML0DATA SMB_CLK_S3 18,40

S
AU2 W1 SML0_ALERT#

D
SPI_SI RC52 1 2 15_0402_5% SPI_SI_R AU1 SPI0_CS1# GPP_C5/SML0ALERT# 2N7002KDWH_SOT363-6
44 SPI_SI SPI0_CS2# PCH_SML1_CLK

5
W3

G
GPP_C6/SML1CLK V3 PCH_SML1_DAT
SPI_CS0# SPI_CS0#_R SPI - TOUCH GPP_C7/SML1DATA SML1_ALERT# GPU, EC, Thermal Sensor
RC51 1 @ 2 0_0402_5% AM7
44 SPI_CS0# M2 GPP_B23/SML1ALERT#/PCHHOT#
M3 GPP_D1/SPI1_CLK PCH_SMB_DATA QC2B 3 4
GPP_D2/SPI1_MISO SMB_DATA_S3 18,40

S
J4

D
V1 GPP_D3/SPI1_MOSI 2N7002KDWH_SOT363-6
V2 GPP_D21/SPI1_IO2
BOARD_ID4 M1 GPP_D22/SPI1_IO3 AY13
LPC
8 BOARD_ID4 GPP_D0/SPI1_CS# GPP_A1/LAD0/ESPI_IO0 BA13 LPC_AD0 32,44
GPP_A2/LAD1/ESPI_IO1 BB13 LPC_AD1 32,44
C LINK GPP_A3/LAD2/ESPI_IO2 AY12 LPC_AD2 32,44
G3 GPP_A4/LAD3/ESPI_IO3 BA12 LPC_AD3 32,44
G2 CL_CLK GPP_A5/LFRAME#/ESPI_CS# BA11 SUS_STAT# LPC_FRAME# 32,44 1
G1 CL_DATA GPP_A14/SUS_STAT#/ESPI_RESET# TC81@
CL_RST#
AW9 CLK_PCI_EC_R RC173 2 1 22_0402_5%
AW13 GPP_A9/CLKOUT_LPC0/ESPI_CLK AY9 CLK_PCI_TPM_R CLK_PCI_EC 44
KBRST# RC1541 2 TPM@ 1 22_0402_5%
44 KBRST# GPP_A0/RCIN# GPP_A10/CLKOUT_LPC1 AW11 PM_CLKRUN# CLK_PCI_TPM 32
AY11 GPP_A8/CLKRUN# PM_CLKRUN# 32
SERIRQ
32,44 SERIRQ GPP_A6/SERIRQ

1 OF 20
SKYLAKE-U_BGA1356
REV = 1
?
@

+3V_SPI
C C
+3VS +3VALW_PCH
check CLKRUN# / SUS_STAT# signal if need to connect +3VS
RC171 1 @ 2 0_0402_5% +3VALW_PCH

RC172 1 @ 2 0_0402_5%
PM_CLKRUN# RC11 1 2 8.2K_0402_5% SMB_ALERT# 2 1 RC1562
+3V_SPI 2.2K_0402_5%

1. If support DS3, connect to +3VS and don't support EC mirror code; SERIRQ RC12 1 2 10K_0402_5%

* 2. If don't support DS3, connect to +3VALW_PCH and support EC mirror code.


KBRST# RC10 1 2 10K_0402_5%
+3VALW_PCH

RPC23
SML0_CLK 4 1
KBRST# CC1255 1 2 1000P_0201_50V7-K SML0_DATA 3 2

EMC_NS@ 2.2K_0404_4P2R_5%
+3V_SPI

+3VALW_PCH
1

RC60 RC61
1K_0402_5% 1K_0402_5% SML0_ALERT# RC1564 2 @ 1 2.2K_0402_5%
Check with BIOS, SPI is Dual mode or quad mode
2

SPI_WP#_R SPI_WP#
This signal has a weak internal pull-down.
RC54 1 @ 2 15_0402_5% +3VALW_PCH +3VS 0 = LPC Is selected for EC. (Default)
1 = eSPI Is selected for EC.
SPI_HOLD#_R RC55 1 @ 2 15_0402_5% SPI_HOLD# Notes:
1. The internal pull-down is disabled after RSMRST#
de-asserts.
4
3

RPC25 2. This signal is in the primary wel


B B
Rising edge of RSMRST#

2
2.2K_0404_4P2R_5%

G
+3VALW_PCH
1
2

+3V_SPI PCH_SML1_CLK QC10A 6 1 @ SML1_ALERT# RC1569 1 @ 2 150K_0402_5% +3VS


EC_SMB_CK2 20,39,44
S
D

UC3 2N7002KDWH_SOT363-6 RC1655 1 2 150K_0402_5%


SPI_CS0#

5
1 8

G
/CS VCC
SPI_SO 2 7 SPI_HOLD#
DO (IO1) IO3 1
SPI_WP# SPI_CLK
CC8
PCH_SML1_DAT
To enable Direct Connect Interface (DCI), a 150K pull up resistor will need to be
3 6 0.1u_0201_10V6K QC10B 3 4 @ added to PCHHOT# pin. This pin must be low during the rising edge of RSMRST#.
IO2 CLK EC_SMB_DA2 20,39,44
S
D

SPI_SI 2 (Refer to WW52_MOW)


4 5 2N7002KDWH_SOT363-6
GND DI (IO0)

W25Q64JVSSIQ_SO8

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (MISC,JTAG,SPI,LPC,SMB)


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
DG421 1.0

Date: Sunday, January 22, 2017 Sheet 7 of 60


5 4 3 2 1
5 4 3 2 1

+3VS

+3VS
@DIS For NV and AMD GPU SKU @OPT&GC6 Only for NV GPU SKU @UMA SKU
+3VS RC1558 1 UMA@ 2 10K_0402_5% DGPU_PWROK

RC1559 2 DIS@ 1 10K_0402_5% PXS_PWREN_R 1K_0402_5% 2 DIS@ 1 RC7


PXS_PWREN 22,58 FB_GC6_EN_R

1 RC1615 2

1 RC1613 2

1 RC1611 2

1 RC1609 2

1 RC1606 2
RC1629 1 @ 2 10K_0402_5% @ 15@ @ DIS@ PX@ @

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
RC1641 1 @ 2 10K_0402_5% PXS_RST#_R RC8 1 @ 2 0_0402_5%

RC1608
PXS_RST# 20 GPU_EVENT#
RC1630 1 GC6@ 2 10K_0402_5%
GPU_EVENT# 20
Reserve for GPU sequence
RC1557 1 DIS@ 2 10K_0402_5% PXS_RST#_R RC1637 1 OPT@ 2 10K_0402_5% FB_GC6_EN_R
FB_GC6_EN_R 20

1
CC1259 1 2 0.01U_0201_10V6K PXS_RST# RC1638 1 @ 2 10K_0402_5% GPU_EVENT# BOARD_ID0
DIS@ BOARD_ID1
BOARD_ID2
D 9 BOARD_ID2 BOARD_ID3 D
DGPU_PWROK BOARD_ID4
DGPU_PWROK 24,55,57,58 7 BOARD_ID4 BOARD_ID5

10K_0402_5%
1 RC1616 2

1 RC1614 2

1 RC1612 2

1 RC1610 2

1 RC1607 2

1 RC123 2
14@ @ UMA@ OPT@ @

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
SKL_ ULT ?
UC1F
LPSS ISH

AN8 P2 BOARD_ID0
AP7 GPP_B15/GSPI0_CS# GPP_D9 P3 BOARD_ID1
AP8 GPP_B16/GSPI0_CLK GPP_D10 P4
RC1561 1 @ 2 2.2K_0402_5% GPP_B18 AR7 GPP_B17/GSPI0_MISO GPP_D11 P1 BOARD_ID3
+3VS +3VS GPP_B18/GSPI0_MOSI GPP_D12
AM5 M4 BOARD_ID6
RPC28 PCH_CMOS_ON# AN7 GPP_B19/GSPI1_CS# GPP_D5/ISH_I2C0_SDA N3 BOARD_ID5
1 4 PCH_I2C_SDA0 33 PCH_CMOS_ON# AP5 GPP_B20/GSPI1_CLK GPP_D6/ISH_I2C0_SCL
2 3 PCH_I2C_SCL0 RC1563 1 @ 2 2.2K_0402_5% GPP_B22 AN5 GPP_B21/GSPI1_MISO N1 BOARD_ID7 Board ID Description Stuff R
GPP_B22/GSPI1_MOSI GPP_D7/ISH_I2C1_SDA N2 BOARD_ID8
2.2K_0404_4P2R_5% AB1 GPP_D8/ISH_I2C1_SCL 00 14" RC1616 RC1614
40 UART_RX_DEBUG AB2 GPP_C8/UART0_RXD AD11
Board_ID[0:1] 01 15" RC1616 RC1613
PCH_TP_INT# 40 UART_TX_DEBUG GPP_C9/UART0_TXD GPP_F10/I2C5_SDA/ISH_I2C2_SDA
RC1658 2 1 10K_0402_5% W4 AD12
AB3 GPP_C10/UART0_RTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL
GPP_C11/UART0_CTS# 10 17" RC1615 RC1614
10/ 25 SIT For I2C T/ P Function wei TC206 1 @ PXS_PWREN_R AD1 U1
TC207 1 @ PXS_RST#_R AD2 GPP_C20/UART2_RXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA U2 11 Reserved RC1615 RC1613
+3VS TC208 1 @ DGPU_PWROK AD3 GPP_C21/UART2_TXD GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL U3
1 FB_GC6_EN_R AD4 GPP_C22/UART2_RTS# GPP_D15/ISH_UART0_RTS# U4 0 Reserved RC1612
TC204 @
GPP_C23/UART2_CTS# GPP_D16/ISH_UART0_CTS#/SML0BALERT#
Board_ID2
AC1 1 Reserved RC1611
RC1656 1 @ 2 0_0402_5% PCH_I2C_SDA0 U7 GPP_C12/UART1_RXD/ISH_UART1_RXD AC2
45 TP_I2C_SDA0
RC1657 1 2 0_0402_5% PCH_I2C_SCL0 U6 GPP_C16/I2C0_SDA GPP_C13/UART1_TXD/ISH_UART1_TXD AC3 GPU_EVENT# @1 0 UMA RC1610
PCH_CMOS_ON# 45 TP_I2C_SCL0
@
GPP_C17/I2C0_SCL GPP_C14/UART1_RTS#/ISH_UART1_RTS#
TC205 Board_ID3
RC1595 2 @ 1 10K_0402_5% AB4
RC1596 2 1 10K_0402_5% PCH_WLAN_OFF# PCH_WLAN_OFF# U8 GPP_C15/UART1_CTS#/ISH_UART1_CTS# PCH_TP_INT# 45 1 DIS RC1609
PCH_BT_OFF# 40 PCH_WLAN_OFF# PCH_BT_OFF# GPP_C18/I2C1_SDA
C RC1597 2 1 10K_0402_5% U9 AY8 C
40 PCH_BT_OFF# GPP_C19/I2C1_SCL GPP_A18/ISH_GP0 BA8 0 NV GPU RC1607
GPP_A19/ISH_GP1
Board_ID4
double check if need the pull up resisor AH9 BB7
AH10 GPP_F4/I2C2_SDA GPP_A20/ISH_GP2 BA7 1 AMD GPU RC1608
GPP_F5/I2C2_SCL GPP_A21/ISH_GP3 AY7
AH11 GPP_A22/ISH_GP4 AW7 0 Reserved RC123
GPP_F6/I2C3_SDA GPP_A23/ISH_GP5
Board_ID5
AH12 AP13
GPP_F7/I2C3_SCL GPP_A12/BM_BUSY#/ISH_GP6 1 Reserved RC1606
+3VALW_PCH +3VS AF11
AF12 GPP_F8/I2C4_SDA
RC1600 1 @ 2 1K_0402_5% GPP_F9/I2C4_SCL +3VS

RC47 1 @ 2 1K_0402_5% HDA_SDOUT SKYLAKE-U_BGA1356 1 OF 20

* REV = 1
@
?
DIMM_ONLY@ DIMM_ONLY@ 520Z@ @ @
HDA_SDO This signal has a weak internal pull-down.

2 RC1631 1

2 RC1632 1

2 RC1633 1

2 RC1639 1

2 RC1651 1
10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
0 = Enable security measures defined in the Flash Descriptor.
1 = Disable Flash Descriptor Security(override). This strap
should only be asserted high during external pull-up in
manufacturing/debug environments ONLY.
BOARD_ID6
BOARD_ID7
BOARD_ID8
BOARD_ID9
BOARD_ID10
UC1G SKL_ ULT ?
@ @ 320G@ @ @
AUDIO
HDA_SDIN0

2 RC1634 1

2 RC1635 1

2 RC1636 1

2 RC1640 1

2 RC1652 1
For EMI

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
RC43 1 2 33_0402_5% HDA_SYNC BA22
1 30 HDA_SYNC_AUDIO HDA_BCLK HDA_SYNC/I2S0_SFRM
CC7 RC42 1 2 33_0402_5% AY22
10P_0201_50V8F 30 HDA_BITCLK_AUDIO HDA_SDOUT BB22 HDA_BLK/I2S0_SCLK
SDIO/SDXC
EMC_NS@ HDA_SDIN0 BA21 HDA_SDO/I2S0_TXD
2 30 HDA_SDIN0 AY21 HDA_SDI0/I2S0_RXD AB11
RC44 1 2 33_0402_5% HDA_RST# AW22 HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD AB13
30 HDA_RST_AUDIO# J5 HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0 AB12
B
AY20 GPP_D23/I2S_MCLK GPP_G2/SD_DATA1 W12 B

AW20 I2S1_SFRM GPP_G3/SD_DATA2 W11


I2S1_TXD GPP_G4/SD_DATA3 W10
AK7 GPP_G5/SD_CD# W8
AK6 GPP_F1/I2S2_SFRM GPP_G6/SD_CLK W7
AK9 GPP_F0/I2S2_SCLK GPP_G7/SD_WP
AK10 GPP_F2/I2S2_TXD BA9
HDA_SDOUT GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7
Board ID Description Stuff R
RC45 1 2 33_0402_5% BB9
30 HDA_SDOUT_AUDIO GPP_A16/SD_1P8_SEL
RC46 1 @ 2 0_0402_5% Samsung 8Gb
44 ME_FLASH BOARD_ID10 H5 AB7 SD_RCOMP
BOARD_ID9 GPP_D19/DMIC_CLK0 SD_RCOMP
00 2400 MT/s RC1634 RC1635
D7
GPP_D20/DMIC_DATA0
Hynix 8Gb

1
D8 AF13 01 2400 MT/s RC1634 RC1632
C8 GPP_D17/DMIC_CLK1 GPP_F23
GPP_D18/DMIC_DATA1
RC49 Board_ID
PCH_BEEP
200_0402_1% [6,7] Micron 8Gb
+3VS AW5 10 2400 MT/s RC1631 RC1635
30 PCH_BEEP GPP_B14/SPKR

2
1 2 2.2K_0402_5% PCH_BEEP
RC14 @
1 OF 20
11 SO-DIMM Only RC1631 RC1632
SKYLAKE-U_BGA1356
REV = 1 ?
@ 0 320G RC1636
Board_ID8
Default When 1 520Z RC1633
Pin Name Strap Description Configuration Value Sampled
Internal PD 0 Reserved RC1640
0 = Disable “ Top Swap” Board_ID9
SPKR /
GPP_B14
Top Swap
Override
mode. (Default)
1 = Enable “ Top Swap”
* 0 Rising edge
of PCH_PWROK 1 Reserved RC1639
mode.
Internal PD 0 Reserved RC1652
GSPI0_MOSI 0 = Disable “ No Reboot” Rising edge Board_ID10
/GPP_B18 No Reboot mode. (Default)
1 = Enable “ No Reboot”
* 0 of PCH_PWROK
1 Reserved RC1651
A A
mode

GSPI1_MOSIBoot BIOS Internal PD Rising edge


/GPP_B22 Strap Bit
BBS
0 = SPI (Default)
1 = LPC
* 0 of PCH_PWROK

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (LPSS,ISH,AUDIO,SDIO)


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
DG421 1.0

Date: Sunday, January 22, 2017 Sheet 8 of 60


5 4 3 2 1
5 4 3 2 1

@DIS For NV and AMD GPU SKU


20 PCIE_CRX_GTX_N[0..3]
D D
20 PCIE_CRX_GTX_P[0..3]
?
UC1H SKL_ULT
20 PCIE_CTX_C_GRX_N[0..3]

20 PCIE_CTX_C_GRX_P[0..3] SSIC / USB3


PCIE/USB3/SATA
H8 USB30_RX_N1
USB3_1_RXN USB30_RX_P1 USB30_RX_N1 41
G8
PCIE_CRX_GTX_N0 H13
PCIE1_RXN/USB3_5_RXN
USB3_1_RXP
USB3_1_TXN
C13 USB30_TX_N1 USB30_RX_P1
USB30_TX_N1
41
41
LEFT USB3.0
PCIE_CRX_GTX_P0 G13 D13 USB30_TX_P1
PCIE_CTX_C_GRX_N0 PCIE_CTX_GRX_N0 PCIE1_RXP/USB3_5_RXP USB3_1_TXP USB30_TX_P1 41
0.22U_0201_6.3V6-K DIS@ 1 2 CC16 B17
PCIE_CTX_C_GRX_P0 0.22U_0201_6.3V6-K DIS@ 1 2 CC14 PCIE_CTX_GRX_P0 A17 PCIE1_TXN/USB3_5_TXN J6 USB30_RX_N2
PCIE1_TXP/USB3_5_TXP USB3_2_RXN/SSIC_1_RXN USB30_RX_P2 USB30_RX_N2 43
H6
PCIE_CRX_GTX_N1 USB3_2_RXP/SSIC_1_RXP USB30_TX_N2 USB30_RX_P2 43
G11 B13
PCIE_CRX_GTX_P1 F11 PCIE2_RXN/USB3_6_RXN
PCIE2_RXP/USB3_6_RXP
USB3_2_TXN/SSIC_1_TXN
USB3_2_TXP/SSIC_1_TXP
A13 USB30_TX_P2 USB30_TX_N2
USB30_TX_P2
43
43
Type-C
PCIE_CTX_C_GRX_N1 0.22U_0201_6.3V6-K DIS@ 1 2 CC15 PCIE_CTX_GRX_N1 D16
PCIE_CTX_C_GRX_P1 0.22U_0201_6.3V6-K DIS@ 1 2 CC17 PCIE_CTX_GRX_P1 C16 PCIE2_TXN/USB3_6_TXN J10 USB30_RX_N3
PCIE2_TXP/USB3_6_TXP USB3_3_RXN/SSIC_2_RXN USB30_RX_P3 USB30_RX_N3 41
H10
DGPU PCIE_CRX_GTX_N2 H16 USB3_3_RXP/SSIC_2_RXP B15 USB30_TX_N3 USB30_RX_P3 41
PCIE_CRX_GTX_P2 G16 PCIE3_RXN
PCIE3_RXP
USB3_3_TXN/SSIC_2_TXN
USB3_3_TXP/SSIC_2_TXP
A15 USB30_TX_P3 USB30_TX_N3
USB30_TX_P3
41
41
LEFT USB3.0
PCIE_CTX_C_GRX_N2 0.22U_0201_6.3V6-K DIS@ 1 2 CC18 PCIE_CTX_GRX_N2 D17
PCIE_CTX_C_GRX_P2 0.22U_0201_6.3V6-K DIS@ 1 2 CC19 PCIE_CTX_GRX_P2 C17 PCIE3_TXN E10
PCIE3_TXP USB3_4_RXN F10
PCIE_CRX_GTX_N3 G15 USB3_4_RXP C15
PCIE_CRX_GTX_P3 F15 PCIE4_RXN USB3_4_TXN D15
PCIE_CTX_C_GRX_N3 0.22U_0201_6.3V6-K DIS@ 1 2 CC20 PCIE_CTX_GRX_N3 B19 PCIE4_RXP USB3_4_TXP
PCIE_CTX_C_GRX_P3 0.22U_0201_6.3V6-K DIS@ 1 2 CC21 PCIE_CTX_GRX_P3 A19 PCIE4_TXN AB9 USB20_N1
PCIE4_TXP USB2N_1 USB20_P1 USB20_N1 41
AB10
37 PCIE_PRX_DTX_N5
PCIE_PRX_DTX_N5 F16
PCIE5_RXN
USB2P_1 USB20_P1 41 LEFT USB3.0
PCIE_PRX_DTX_P5 E16 AD6 USB20_N2
37 PCIE_PRX_DTX_P5 PCIE_PTX_DRX_N5 PCIE5_RXP USB2N_2 USB20_P2 USB20_N2 43
CC1262 1 2 0.1u_0201_10V6K C19 AD7
LAN 37
37
PCIE_PTX_C_DRX_N5
PCIE_PTX_C_DRX_P5
CC1261 1 2 0.1u_0201_10V6K PCIE_PTX_DRX_P5 D19 PCIE5_TXN USB2P_2 USB20_P2 43 Type-C
C PCIE5_TXP AH3 USB20_N3 C
PCIE_PRX_DTX_N6 USB2N_3 USB20_P3 USB20_N3 41
G18 AJ3
40
40
PCIE_PRX_DTX_N6
PCIE_PRX_DTX_P6
PCIE_PRX_DTX_P6 F18 PCIE6_RXN
PCIE6_RXP
USB2P_3 USB20_P3 41 LEFT USB3.0
CC1264 1 2 0.1u_0201_10V6K PCIE_PTX_DRX_N6 D20 AD9 USB20_N4
WLAN 40 PCIE_PTX_C_DRX_N6
CC1263 1 2 0.1u_0201_10V6K PCIE_PTX_DRX_P6 C20 PCIE6_TXN USB2N_4 AD10 USB20_P4 USB20_N4 45
40 PCIE_PTX_C_DRX_P6 PCIE6_TXP USB2P_4 USB20_P4 45 Finger Print
SATA_PRX_DTX_N0 F20 AJ1 USB20_N5
42 SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 PCIE7_RXN/SATA0_RXN USB2N_5 USB20_P5 USB20_N5 30
E20 AJ2
42 SATA_PRX_DTX_P0 SATA_PTX_DRX_N0 B21 PCIE7_RXP/SATA0_RXP USB2P_5 USB20_P5 30 Card reader
SATA HDD 42 SATA_PTX_DRX_N0 SATA_PTX_DRX_P0 A21 PCIE7_TXN/SATA0_TXN
PCIE7_TXP/SATA0_TXP
USB2

USB2N_6
AF6 USB20_N6
USB20_N6 33
42 SATA_PTX_DRX_P0 AF7 USB20_P6
SATA_PRX_DTX_N1 G21
PCIE8_RXN/SATA1A_RXN
USB2P_6 USB20_P6 33 Touch panel
42 SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 F21 AH1 USB20_N7
42 SATA_PRX_DTX_P1 SATA_PTX_DRX_N1 PCIE8_RXP/SATA1A_RXP USB2N_7 USB20_P7 USB20_N7 40
D21 AH2
SATA ODD 42 SATA_PTX_DRX_N1 SATA_PTX_DRX_P1 C21 PCIE8_TXN/SATA1A_TXN
PCIE8_TXP/SATA1A_TXP
USB2P_7 USB20_P7 40 BT
42 SATA_PTX_DRX_P1 AF8 USB20_N8
USB2N_8 USB20_P8 USB20_N8 33
E22 AF9
E23 PCIE9_RXN
PCIE9_RXP
USB2P_8 USB20_P8 33 Camera
B23 AG1
A23 PCIE9_TXN USB2N_9 AG2
PCIE9_TXP USB2P_9
F25 AH7
E25 PCIE10_RXN USB2N_10 AH8
D23 PCIE10_RXP USB2P_10
C23 PCIE10_TXN AB6 USB2_COMP RC118 2 1 113_0402_1%
PCIE10_TXP USB2_COMP
USBRBIAS
AG3 USB2_ID RC1626 1 @ 2 0_0402_5% Width 20Mil
RC119 1 2 100_0402_1% PCIE_RCOMPN F5 USB2_ID AG4 USB2_VBUSSENSE RC1627 1 2 1K_0402_5%
PCIE_RCOMPP PCIE_RCOMPN USB2_VBUSSENSE Space 15Mil
E5 Length 500Mil
PCIE_RCOMPP A9 USB_OC0#
Optane Memory PCIE_RCOMPN and PCIE_RCOMPP PAD @ TC20 1 XDP_PRDY# D56
PROC_PRDY#
GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
C9 USB_OC1#
USB_OC1# 41
Trace Width: 12-15mil PAD @ TC19 1 XDP_PREQ# D61 D9 USB_OC2#
Differential between RCOMPP/RCOMPN
PIRQA# BB11 PROC_PREQ# GPP_E11/USB2_OC2# B9 USB_OC3#
B GPP_A7/PIRQA# GPP_E12/USB2_OC3# B
E28 J1 GPP_E4 RC1628 1 @ 2 0_0402_5%
PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0 GPP_E5 EC_SMI# 44
E27 J2 1
D24 PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1 J3 @ PAD TC202
C24 PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2
E30 PCIE11_TXP/SATA1B_TXP H2
2016/05/03: Implement as Power Button
SATA0GP
F30 PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0 H3 ODD_DETECT# function for Windows RedStone support
A25 PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1 G4 SATA2GP
B25 PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCIE2/SATAGP2
PCIE12_TXP/SATA2_TXP H1 BOARD_ID2
GPP_E8/SATALED# BOARD_ID2 8

SKYLAKE-U_BGA1356 1 OF 20
REV = 1 ?
@

+3VS

+3VALW_PCH

+3VS GPP_E4 RC1617 2 @ 1 10K_0402_5%


RPC2 RPC17
1 8 ODD_DETECT# USB_OC0# 8 1
2 7 SATA0GP USB_OC1# 7 2
3 6 SATA2GP USB_OC3# 6 3
4 5 PIRQA# USB_OC2# 5 4 USB_OC2# RC1654 1 @ 2 0_0402_5%
TYPE_C_OCP# 43
10K_0804_8P4R_5% 10K_0804_8P4R_5%
8/ 24 Reserve TYPE_C_OCP# to CPU USB_OC2# wei
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (PCIE,SATA,USB3,USB2)


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG421
Date: Sunday, January 22, 2017 Sheet 9 of 60
5 4 3 2 1
5 4 3 2 1

UC1I
SKL_ULT ?

CSI-2

A36 C37
B36 CSI2_DN0 CSI2_CLKN0 D37
C38 CSI2_DP0 CSI2_CLKP0 C32
D38 CSI2_DN1 CSI2_CLKN1 D32
C36 CSI2_DP1 CSI2_CLKP1 C29
D D36 CSI2_DN2 CSI2_CLKN2 D29 D
A38 CSI2_DP2 CSI2_CLKP2 B26
check the Pull up resistor CSI2_DN3 CSI2_CLKN3
B38 A26
CSI2_DP3 CSI2_CLKP3
+3VS C31 E13 CSI2_COMP RC73 1 2 100_0402_1%
D31 CSI2_DN4 CSI2_COMP B7
C33 CSI2_DP4 GPP_D4/FLASHTRIG
RPC4 D33 CSI2_DN5
1 8 LAN_CLKREQ# A31 CSI2_DP5 EMMC

2 7 WLAN_CLKREQ# B31 CSI2_DN6 AP2


3 6 A33 CSI2_DP6 GPP_F13/EMMC_DATA0 AP1
4 5 GPU_CLKREQ# B33 CSI2_DN7 GPP_F14/EMMC_DATA1 AP3
CSI2_DP7 GPP_F15/EMMC_DATA2 AN3
10K_0804_8P4R_5% A29 GPP_F16/EMMC_DATA3 AN1
B29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN2
C28 CSI2_DP8 GPP_F18/EMMC_DATA5 AM4
D28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM1
A27 CSI2_DP9 GPP_F20/EMMC_DATA7
B27 CSI2_DN10 AM2
C27 CSI2_DP10 GPP_F21/EMMC_RCLK AM3
D27 CSI2_DN11 GPP_F22/EMMC_CLK AP4
CSI2_DP11 GPP_F12/EMMC_CMD
AT1 EMMC_RCOMP RC50 1 2 200_0402_1%
EMMC_RCOMP
SKYLAKE-U_BGA1356 1 OF 20
REV = 1 ?
@

@DIS For NV and AMD GPU SKU UC1J SKL_ULT ?


SUSCLK RC95 1 @ 2 1K_0402_5%
C CLOCK SIGNALS C

CLK_PCIE_GPU# D42 DIFFCLK_BIASREF RC1555 1 2 60.4_0402_1%


20 CLK_PCIE_GPU# CLK_PCIE_GPU CLKOUT_PCIE_N0
PCIE CLK0 DGPU C42 Cannonlake@
20 CLK_PCIE_GPU GPU_CLKREQ# CLKOUT_PCIE_P0
AR10
20 GPU_CLKREQ# GPP_B5/SRCCLKREQ0#
B42
A42 CLKOUT_PCIE_N1 F43 CLK_PCIE_XDP# 1 TC85 @
Optane memory CLKOUT_PCIE_P1 CLKOUT_ITPXDP_N CLK_PCIE_XDP
AT7 E43 1 TC87 @
GPP_B6/SRCCLKREQ1# CLKOUT_ITPXDP_P
CLK_PCIE_WLAN# D41 BA17 SUSCLK
40 CLK_PCIE_WLAN# CLK_PCIE_WLAN CLKOUT_PCIE_N2 GPD8/SUSCLK SUSCLK 40
PCIE CLK5 WLAN C41
40 CLK_PCIE_WLAN WLAN_CLKREQ# CLKOUT_PCIE_P2 XTAL24_IN
AT8 E37
40 WLAN_CLKREQ# GPP_B7/SRCCLKREQ2# XTAL24_IN XTAL24_OUT
E35 +VCCCLK5
D40 XTAL24_OUT
C40 CLKOUT_PCIE_N3 E42 DIFFCLK_BIASREF RC72 1 2 2.7K_0402_1%
AT10 CLKOUT_PCIE_P3 XCLK_BIASREF
GPP_B8/SRCCLKREQ3# AM18 RTC_X1
CLK_PCIE_LAN# B40 RTCX1 AM20 RTC_X2
37 CLK_PCIE_LAN# CLK_PCIE_LAN CLKOUT_PCIE_N4 RTCX2
PCIE CLK4 LAN A40
37 CLK_PCIE_LAN LAN_CLKREQ# CLKOUT_PCIE_P4 SRTC_RST#
AU8 AN18
37 LAN_CLKREQ# GPP_B9/SRCCLKREQ4# SRTCRST# RTC_RST#
AM16
E40 RTCRST#
E38 CLKOUT_PCIE_N5
AU7 CLKOUT_PCIE_P5
GPP_B10/SRCCLKREQ5#

1 OF 20 1
SKYLAKE-U_BGA1356 CC3
REV = 1 ? VCCRTC 1U_0402_6.3V6K
@
B 2 B
RC33 1 2 20K_0402_1% SRTC_RST#
RC34 1 2 20K_0402_1% RTC_RST# RC1624 1 @ 2 0_0402_5%
EC_RTC_RST# 44

1
CC6 JCMOS1
1U_0402_6.3V6K SHORT PADS
@
2

2
RC71 2 1 1M_0402_5% RTC_X1

YC2
RC32 2 1 10M_0402_5% RTC_X2
2 3 RC240 1 2 0_0201_5% XTAL24_OUT
GND1 OSC2 YC1
XTAL24_IN RC241 1 2 0_0201_5% 1 4 1 2
OSC1 GND2
2 32.768KHZ_9PF_X1A0001410002 2
1 24MHZ_6PF_7V24000032 1
CC12 CC11 CC4 CC5
3.3P_0402_50V8-C 2.7P_0402_50V9-B 7P_0402_50V8J 7P_0402_50V8J
1 1
2 2
when single end external clock generator used,
this pin should be grounded

need to use 38.4MHz (30ohm) for Cannonlake-u


A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (CSI2,EMMC,CLOCK)


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG421
Date: Sunday, January 22, 2017 Sheet 10 of 60
5 4 3 2 1
5 4 3 2 1

?
UC1K SKL_ULT

SYSTEM POWER MANAGEMENT


AT11
GPP_B12/SLP_S0# AP15 PM_SLP_S3#_R RC96 1 @ 2 0_0402_5%
PLT_RST#_R GPD4/SLP_S3# PM_SLP_S4#_R PM_SLP_S3# 13,44
RC84 1 @ 2 0_0402_5% AN10 BA16 RC97 1 @ 2 0_0402_5%
20,32,37,40,44 PLT_RST# SYS_RESET# GPP_B13/PLTRST# GPD5/SLP_S4# PM_SLP_S4# 44
B5 AY16
D RC85 1 @ 2 0_0402_5% PCH_RSMRST#_R AY17 SYS_RESET# GPD10/SLP_S5# D
44 EC_RSMRST# RSMRST# PM_SLP_SUS#_R
PAD @ TC21 AN15 RC89 1 @ 2 0_0402_5%
CPU_PROCPWRGD SLP_SUS# PM_SLP_SUS# 44
1 A68 AW15
VCCST_PWRGD_R RC93 1 2 60.4_0402_1% VCCST_PWRGD B65 PROCPWRGD SLP_LAN# BB17 Reserve for DS3
VCCST_PWRGD GPD9/SLP_WLAN# AN16
RC139 1 @ 2 0_0402_5% SYS_PWROK_R B6 GPD6/SLP_A#
44 SYS_PWROK PCH_PWROK_R SYS_PWROK PBTN_OUT#_R
RC126 1 @ 2 0_0402_5% BA20 BA15 RC87 1 @ 2 0_0402_5%
44 PCH_PWROK PCH_DPWROK_R PCH_PWROK GPD3/PWRBTN# AC_PRESENT_R PBTN_OUT# 44
BB20 AY15
DSW_PWROK GPD1/ACPRESENT AU13 BATLOW#
RC86 1 @ 2 0_0402_5% SUSWARN#_R AR13 GPD0/BATLOW#
44 SUSWARN# SUSACK#_R GPP_A13/SUSWARN#/SUSPWRDNACK
RC79 1 @ 2 0_0402_5% AP11 VCCRTC
44 SUSACK# GPP_A15/SUSACK#
Reserve for DS3 AU11 PME# @1 TC89
RC91 1 @ 2 0_0402_5% WAKE# BB15 GPP_A11/PME# AP16 INTVRMEN RC41 2 1 330K_0402_5%
37,40,44 PCIE_WAKE# PCH_LAN_WAKE# AM15 WAKE# INTRUDER#
AW17 GPD2/LAN_WAKE# AM10
AT15 GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# AM11
GPD7/RSVD GPP_B2/VRALERT#

SKYLAKE-U_BGA1356 1 OF 20
REV = 1 ?
@

RC88 1 @ 2 0_0402_5% AC_PRESENT_R


44 AC_PRESENT
+3VALW

AC_PRESENT_R

1
RC74 1 2 10K_0402_5% D
2 QC8
44 ACIN#
RC75 1 2 8.2K_0402_5% BATLOW# G 2N7002KW_SOT323-3
C @ C
RC76 2 1 1K_0402_5% WAKE# Follow CRB change to 1kohm S

3
RC90 1 2 10K_0402_5% PCH_LAN_WAKE#

+3VALW_PCH +3VALW +VCCST_CPU +VCCSTG

SUSWARN#_R

2
RC78 1 @ 2 10K_0402_5%

2
RC137 RC1554
RC136 1K_0402_5% 1K_0402_5%
10K_0402_5% @
+3VS @

1
VCCST_PWRGD_R

1
RC80 1 2 10K_0402_5% SYS_RESET#

3
D

6
D 5 QC6B 2
RC138 1 @ 2 0_0402_5% 2 QC6A G 2N7002KDWH_SOT363-6 CC140
44 EC_VCCST_PWRGD G 2N7002KDWH_SOT363-6 @ 1000P_0201_50V7-K
@ S EMC_NS@
1 1

4
1000P_0201_50V7-K 1 2 CC1254 PCH_RSMRST#_R CC46 S

1
EMC_NS@ 0.01U_0201_25V6-K
Stuff to fix Reset&PWRGD test fail issue EMC_NS@
0.01U_0201_10V6K 1 2 CC104 PCH_PWROK 2

1000P_0201_50V7-K 1 2 CC103 PCH_DPWROK_R


EMC_NS@
B B
47P_0201_25V8-J 1 2 CC101 SYS_PWROK

0.01U_0201_10V6K 1 2 CC1260 EC_RSMRST#


RC1599 1 @ 2 0_0402_5%

Add to fix Reset&PWRGD test fail issue


PM_SLP_S3# DC4 1 2 @

RPC21 RB751V-40_SOD323-2
1 8 PCH_RSMRST#_R
2 7 PCH_PWROK
3 6 SYS_PWROK
4 5

10K_0804_8P4R_5%
RC182 1 @ 2 0_0402_5% EC_RSMRST#

PCH_DPWROK_R RC81 1 @ 2 0_0402_5% DPWROK_EC 44


100K_0402_5% 2 1 RC92 PLT_RST#_R Reserve for DS3

100K_0402_1% 2 @ 1 RC94 PCH_DPWROK_R

A A
100P_0201_25V8J 1 2 CC1294 PLT_RST#

10/ 25 SIT Add to fix PLT_RST# glitch issue wei Title


Security Classification LC Future Center Secret Data
Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (SYSTEM PWR MANAGEMENT)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG421
Date: Sunday, January 22, 2017 Sheet 11 of 60
5 4 3 2 1
5 4 3 2 1

+CPU_CORE ? +CPU_CORE +CPU_CORE +VCC_GT +VCC_GT


SKL_ULT SKL_ULT ?
UC1L +VCC_GT UC1M
CPU POWER 1 OF 4 VCORE_VCC_SEN VCCGT_VCC_SEN
RC77 1 2 100_0402_1% RC83 1 2 100_0402_1% CPU POWER 2 OF 4
32000mA A30 G32 N70
A34 VCC_A30 VCC_G32 G33 31000mA A48 VCCGT_N70 N71
A39 VCC_A34 VCC_G33 G35 VCORE_VSS_SEN RC82 1 2 100_0402_1% VCCGT_VSS_SEN RC98 1 2 100_0402_1% A53 VCCGT_A48 VCCGT_N71 R63
A44 VCC_A39 VCC_G35 G37 A58 VCCGT_A53 VCCGT_R63 R64
AK33 VCC_A44 VCC_G37 G38 A62 VCCGT_A58 VCCGT_R64 R65
AK35 VCC_AK33 VCC_G38 G40 A66 VCCGT_A62 VCCGT_R65 R66
AK37 VCC_AK35 VCC_G40 G42 AA63 VCCGT_A66 VCCGT_R66 R67
AK38 VCC_AK37 VCC_G42 J30 AA64 VCCGT_AA63 VCCGT_R67 R68
AK40 VCC_AK38 VCC_J30 J33 AA66 VCCGT_AA64 VCCGT_R68 R69
AL33 VCC_AK40 VCC_J33 J37 AA67 VCCGT_AA66 VCCGT_R69 R70
AL37 VCC_AL33 VCC_J37 J40 AA69 VCCGT_AA67 VCCGT_R70 R71
AL40 VCC_AL37 VCC_J40 K33 AA70 VCCGT_AA69 VCCGT_R71 T62
D VCC_AL40 VCC_K33 VCCGT_AA70 VCCGT_T62 D
AM32 K35 SVID +VCCST_CPU AA71 U65
AM33 VCC_AM32 VCC_K35 K37 AC64 VCCGT_AA71 VCCGT_U65 U68
AM35 VCC_AM33 VCC_K37 K38 AC65 VCCGT_AC64 VCCGT_U68 U71
AM37 VCC_AM35 VCC_K38 K40 AC66 VCCGT_AC65 VCCGT_U71 W63
AM38 VCC_AM37 VCC_K40 K42 AC67 VCCGT_AC66 VCCGT_W63 W64
G30 VCC_AM38 VCC_K42 K43 AC68 VCCGT_AC67 VCCGT_W64 W65
VCC_G30 VCC_K43 AC69 VCCGT_AC68 VCCGT_W65 W66
VCORE_VCC_SEN 1 VCCGT_AC69 VCCGT_W66
@ TC90 1 K32 E32 CC42 AC70 W67
RSVD_K32 VCC_SENSE E33 VCORE_VSS_SEN VCORE_VCC_SEN 59 0.1u_0201_10V6K AC71 VCCGT_AC70 VCCGT_W67 W68
VSS_SENSE VCORE_VSS_SEN 59 VCCGT_AC71 VCCGT_W68

1
AK32 J43 W69

56_0402_5%

100_0402_1%

100_0402_1%
@
RSVD_AK32 B63 CPU_SVID_ALERT#_R 2 J45 VCCGT_J43 VCCGT_W69 W70

RC131

RC1544

RC132
AB62 VIDALERT# A63 CPU_SVID_CLK_R J46 VCCGT_J45 VCCGT_W70 W71
P62 VCCOPC_AB62 VIDSCK D64 CPU_SVID_DAT_R J48 VCCGT_J46 VCCGT_W71 Y62
@ TC92 1 +VCCOPC_1.0V V62 VCCOPC_P62 VIDSOUT J50 VCCGT_J48 VCCGT_Y62 +VCC_GT
VCCOPC_V62 VCCGT_J50

2
G20 J52
VCCSTG_G20 +VCCSTG VCCGT_J52
H63 @ J53 AK42
VCC_OPC_1P8_H63 J55 VCCGT_J53 VCCGTX_AK42 AK43
@ TC94 1 +V1.8S_EDRAM G61 J56 VCCGT_J55 VCCGTX_AK43 AK45
VCC_OPC_1P8_G61 1 2 220_0402_1% CPU_SVID_ALERT#_R J58 VCCGT_J56 VCCGTX_AK45 AK46
@ TC95 1 VCCOPC_SENSE AC63
59 VR_SVID_ALRT# RC133
J60 VCCGT_J58 VCCGTX_AK46 AK48 For UMA 2+3e
@ TC97 1 VSSOPC_SENSE AE63 VCCOPC_SENSE K48 VCCGT_J60 VCCGTX_AK48 AK50
VSSOPC_SENSE RC134 1 @ 2 0_0402_5% CPU_SVID_CLK_R K50 VCCGT_K48 VCCGTX_AK50 AK52
AE62 59 VR_SVID_CLK K52 VCCGT_K50 VCCGTX_AK52 AK53
@ TC99 1 +VCCEOPIO AG62 VCCEOPIO_AE62 K53 VCCGT_K52 VCCGTX_AK53 AK55
VCCEOPIO_AG62 RC1545 1 @ 2 0_0402_5% CPU_SVID_DAT_R K55 VCCGT_K53 VCCGTX_AK55 AK56
1 VCCEOPIO_SENSE AL63 59 VR_SVID_DAT K56 VCCGT_K55 VCCGTX_AK56 AK58
@ TC100
1 VSSEOPIO_SENSE AJ62 VCCEOPIO_SENSE K58 VCCGT_K56 VCCGTX_AK58 AK60
@ TC101
VSSEOPIO_SENSE
1, Alert# Route Between CLK and Data VCCGT_K58 VCCGTX_AK60
K60 AK70
L62 VCCGT_K60 VCCGTX_AK70 AL43
For UMA 2+3e SKYLAKE-U_BGA1356 1 OF 20 L63 VCCGT_L62 VCCGTX_AL43 AL46
REV = 1 ? L64 VCCGT_L63 VCCGTX_AL46 AL50
@ L65 VCCGT_L64 VCCGTX_AL50 AL53
L66 VCCGT_L65 VCCGTX_AL53 AL56
L67 VCCGT_L66 VCCGTX_AL56 AL60
L68 VCCGT_L67 VCCGTX_AL60 AM48
+CPU_CORE L69 VCCGT_L68 VCCGTX_AM48 AM50
L70 VCCGT_L69 VCCGTX_AM50 AM52
C +VCC_GT Backside Cap 8x10uF 0402, SIT update VCCGT_L70 VCCGTX_AM52 C
13x10uF 0402, SIT update to 0603 package L71 AM53
M62 VCCGT_L71 VCCGTX_AM53 AM56
N63 VCCGT_M62 VCCGTX_AM56 AM58
N64 VCCGT_N63 VCCGTX_AM58 AU58
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
N66 VCCGT_N64 VCCGTX_AU58 AU63
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VCCGT_N66 VCCGTX_AU63
N67 BB57
CC1086

CC1085

CC1080

CC1236

CC1237

CC1093

CC1092

CC1091

CC1089

CC1238

CC1122

CC1123

CC1124

CC1125

CC1126

CC1127

CC1128

CC1129
N69 VCCGT_N67 VCCGTX_BB57 BB66
VCCGT_N69 VCCGTX_BB66
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 VCCGT_VCC_SEN J70 AK62 VCCGTX_SENSE 1 TC133 @
59 VCCGT_VCC_SEN VCCGT_VSS_SEN J69 VCCGT_SENSE VCCGTX_SENSE AL61 VSSGTX_SENSE 1 TC134 @
59 VCCGT_VSS_SEN VSSGT_SENSE VSSGTX_SENSE
@ CD@ @ @ @ @ CD@ CD@

SKYLAKE-U_BGA1356 1 OF 20
REV = 1 ?
@

+CPU_CORE +VCC_GT
15x1uF 0201, SIT update to 0402 package Backside Cap 12x1uF 0201, SIT update
1U_0201_6.3V6-M

1U_0201_6.3V6-M
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CC1095

CC1096

CC1097

CC1098

CC1099

CC1100

CC1101

CC1102

CC1104

CC1105

CC1108

CC1109

CC1111

CC1114

CC1115

CC1116

CC1118

CC1119

CC1240

CC1241
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

@ @

B B

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (CPU PWR1)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
DG421 1.0

Date: Sunday, January 22, 2017 Sheet 12 of 60


5 4 3 2 1
5 4 3 2 1

+VCCIO
3.1A 2x10uF, 4x1uF

10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1
+VCCIO

CC1152

CC1153

CC1158

CC1159

CC1160

CC1161

CC1218

CC1230

CC1231

CC1232
?
+1.2V UC1N SKL_ULT

CPU POWER 3 OF 4 2 2 2 2 2 2 2 2 2 2
2800mA AU23 AK28 3100mA
AU28 VDDQ_AU23 VCCIO_AK28 AK30
AU35 VDDQ_AU28 VCCIO_AK30 AL30 @ @ @ @ @
AU42 VDDQ_AU35 VCCIO_AL30 AL42
BB23 VDDQ_AU42 VCCIO_AL42 AM28
+1.2V 2A , 3x22uF, 6x10uF, 4x1uF, SIT update VDDQ_BB23 VCCIO_AM28
BB32 AM30 +VCCSA
BB41 VDDQ_BB32 VCCIO_AM30 AM42
BB47 VDDQ_BB41 VCCIO_AM42
D VDDQ_BB47 D
BB51 AK23
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

10U_0603_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M
5100mA +VCCSA
VDDQ_BB51 VCCSA_AK23 AK25
1 1 1 1 1 1 1 1 1 1 1 1 1 1 VCCSA_AK25 G23 4.5A 10x10uF, 7x1uF, SIT update
CC1256

CC1257

CC1258

CC1168

CC1169

CC1171

CC1222

CC1223

CC1243

CC1244

CC1224

CC1225

CC1226

CC1227
AM40 VCCSA_G23 G25
+VDDQ_CPU_CLK VDDQC VCCSA_G25 G27
2 2 2 2 2 2 2 2 2 2 2 2 2 2 A18 VCCSA_G27 G28

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
+VCCST_CPU VCCST VCCSA_G28 J22 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CD@ CD@ @ @ CD@ @ CD@ @ A22 VCCSA_J22 J23

CC1133

CC1134

CC1135

CC1136

CC1137

CC1251

CC1252

CC1253

CC1139

CC1140

CC1142

CC1145

CC1141

CC1143

CC1144
+VCCSTG VCCSTG_A22 VCCSA_J23 J27

CC1132
AL23 VCCSA_J27 K23
+VCCSFR_OC VCCPLL_OC VCCSA_K23 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
K25
K20 VCCSA_K25 K27
130mA K21 VCCPLL_K20 VCCSA_K27 K28
+VCCPLL_CPU VCCPLL_K21 VCCSA_K28 K30 @ @ @ @ CD@ CD@ CD@
VCCSA_K30
AM23 VCCIO_SENSE 1 TC136 @
VCCIO_SENSE AM22 VSSIO_SENSE 1 TC137 @
VSSIO_SENSE
H21 VCCSA_VSS_SEN
VSSSA_SENSE H20 VCCSA_VCC_SEN VCCSA_VSS_SEN 59
VCCSA_SENSE VCCSA_VCC_SEN 59

SKYLAKE-U_BGA13561 OF 20
REV = 1 ?
@

+VCCSTG +VCCST_CPU
+VDDQ_CPU_CLK
120mA
RC1497 1 @ 2 0_0402_5% RC103 1 @ 2 0_0402_5%

1U_0402_6.3V6K
+1.2V +VCCIO
1U_0201_6.3V6-M

10U_0402_6.3V6M

1
RC1604 1 @ 2 0_0402_5%

1U_0402_6.3V6K

CC86
1 1 +VCCST_CPU
+VCCSA
CC1229

CC1228

1
+1.0VALW +VCCST_CPU

CC87
C C
2
2 2 Reserved for VCCST/VCCSTG/VCCPLL
@ power optimized 2
RC1605 1 @ 2 0_0402_5%
VCCSA_VCC_SEN RC101 1 2 100_0402_1%
Reserved for VCCST/VCCSTG/VCCPLL power optimized
+VCCSFR_OC VCCSA_VSS_SEN RC102 1 2 100_0402_1%

+VCCPLL_CPU
RC104 1 @ 2 0_0402_5%
1U_0201_6.3V6-M

1 120mA
RC105 1 @ 2 0_0402_5%
CC85

+VCCST_CPU

0.1u_0201_10V6K

1U_0402_6.3V6K
1 1
2

CC1249

CC84
2 2

+VCCIO
+1.0VALW

22U_0603_6.3V6-M

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0603_6.3V6-M
RC128 1 @ 2 0_0402_5% VCCIO_EN
44 EC_VCCIO_EN 1 1 1 1

CC1250

C1102
CC71

CC72
B B
DC1 1 2 @
11,44 PM_SLP_S3#
1 0.01U_0201_6.3V7-K
RB751V-40_SOD323-2 2 2 2 2
CC77 UC4 @
@ 1 14
2 2 IN1_1 OUT1_2 13
@ IN1_2 OUT1_1
VCCIO_EN 3 12 CC1293 1 2 1000P_0201_50V7-K
EN1 CT1
4 11
+5VALW VBIAS GND
VCCST_EN 5 10 CC1292 1 2 1000P_0201_50V7-K
+1.0VALW EN2 CT2 +VCCST_CPU
6 9
7 IN2_1 OUT2_2 8

10U_0603_6.3V6M
IN2_2 OUT2_1
10U_0603_6.3V6M

VCCST_EN 1
RC142 1 @ 2 0_0402_5% 15

CC80
44 EC_VCCST_EN GPAD
1
G5016KD1U_TDFN14_2X3
CC79

1 0.01U_0201_6.3V7-K
2
CC81 @
2
2
@
Follow DG470 change to Dual Switch 8/ 24 wei

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (CPU PWR2)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
DG421 1.0

Date: Sunday, January 22, 2017 Sheet 13 of 60


5 4 3 2 1
5 4 3 2 1

+1.0VALW RC1503 1 @ 2 0_0603_5% +VCCAMPHY

+1.0VALW RC1504 1 @ 2 0_0402_5% +VCCAPLL_1P0 +3VALW_PCH +VCCPGPPG

+VCCHDA

RC1622 1 @ 2 0_0402_5%
D D

+3VALW_PCH RC1586 1 @ 2 0_0402_5%

RC1620 1 @ 2 0_0402_5% VCCMPHYON_1P0_L1


+1.0VALW

1U_0402_6.3V6K
1

CC144
2

+3VALW_PCH

0.696A
+1.0VALW

Near AB19

1U_0402_6.3V6K
1

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
CC141
1 1 1 1 1
22mA 2.574A +VCCPGPPG

CC156

CC164

CC172

CC173

CC174
+1.0VALW +1.0VALW ?
1 1

22U_0603_6.3V6-M

1U_0402_6.3V6K
SKL_ULT
2 UC1O

CC158
@ 2 2 2 2 2

CC153
CPU POWER 4 OF 4
@ @ @ @

1U_0402_6.3V6K
+VCCDSW_1P0 2 2 AB19 1

1U_0402_6.3V6K
AB20 VCCPRIM_1P0_AB19 AK15
@ 20mA Near Y15

CC175
1 VCCPRIM_1P0_AB20 VCCPGPPA +3VALW_PCH
P18 AG15 4mA

CC145

1U_0402_6.3V6K
VCCPRIM_1P0_P18 VCCPGPPB Y16
+1.0VALW
1.5A Near AF18 VCCPGPPC
6mA
2
1
AF18 Y15 8mA

CC176
2 AF19 VCCPRIM_CORE_AF18 VCCPGPPD T16 6mA @
VCCPRIM_CORE_AF19 VCCPGPPE +1.8VALW
C V20 AF16 161mA C
47U_0805_4V6-M

1U_0201_6.3V6-M

1U_0402_6.3V6K
VCCPRIM_CORE_V20 VCCPGPPF +1.8VALW 2
1 1 PCH Internal VRM V21 AD15 61mA
1
VCCPRIM_CORE_V21 VCCPGPPG @
CC148

CC147

CC142
+3VALW_PCH
Near N15 AL1 V19

0.1u_0201_10V6K

1U_0402_6.3V6K
DCPDSW_1P0 VCCPRIM_3P3_V19
1 1
2 2 K17 T1 2

CC149

CC143
VCCMPHYON_1P0_L1 VCCMPHYAON_1P0_K17 VCCPRIM_1P0_T1 +1.0VALW
+VCCAMPHY
88mA L1
@ VCCMPHYAON_1P0_L1 AA1 6mA
22U_0603_6.3V6-M

1U_0402_6.3V6K

N15 VCCATS_1P8 2 2
1 1 VCCMPHYGT_1P0_N15
N16 AK17 1mA
C1096

CC151

N17 VCCMPHYGT_1P0_N16 VCCRTCPRIM_3P3


P15 VCCMPHYGT_1P0_N17 AK19 1mA
2 2 VCCMPHYGT_1P0_P15 VCCRTC_AK19 VCCRTC
Near K15 P16 BB14

0.1u_0201_10V6K

1U_0402_6.3V6K
@ VCCMPHYGT_1P0_P16 VCCRTC_BB14
1 1
K15 BB10 VCCRTCEXT

CC146

CC1242
L15 VCCAMPHYPLL_1P0_K15 DCPRTC
VCCAMPHYPLL_1P0_L15 A14 35mA

0.1u_0201_10V6K
VCCCLK1 +1.0VALW 2 2
+VCCAPLL_1P0
22mA V15 1
VCCAPLL_1P0 K19 29mA RC1587 1 @ 2 0_0603_5%

CC55
0.1u_0201_10V6K

1U_0402_6.3V6K

VCCCLK2 +1.0VALW
1 1 AB17

1U_0402_6.3V6K
+1.0VALW VCCPRIM_1P0_AB17
Y18 L21 24mA
C1097

CC154

1 1

22U_0603_6.3V6-M
VCCPRIM_1P0_Y18 VCCCLK3 +1.0VALW 2

C1098
CC56
+VCCHDA
0.118A AD17 N20 33mA
0.1u_0201_10V6K

2 2 +3VALW VCCDSW_3P3_AD17 VCCCLK4 +VCCCLK4


1 AD18
AJ17 VCCDSW_3P3_AD18 L19 4mA 2 2
CC165

VCCDSW_3P3_AJ17 VCCCLK5 +VCCCLK5


@
68mA AJ19 A10 10mA
+1.0VALW
2 VCCHDA VCCCLK6

1U_0402_6.3V6K
+3VALW_PCH
11mA AJ16 AN11 1
VCCSPI GPP_B0/CORE_VID0 AN13

CC57
0.642A AF20 GPP_B1/CORE_VID1
+1.0VALW VCCSRAM_1P0_AF20
AF21
1U_0402_6.3V6K

T19 VCCSRAM_1P0_AF21 2
1 Near AF20 VCCSRAM_1P0_T19
T20
CC159

VCCSRAM_1P0_T20
+3VALW_PCH
75mA AJ21
2 VCCPRIM_3P3_AJ21
1U_0402_6.3V6K

CD@ 1 +1.0VALW AK20


VCCPRIM_1P0_AK20
CC171

+1.0VALW
33mA N18 +VCCCLK4 RC1588 1 @ 2 0_0603_5% +1.0VALW
B VCCAPLLEBB B

22U_0603_6.3V6-M
2
1
1U_0402_6.3V6K

SKYLAKE-U_BGA1356 1 OF 20

C1099
1
CD@ REV = 1
CC169

?
@
2
2 @

+VCCCLK5 RC1589 1 @ 2 0_0603_5% +1.0VALW


Near A18

22U_0603_6.3V6-M
1

C1100
2
@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (PCH PWR)


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
DG421 1.0

Date: Sunday, January 22, 2017 Sheet 14 of 60


5 4 3 2 1
5 4 3 2 1

UC1Q
SKL_ULT ?
SKL_ULT
UC1P ?
D GND 2 OF 3 D
GND 1 OF 3
AT63 BA49
A5 AL65 AT68 VSS_AT63 VSS_BA49 BA53
A67 VSS_A5 VSS_AL65 AL66 AT71 VSS_AT68 VSS_BA53 BA57
A70 VSS_A67 VSS_AL66 AM13 AU10 VSS_AT71 VSS_BA57 BA6
AA2 VSS_A70 VSS_AM13 AM21 AU15 VSS_AU10 VSS_BA6 BA62
AA4 VSS_AA2 VSS_AM21 AM25 AU20 VSS_AU15 VSS_BA62 BA66
AA65 VSS_AA4 VSS_AM25 AM27 AU32 VSS_AU20 VSS_BA66 BA71
AA68 VSS_AA65 VSS_AM27 AM43 AU38 VSS_AU32 VSS_BA71 BB18
AB15 VSS_AA68 VSS_AM43 AM45 AV1 VSS_AU38 VSS_BB18 BB26
AB16 VSS_AB15 VSS_AM45 AM46 AV68 VSS_AV1 VSS_BB26 BB30
AB18 VSS_AB16 VSS_AM46 AM55 AV69 VSS_AV68 VSS_BB30 BB34
AB21 VSS_AB18 VSS_AM55 AM60 AV70 VSS_AV69 VSS_BB34 BB38
VSS_AB21 VSS_AM60 VSS_AV70 VSS_BB38 SKL_ULT ?
AB8 AM61 AV71 BB43 UC1R
AD13 VSS_AB8 VSS_AM61 AM68 AW10 VSS_AV71 VSS_BB43 BB55
AD16 VSS_AD13 VSS_AM68 AM71 AW12 VSS_AW10 VSS_BB55 BB6 GND 3 OF 3
AD19 VSS_AD16 VSS_AM71 AM8 AW14 VSS_AW12 VSS_BB6 BB60 F8 L18
AD20 VSS_AD19 VSS_AM8 AN20 AW16 VSS_AW14 VSS_BB60 BB64 G10 VSS_F8 VSS_L18 L2
AD21 VSS_AD20 VSS_AN20 AN23 AW18 VSS_AW16 VSS_BB64 BB67 G22 VSS_G10 VSS_L2 L20
AD62 VSS_AD21 VSS_AN23 AN28 AW21 VSS_AW18 VSS_BB67 BB70 G43 VSS_G22 VSS_L20 L4
AD8 VSS_AD62 VSS_AN28 AN30 AW23 VSS_AW21 VSS_BB70 C1 G45 VSS_G43 VSS_L4 L8
AE64 VSS_AD8 VSS_AN30 AN32 AW26 VSS_AW23 VSS_C1 C25 G48 VSS_G45 VSS_L8 N10
AE65 VSS_AE64 VSS_AN32 AN33 AW28 VSS_AW26 VSS_C25 C5 G5 VSS_G48 VSS_N10 N13
AE66 VSS_AE65 VSS_AN33 AN35 AW30 VSS_AW28 VSS_C5 D10 G52 VSS_G5 VSS_N13 N19
AE67 VSS_AE66 VSS_AN35 AN37 AW32 VSS_AW30 VSS_D10 D11 G55 VSS_G52 VSS_N19 N21
AE68 VSS_AE67 VSS_AN37 AN38 AW34 VSS_AW32 VSS_D11 D14 G58 VSS_G55 VSS_N21 N6
AE69 VSS_AE68 VSS_AN38 AN40 AW36 VSS_AW34 VSS_D14 D18 G6 VSS_G58 VSS_N6 N65
AF1 VSS_AE69 VSS_AN40 AN42 AW38 VSS_AW36 VSS_D18 D22 G60 VSS_G6 VSS_N65 N68
AF10 VSS_AF1 VSS_AN42 AN58 AW41 VSS_AW38 VSS_D22 D25 G63 VSS_G60 VSS_N68 P17
AF15 VSS_AF10 VSS_AN58 AN63 AW43 VSS_AW41 VSS_D25 D26 G66 VSS_G63 VSS_P17 P19
AF17 VSS_AF15 VSS_AN63 AP10 AW45 VSS_AW43 VSS_D26 D30 H15 VSS_G66 VSS_P19 P20
C AF2 VSS_AF17 VSS_AP10 AP18 AW47 VSS_AW45 VSS_D30 D34 H18 VSS_H15 VSS_P20 P21 C
AF4 VSS_AF2 VSS_AP18 AP20 AW49 VSS_AW47 VSS_D34 D39 H71 VSS_H18 VSS_P21 R13
AF63 VSS_AF4 VSS_AP20 AP23 AW51 VSS_AW49 VSS_D39 D44 J11 VSS_H71 VSS_R13 R6
AG16 VSS_AF63 VSS_AP23 AP28 AW53 VSS_AW51 VSS_D44 D45 J13 VSS_J11 VSS_R6 T15
AG17 VSS_AG16 VSS_AP28 AP32 AW55 VSS_AW53 VSS_D45 D47 J25 VSS_J13 VSS_T15 T17
AG18 VSS_AG17 VSS_AP32 AP35 AW57 VSS_AW55 VSS_D47 D48 J28 VSS_J25 VSS_T17 T18
AG19 VSS_AG18 VSS_AP35 AP38 AW6 VSS_AW57 VSS_D48 D53 J32 VSS_J28 VSS_T18 T2
AG20 VSS_AG19 VSS_AP38 AP42 AW60 VSS_AW6 VSS_D53 D58 J35 VSS_J32 VSS_T2 T21
AG21 VSS_AG20 VSS_AP42 AP58 AW62 VSS_AW60 VSS_D58 D6 J38 VSS_J35 VSS_T21 T4
AG71 VSS_AG21 VSS_AP58 AP63 AW64 VSS_AW62 VSS_D6 D62 J42 VSS_J38 VSS_T4 U10
AH13 VSS_AG71 VSS_AP63 AP68 AW66 VSS_AW64 VSS_D62 D66 J8 VSS_J42 VSS_U10 U63
AH6 VSS_AH13 VSS_AP68 AP70 AW8 VSS_AW66 VSS_D66 D69 K16 VSS_J8 VSS_U63 U64
AH63 VSS_AH6 VSS_AP70 AR11 AY66 VSS_AW8 VSS_D69 E11 K18 VSS_K16 VSS_U64 U66
AH64 VSS_AH63 VSS_AR11 AR15 B10 VSS_AY66 VSS_E11 E15 K22 VSS_K18 VSS_U66 U67
AH67 VSS_AH64 VSS_AR15 AR16 B14 VSS_B10 VSS_E15 E18 K61 VSS_K22 VSS_U67 U69
AJ15 VSS_AH67 VSS_AR16 AR20 B18 VSS_B14 VSS_E18 E21 K63 VSS_K61 VSS_U69 U70
AJ18 VSS_AJ15 VSS_AR20 AR23 B22 VSS_B18 VSS_E21 E46 K64 VSS_K63 VSS_U70 V16
AJ20 VSS_AJ18 VSS_AR23 AR28 B30 VSS_B22 VSS_E46 E50 K65 VSS_K64 VSS_V16 V17
AJ4 VSS_AJ20 VSS_AR28 AR35 B34 VSS_B30 VSS_E50 E53 K66 VSS_K65 VSS_V17 V18
AK11 VSS_AJ4 VSS_AR35 AR42 B39 VSS_B34 VSS_E53 E56 K67 VSS_K66 VSS_V18 W13
AK16 VSS_AK11 VSS_AR42 AR43 B44 VSS_B39 VSS_E56 E6 K68 VSS_K67 VSS_W13 W6
AK18 VSS_AK16 VSS_AR43 AR45 B48 VSS_B44 VSS_E6 E65 K70 VSS_K68 VSS_W6 W9
AK21 VSS_AK18 VSS_AR45 AR46 B53 VSS_B48 VSS_E65 E71 K71 VSS_K70 VSS_W9 Y17
AK22 VSS_AK21 VSS_AR46 AR48 B58 VSS_B53 VSS_E71 F1 L11 VSS_K71 VSS_Y17 Y19
AK27 VSS_AK22 VSS_AR48 AR5 B62 VSS_B58 VSS_F1 F13 L16 VSS_L11 VSS_Y19 Y20
AK63 VSS_AK27 VSS_AR5 AR50 B66 VSS_B62 VSS_F13 F2 L17 VSS_L16 VSS_Y20 Y21
AK68 VSS_AK63 VSS_AR50 AR52 B71 VSS_B66 VSS_F2 F22 VSS_L17 VSS_Y21
AK69 VSS_AK68 VSS_AR52 AR53 BA1 VSS_B71 VSS_F22 F23
AK8 VSS_AK69 VSS_AR53 AR55 BA10 VSS_BA1 VSS_F23 F27
AL2 VSS_AK8 VSS_AR55 AR58 BA14 VSS_BA10 VSS_F27 F28
AL28 VSS_AL2 VSS_AR58 AR63 BA18 VSS_BA14 VSS_F28 F32 1 OF 20
SKYLAKE-U_BGA1356
AL32 VSS_AL28 VSS_AR63 AR8 BA2 VSS_BA18 VSS_F32 F33 REV = 1
VSS_AL32 VSS_AR8 VSS_BA2 VSS_F33 ?
B AL35 AT2 BA23 F35 @ B
AL38 VSS_AL35 VSS_AT2 AT20 BA28 VSS_BA23 VSS_F35 F37
AL4 VSS_AL38 VSS_AT20 AT23 BA32 VSS_BA28 VSS_F37 F38
AL45 VSS_AL4 VSS_AT23 AT28 BA36 VSS_BA32 VSS_F38 F4
AL48 VSS_AL45 VSS_AT28 AT35 F68 VSS_BA36 VSS_F4 F40
AL52 VSS_AL48 VSS_AT35 AT4 BA45 VSS_F68 VSS_F40 F42
AL55 VSS_AL52 VSS_AT4 AT42 VSS_BA45 VSS_F42 BA41
AL58 VSS_AL55 VSS_AT42 AT56 VSS_BA41
AL64 VSS_AL58 VSS_AT56 AT58
VSS_AL64 VSS_AT58
1 OF 20
SKYLAKE-U_BGA1356
1 OF 20
SKYLAKE-U_BGA1356 REV = 1 ?
REV = 1 ? @
@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (VSS)


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG421
Date: Sunday, January 22, 2017 Sheet 15 of 60
5 4 3 2 1
5 4 3 2 1

?
SKL_ULT
UC1S

RESERVED SIGNALS-1

CPU_CFG0 E68 BB68 1 TC173 @ PAD


D PAD @ TC142 1 CPU_CFG1 B67 CFG[0] RSVD_TP_BB68 BB69 1 TC174 @ PAD D
PAD @ TC143 1 CPU_CFG2 D65 CFG[1] RSVD_TP_BB69
PAD @ TC144 1 XDP_CPU_CFG3 D67 CFG[2] AK13 1 TC175 @ PAD
CPU_CFG4 CFG[3] RSVD_TP_AK13
2

E70 AK12 1 TC176 @ PAD


RC1618 PAD @ TC146 1 CPU_CFG5 C68 CFG[4] RSVD_TP_AK12 +VCCST_CPU
1K_0402_5% PAD @ TC147 1 CPU_CFG6 D68 CFG[5] BB2 UC1T SKL_ULT ?
@ PAD @ TC148 1 CPU_CFG7 C67 CFG[6] RSVD_BB2 BA3
CPU_CFG8 CFG[7] RSVD_BA3

2
PAD @ TC153 1 F71 SPARE
CFG[8]
1

RC106 PAD @ TC150 1 CPU_CFG9 G69 +1.8VALW


CPU_CFG10 CFG[9]

1
1K_0402_5% PAD @ TC151 1 F70 AU5 AW69 F6
PAD @ TC152 1 CPU_CFG11 G68 CFG[10] TP5 AT5 AW68 RSVD_AW69 RSVD_F6 E3 RC1619
PAD @ TC157 1 CPU_CFG12 H70 CFG[11] TP6 AU56 RSVD_AW68 RSVD_E3 C11 150_0402_5%
CFG[12] RSVD_AU56 RSVD_C11
1

PAD @ TC154 1 CPU_CFG13 G71 AW48 B11 @


PAD @ TC155 1 CPU_CFG14 H69 CFG[13] D5 Cannonlake@ C7 RSVD_AW48 RSVD_B11 A11
CFG[14] RSVD_D5 RSVD_C7 RSVD_A11

2
PAD @ TC156 1 CPU_CFG15 G70 D4 RC1582 2 1 0_0402_5% RSVD_U12 U12 D12
CFG[15] RSVD_D4 B2 1 TC183 @ PAD RC1583 2 1 0_0402_5% RSVD_U11 U11 RSVD_U12 RSVD_D12 C12
PAD @ TC159 1 CPU_CFG16 E63 RSVD_B2 C2 1 TC185 @ PAD Cannonlake@ H11 RSVD_U11 RSVD_C12 F52 RSVD_F52
PAD @ TC158 1 CPU_CFG17 F63 CFG[16] RSVD_C2 RSVD_H11 RSVD_F52
CFG[17] B3 1 TC184 @ PAD
PAD @ TC161 1 CPU_CFG18 E66 RSVD_B3 A3 1 TC181 @ PAD
CPU_CFG19 CFG[18] RSVD_A3 1 OF 20
PAD @ TC160 1 F66 SKYLAKE-U_BGA1356
CFG[19] AW1 REV = 1 ?
C CFG_RCOMP E60 RSVD_AW1 @ C
CFG_RCOMP E1 1 TC187 @ PAD
PAD @ TC166 1 XDP_ITP_PMODE E8 RSVD_E1 E2
ITP_PMODE RSVD_E2
2

RC162 AY2 BA4


AY1 RSVD_AY2 RSVD_BA4 BB4
49.9_0402_1% RSVD_AY1 RSVD_BB4
PAD @ TC186 1 D1 A4 1 TC182 @ PAD
RSVD_D1 RSVD_A4
1

D3 C4
RSVD_D3 RSVD_C4
K46 BB5
K45 RSVD_K46 TP4
RSVD_K45 A69 1 TC188 @ PAD
AL25 RSVD_A69 B69 1 TC193 @ PAD
AL27 RSVD_AL25 RSVD_B69
RSVD_AL27 AY3 RSVD_AY3 need to check with Intel
PAD @ TC189 1 C71 RSVD_AY3
RSVD_C71

2
PAD @ TC191 1 B70 D71 1 TC190 @ PAD
RSVD_B70 RSVD_D71 C70 1 TC192 @ PAD RC107
F60 RSVD_C70 @
RSVD_F60 0_0402_5%
C54
A52 RSVD_C54 D54
RSVD_A52 RSVD_D54

1
B B
PAD @ TC171 1 BA70 AY4
PAD @ TC172 1 BA68 RSVD_TP_BA70 TP1 BB3
RSVD_TP_BA68 TP2
J71 AY71 VSS_AY71 need to check with Intel
J68 RSVD_J71 VSS_AY71 AR56 1 TC167 @ PAD
RSVD_J68 ZVM#

2
PAD @ TC169 1 F65 AW71 1 TC177 @ PAD
PAD @ TC170 1 G65 VSS_F65 RSVD_TP_AW71 AW70 1 TC178 @ PAD RC108
VSS_G65 RSVD_TP_AW70 @ 0_0402_5%
F61 AP56 1 TC168 @ PAD
E61 RSVD_F61 MSM# C64 PROC_SELECT# 1 2
RSVD_E61 PROC_SELECT# +VCCST_CPU

1
100K_0402_5% Cannonlake@ R22

1 OF 20
SKYLAKE-U_BGA1356
REV = 1 ?
@
Default
Pin Name Strap Description Configuration Value

A A
CFG[4] Display Port — 1 = eDP Disabled 1
Presence strap — 0 = eDP Enabled
* Security Classification LC Future Center Secret Data Title
Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (CFG,RESERVED)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG421
Date: Sunday, January 22, 2017 Sheet 16 of 60
5 4 3 2 1
5 4 3 2 1

DDRA_DQ[0..63]
DDRA_DQ[0..63] 5
DDRA_DQS#[0..7]
UD1 @ UD2 @
DDRA_DQS#[0..7] 5
DDRA_MA0 DDRA_DQ2 DDRA_MA0 DDRA_DQ18 +1.2V DDRA_DQS[0..7]
P3 G2 P3 G2
DDRA_MA1 A0 DQ0 DDRA_DQ3 DDRA_MA1 A0 DQ0 DDRA_DQ19 DDRA_DQS[0..7] 5
P7 F7 P7 F7
DDRA_MA2 A1 DQ1 DDRA_DQ7 DDRA_MA2 A1 DQ1 DDRA_DQ16 DDRA_MA[0..13]
R3 H3 R3 H3
DDRA_MA3 A2 DQ2 DDRA_DQ1 DDRA_MA3 A2 DQ2 DDRA_DQ21 DDRA_MA[0..13] 5
N7 H7 N7 H7
DDRA_MA4 N3 A3 DQ3 H2 DDRA_DQ4 DDRA_MA4 N3 A3 DQ3 H2 DDRA_DQ22
DDRA_MA5 A4 DQ4 DDRA_DQ0 DDRA_MA5 A4 DQ4 DDRA_DQ17 1

1
P8 H8 P8 H8 MD@ MD@ +0.6VS
DDRA_MA6 P2 A5 DQ5 J3 DDRA_DQ6 DDRA_MA6 P2 A5 DQ5 J3 DDRA_DQ23
CD119 RD45
DDRA_MA7 R8 A6 DQ6 J7 DDRA_DQ5 DDRA_MA7 R8 A6 DQ6 J7 DDRA_DQ20
0.1u_0201_10V6K 1.8K_0402_1%
DDRA_MA8 R2 A7 DQ7 A3 DDRA_DQ11 DDRA_MA8 R2 A7 DQ7 A3 DDRA_DQ30 2 DDRA_CLK0# 1 MD@ 2
RD49 36_0402_1%
DDRA_MA9 R7 A8 DQ8 B8 DDRA_DQ8 DDRA_MA9 R7 A8 DQ8 B8 DDRA_DQ28 DDRA_CLK0 1 MD@ 2
RD50 36_0402_1%
DDRA_MA10 A9 DQ9 DDRA_DQ14 DDRA_MA10 A9 DQ9 DDRA_DQ26

2
M3 C3 M3 C3
DDRA_MA11 T2 A10/AP DQ10 C7 DDRA_DQ13 DDRA_MA11 T2 A10/AP DQ10 C7 DDRA_DQ25 DDRA_CS0# 1 MD@ 2
RD51 34.8_0402_1%
DDRA_MA12 M7 A11 DQ11 C2 DDRA_DQ15 DDRA_MA12 M7 A11 DQ11 C2 DDRA_DQ31 +VREF_CA_MD DDRA_ODT0
RD46 1 2 MD@ RD52 1 MD@ 2 34.8_0402_1%
DDRA_MA13 A12/BC_N DQ12 DDRA_DQ12 DDRA_MA13 A12/BC_N DQ12 DDRA_DQ29 5 DDR_SA_VREFCA
T8 C8 T8 C8 2.7_0402_1%
A13 DQ13 D3 DDRA_DQ10 A13 DQ13 D3 DDRA_DQ27 DDRA_CKE0 1 MD@ 2
1 RD53 34.8_0402_1%
DDRA_MA14_WE# DQ14 DDRA_DQ9 DDRA_MA14_WE# DQ14 DDRA_DQ24

1
D 5 DDRA_MA14_WE# L2 D7 L2 D7 MD@ 1 D
DDRA_MA15_CAS# M8 WE_N/A14 DQ15 DDRA_MA15_CAS# M8 WE_N/A14 DQ15 DDRA_MA0 1 MD@ 2
CD111 RD47 MD@ RD54 34.8_0402_1%
5 DDRA_MA15_CAS# DDRA_MA16_RAS# CAS_N/A15 +1.2V DDRA_MA16_RAS# CAS_N/A15 +1.2V DDRA_MA1
L8 L8 0.022U_0201_6.3V6-K MD@ 1.8K_0402_1% CD112 RD55 1 MD@ 2 34.8_0402_1%
5 DDRA_MA16_RAS# RAS_N/A16 RAS_N/A16 2 DDRA_MA2
D1 D1 0.1u_0201_10V6K RD56 1 MD@ 2 34.8_0402_1%
DDRA_CLK0# K8 VDD1 J1 DDRA_CLK0# K8 VDD1 J1 2 DDRA_MA3 1 MD@ 2
5 DDRA_CLK0# RD57 34.8_0402_1%
DDRA_CLK0 CK_C VDD2 DDRA_CLK0 CK_C VDD2

2
1
5 DDRA_CLK0 K7 L1 K7 L1
CK_T VDD3 R1 CK_T VDD3 R1 DDRA_MA4 1 MD@ 2
RD48 RD58 34.8_0402_1%
DDRA_CKE0 K2 VDD4 B3 DDRA_CKE0 K2 VDD4 B3 DDRA_MA5 1 MD@ 2
5 DDRA_CKE0 24.9_0402_1% MD@ RD59 34.8_0402_1%
CKE VDD5 G7 CKE VDD5 G7 DDRA_MA6 1 MD@ 2
RD60 34.8_0402_1%
DDRA_DQS#0 F3 VDD6 B9 DDRA_DQS#2 F3 VDD6 B9 DDRA_MA7 1 MD@ 2
RD61 34.8_0402_1%
DDRA_DQS0 LDQS_C VDD7 DDRA_DQS2 LDQS_C VDD7

2
G3 J9 G3 J9
DDRA_DQS#1 A7 LDQS_T VDD8 L9 DDRA_DQS#3 A7 LDQS_T VDD8 L9 DDRA_MA8 1 MD@ 2
RD62 34.8_0402_1%
+1.2V DDRA_DQS1 B7 UDQS_C VDD9 T9 +1.2V DDRA_DQS3 B7 UDQS_C VDD9 T9 DDRA_MA9 1 MD@ 2
RD63 34.8_0402_1%
UDQS_T VDD10 UDQS_T VDD10 DDRA_MA10 1 MD@ 2
RD64 34.8_0402_1%
DDRA_DM1 DDRA_DM3 DDRA_MA11
RD65 1 @ 2 0_0402_5% E2 A1 RD66 1 @ 2 0_0402_5% E2 A1 RD67 1 MD@ 2 34.8_0402_1%
RD68 1 @ 2 0_0402_5% DDRA_DM0 E7 NF/UDM_N/UDBI_N VDDQ1 C1 RD69 1 @ 2 0_0402_5% DDRA_DM2 E7 NF/UDM_N/UDBI_N VDDQ1 C1
NF/LDM_N/LDBI_N VDDQ2 G1 NF/LDM_N/LDBI_N VDDQ2 G1 DDRA_MA12 1 MD@ 2
RD70 34.8_0402_1%
DDRA_BS0# N2 VDDQ3 F2 DDRA_BS0# N2 VDDQ3 F2 DDRA_MA13 1 MD@ 2
5 DDRA_BS0# RD71 34.8_0402_1%
DDRA_BS1# N8 BA0 VDDQ4 J2 DDRA_BS1# N8 BA0 VDDQ4 J2 DDRA_MA14_WE# 1 MD@ 2
5 DDRA_BS1# RD72 34.8_0402_1%
BA1 VDDQ5 F8 BA1 VDDQ5 F8 DDRA_MA15_CAS# 1 MD@ 2
RD73 34.8_0402_1%
DDRA_ACT# L3 VDDQ6 J8 DDRA_ACT# L3 VDDQ6 J8
5 DDRA_ACT# DDRA_CS0# ACT_N VDDQ7 DDRA_CS0# ACT_N VDDQ7
L7 A9 L7 A9
5 DDRA_CS0# DDRA_ALERT# CS_N VDDQ8 DDRA_ALERT# CS_N VDDQ8 DDRA_MA16_RAS#
P9 D9 P9 D9 RD74 1 MD@ 2 34.8_0402_1%
5 DDRA_ALERT# ALERT_N VDDQ9 +2.5V_DDR ALERT_N VDDQ9 +2.5V_DDR DDRA_BG0
G9 G9 RD75 1 MD@ 2 34.8_0402_1%
DDRA_BG0 M2 VDDQ10 DDRA_BG0 M2 VDDQ10 DDRA_BS0# 1 MD@ 2
5 DDRA_BG0 RD76 34.8_0402_1%
BG0 B1 BG0 B1 DDRA_BS1# RD77 1 MD@ 2 34.8_0402_1%
DDRA_ODT0 K3 VPP1 R9 DDRA_ODT0 K3 VPP1 R9
5 DDRA_ODT0 ODT VPP2 ODT VPP2 DDRA_ACT#
RD78 1 MD@ 2 34.8_0402_1%
DDRA_PAR T3 M1 +VREF_CA_MD DDRA_PAR T3 M1 +VREF_CA_MD DDRA_PAR 1 MD@ 2
RD79 34.8_0402_1%
5 DDRA_PAR PAR VREFCA PAR VREFCA

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1
RD94 1 MD@ 2 10K_0402_5% TEN_UD1 N9 E1 MD@ CD@ RD95 1 MD@ 2 10K_0402_5% TEN_UD2 N9 E1 MD@ MD@
TEN VSS1 TEN VSS1

0.1u_0201_10V6K

0.1u_0201_10V6K
.047U_0201_6.3V6K

.047U_0201_6.3V6K
K1 1 1 K1 1 1
CPU_DRAMRST# P1 VSS2 N1 CPU_DRAMRST# P1 VSS2 N1
MD@ MD@ MD@ MD@
6,18 CPU_DRAMRST# RESET_N VSS3 2 2 RESET_N VSS3 2 2
T1 T1
@ F1 VSS4 B2 @ F1 VSS4 B2

CD121

CD123

CD124

CD125
VSSQ1 VSS5 2 2 VSSQ1 VSS5 2 2
0.1u_0201_10V6K

0.1u_0201_10V6K
1 H1 G8 1 H1 G8
A2 VSSQ2 VSS6 E9 A2 VSSQ2 VSS6 E9 +1.2V

CD114
CD113

CD120

CD122
D2 VSSQ3 VSS7 K9 D2 VSSQ3 VSS7 K9
E3 VSSQ4 VSS8 M9 E3 VSSQ4 VSS8 M9
2 A8 VSSQ5 VSS9 2 A8 VSSQ5 VSS9 DDRA_ALERT# 1 MD@ 2 49.9_0402_1%
RD86
CD47

CD48
D8 VSSQ6 T7 D8 VSSQ6 T7
E8 VSSQ7 NC E8 VSSQ7 NC
C9 VSSQ8 C9 VSSQ8
H9 VSSQ9 H9 VSSQ9
VSSQ10 VSSQ10
C C
F9 F9
ZQ ZQ
1

1
MD@ RD39 MT40A512M16HA083EA_FBGA96 RD40 MT40A512M16HA083EA_FBGA96
240_0402_1% MD@ 240_0402_1%
2

2
+1.2V (1uF_0402_6.3V) *16
Place 4 near each DRAM

1U_0402_6.3V6K
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
UD3 @ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
UD4 @ MD@ MD@ MD@ CD@ CD@ MD@ MD@ MD@ MD@ MD@ MD@ MD@
DDRA_MA0 P3 G2 DDRA_DQ43
DDRA_MA1 P7 A0 DQ0 F7 DDRA_DQ44 DDRA_MA0 P3 G2 DDRA_DQ59
DDRA_MA2 R3 A1 DQ1 H3 DDRA_DQ46 DDRA_MA1 P7 A0 DQ0 F7 DDRA_DQ60 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
DDRA_MA3 N7 A2 DQ2 H7 DDRA_DQ40 DDRA_MA2 R3 A1 DQ1 H3 DDRA_DQ62

CD129
CD126

CD127

CD128

CD130

CD131

CD132

CD133

CD134

CD135

CD136

CD137

CD138

CD139

CD140

CD141
DDRA_MA4 N3 A3 DQ3 H2 DDRA_DQ47 DDRA_MA3 N7 A2 DQ2 H7 DDRA_DQ56
DDRA_MA5 P8 A4 DQ4 H8 DDRA_DQ45 DDRA_MA4 N3 A3 DQ3 H2 DDRA_DQ63
CD@ CD@ CD@ CD@
DDRA_MA6 P2 A5 DQ5 J3 DDRA_DQ42 DDRA_MA5 P8 A4 DQ4 H8 DDRA_DQ61
DDRA_MA7 R8 A6 DQ6 J7 DDRA_DQ41 DDRA_MA6 P2 A5 DQ5 J3 DDRA_DQ58
DDRA_MA8 R2 A7 DQ7 A3 DDRA_DQ34 DDRA_MA7 R8 A6 DQ6 J7 DDRA_DQ57
DDRA_MA9 R7 A8 DQ8 B8 DDRA_DQ37 DDRA_MA8 R2 A7 DQ7 A3 DDRA_DQ54
DDRA_MA10 M3 A9 DQ9 C3 DDRA_DQ39 DDRA_MA9 R7 A8 DQ8 B8 DDRA_DQ52
DDRA_MA11 T2 A10/AP DQ10 C7 DDRA_DQ32 DDRA_MA10 M3 A9 DQ9 C3 DDRA_DQ51
DDRA_MA12 M7 A11 DQ11 C2 DDRA_DQ35 DDRA_MA11 T2 A10/AP DQ10 C7 DDRA_DQ49 +1.2V +1.2V
DDRA_MA13 A12/BC_N DQ12 DDRA_DQ33 DDRA_MA12 A11 DQ11 DDRA_DQ50
(1OuF_0603_6.3V) *5
T8 C8 M7 C2 Place around the DRAMs
A13 DQ13 D3 DDRA_DQ38 DDRA_MA13 T8 A12/BC_N DQ12 C8 DDRA_DQ53
DDRA_MA14_WE# L2 DQ14 D7 DDRA_DQ36 A13 DQ13 D3 DDRA_DQ55
DDRA_MA15_CAS# M8 WE_N/A14 DQ15 DDRA_MA14_WE# L2 DQ14 D7 DDRA_DQ48
DDRA_MA16_RAS# L8 CAS_N/A15 +1.2V DDRA_MA15_CAS# M8 WE_N/A14 DQ15
RAS_N/A16 D1 DDRA_MA16_RAS# L8 CAS_N/A15 +1.2V
DDRA_CLK0# K8 VDD1 J1 RAS_N/A16 D1
DDRA_CLK0 CK_C VDD2 DDRA_CLK0# VDD1

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
K7 L1 K8 J1 1 1 1 1 1 1 1
CK_T VDD3 R1 DDRA_CLK0 K7 CK_C VDD2 L1
B CD@ CD@ MD@ MD@ CD109 CD110 B
DDRA_CKE0 K2 VDD4 B3 CK_T VDD3 R1 22P_0402_50V8-J 22P_0402_50V8-J
CKE VDD5 G7 DDRA_CKE0 K2 VDD4 B3 RF@ RF@
DDRA_DQS#5 F3 VDD6 B9 CKE VDD5 G7 2 2 2 2 2 2 2
DDRA_DQS5 G3 LDQS_C VDD7 J9 DDRA_DQS#7 F3 VDD6 B9

CD142

CD143

CD144

CD145

CD146
DDRA_DQS#4 A7 LDQS_T VDD8 L9 DDRA_DQS7 G3 LDQS_C VDD7 J9
+1.2V DDRA_DQS4 B7 UDQS_C VDD9 T9 DDRA_DQS#6 A7 LDQS_T VDD8 L9 CD@
UDQS_T VDD10 +1.2V DDRA_DQS6 B7 UDQS_C VDD9 T9
DDRA_DM4 UDQS_T VDD10
RD87 1 @ 2 0_0402_5% E2 A1
DDRA_DM5 NF/UDM_N/UDBI_N VDDQ1 DDRA_DM6
RD88 1 @ 2 0_0402_5% E7 C1 RD89 1 @ 2 0_0402_5% E2 A1
NF/LDM_N/LDBI_N VDDQ2 G1 DDRA_DM7 NF/UDM_N/UDBI_N VDDQ1
RD90 1 @ 2 0_0402_5% E7 C1
DDRA_BS0# N2 VDDQ3 F2 NF/LDM_N/LDBI_N VDDQ2 G1
DDRA_BS1# N8 BA0 VDDQ4 J2 DDRA_BS0# N2 VDDQ3 F2
BA1 VDDQ5 F8 DDRA_BS1# N8 BA0 VDDQ4 J2
DDRA_ACT# L3 VDDQ6 J8 BA1 VDDQ5 F8
DDRA_CS0# L7 ACT_N VDDQ7 A9 DDRA_ACT# L3 VDDQ6 J8
DDRA_ALERT# CS_N VDDQ8 DDRA_CS0# ACT_N VDDQ7
(1OuF_0603_6.3V) *3
P9 D9 L7 A9 +2.5V_DDR +2.5V_DDR
ALERT_N VDDQ9 +2.5V_DDR DDRA_ALERT# CS_N VDDQ8 Place around the DRAMs
G9 P9 D9
DDRA_BG0 M2 VDDQ10 ALERT_N VDDQ9 G9 +2.5V_DDR
BG0 B1 DDRA_BG0 M2 VDDQ10
DDRA_ODT0 K3 VPP1 R9 BG0 B1
ODT VPP2 DDRA_ODT0 K3 VPP1 R9
DDRA_PAR +VREF_CA_MD ODT VPP2

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
T3 M1 1 1 1 1 1
PAR VREFCA DDRA_PAR +VREF_CA_MD
1U_0402_6.3V6K

1U_0402_6.3V6K

1 1 T3 M1 MD@ MD@ CD@ CD157 CD148


2 10K_0402_5% TEN_UD3 PAR VREFCA

1U_0402_6.3V6K

1U_0402_6.3V6K
RD96 1 MD@ N9 E1 CD@ 1 1 22P_0402_50V8-J 22P_0402_50V8-J
TEN VSS1 TEN_UD4
0.1u_0201_10V6K

K1 RD97 1 MD@ 2 10K_0402_5% N9 E1


.047U_0201_6.3V6K

1 1 MD@ RF@ RF@


CPU_DRAMRST# VSS2 TEN VSS1 2 2 2 2 2

0.1u_0201_10V6K
.047U_0201_6.3V6K
P1 N1 MD@ MD@ K1 1 1
RESET_N VSS3 T1 2 2 CPU_DRAMRST# P1 VSS2 N1 MD@ MD@

CD152

CD156

CD147
@ F1 VSS4 B2 RESET_N VSS3 T1 2 2
CD150

CD151

VSSQ1 VSS5 VSS4


0.1u_0201_10V6K

H1 G8 2 2 @ F1 B2
1

CD154

CD155
VSSQ2 VSS6 VSSQ1 VSS5 2 2
0.1u_0201_10V6K

A2 E9 CD@ 1 H1 G8
CD115

CD149

D2 VSSQ3 VSS7 K9 A2 VSSQ2 VSS6 E9 CD@

CD116

CD153
E3 VSSQ4 VSS8 M9 D2 VSSQ3 VSS7 K9
2 A8 VSSQ5 VSS9 E3 VSSQ4 VSS8 M9
CD107

D8 VSSQ6 T7 2 A8 VSSQ5 VSS9


CD108

E8 VSSQ7 NC D8 VSSQ6 T7
C9 VSSQ8 E8 VSSQ7 NC
H9 VSSQ9 C9 VSSQ8 +0.6VS +0.6VS
VSSQ10 VSSQ9
(1uF_0402_6.3V) *8 (1OuF_0603_6.3V) *2
H9 Place 2 near each DRAM Place around the DRAMs
F9 VSSQ10
ZQ F9
ZQ
1

RD43 MT40A512M16HA083EA_FBGA96

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M
MD@ 240_0402_1% RD44 MT40A512M16HA083EA_FBGA96 1 1 1 1 1 1 1 1 1 1 1 1
MD@ 240_0402_1% MD@ MD@ CD@ CD@ MD@ MD@ MD@ CD168 CD169
A 22P_0402_50V8-J 22P_0402_50V8-J A
2

RF@ RF@
2

2 2 2 2 2 2 2 2 2 2 2 2

CD158

CD159

CD160

CD161

CD162

CD163

CD164

CD165

CD166

CD167
CD@ CD@ CD@

Security Classification LC Future Center Secret Data Title


Issued Date 2015/08/20 Deciphered Date 2016/08/20 DDR4 Memory Down
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG421
Date : Sunday, January 22, 2017 Sheet 17 of 60
5 4 3 2 1
5 4 3 2 1

+1.2V

DDR4 SO-DIMM