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HT9032

Calling Line Identification Receiver

Features
· HT9032B/C/D operating voltage: 3.5V~5.5V · Power down mode
HT9032F operating voltage: 3.0V~5.5V · High input sensitivity
· Bell 202 FSK and V.23 demodulation · HT9032C: 16-pin DIP/SOP package
· Ring detection input and output HT9032B/F-A: 8-pin DIP package
· Carrier detection output HT9032D/F-B: 8-pin SOP package

Applications
· Feature phones · Computer telephony interface products
· Caller ID adjunct boxes · ADSI products
· Fax and answering machines

General Description
The HT9032 calling line identification receiver receive and display the calling number, or mes-
is a low power CMOS integrated circuit de- sage waiting indicator sent to subscribers from
signed for receiving physical layer signals tran- the central office facilities. The device also pro-
smitted according to Bellcore TR-NWT-000030 vides a carrier detection circuit and a ring de-
and ITU-T V.23 specifications. The primary ap- tection circuit for easier system applications.
plication of this device is for products used to

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HT9032

Block Diagram

T IP B a n d P a s s
F ilte r D e m o d u la to r
R IN G

D O U T C
V a lid D a ta
P D W N D e te c tio n
D O U T

P o w e r U p C D E T
R T IM E L o g ic

In te rn a l
P o w e r U p
L o g ic
R D E T 1
R D E T

R D E T 2 R in g
A n a ly s is
C ir c u it

V D D R e fe re n c e C lo c k X 1
V o lta g e G e n e ra to r X 2
V S S

Pin Assignment

T IP 1 1 6 V D D
R IN G 2 1 5 D O U T C
R D E T 1 3 1 4 D O U T
R D E T 2 4 1 3 C D E T
T IP 1 8 V D D N C 5 1 2 R D E T D O U T 1 8 X 1
R IN G 2 7 D O U T R T IM E 6 1 1 N C V D D 2 7 X 2
P D W N 3 6 X 1 P D W N 7 1 0 X 1 T IP 3 6 V S S
V S S 4 5 X 2 V S S 8 9 X 2 R IN G 4 5 P D W N

H T 9 0 3 2 B H T 9 0 3 2 C H T 9 0 3 2 D
8 D IP 1 6 D IP /S O P 8 S O P

T IP 1 8 V D D D O U T 1 8 C D E T
R IN G 2 7 D O U T V D D 2 7 X 1
P D W N 3 6 C D E T T IP 3 6 V S S
V S S 4 5 X 1 R IN G 4 5 P D W N

H T 9 0 3 2 F -A H T 9 0 3 2 F -B
8 D IP 8 S O P

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HT9032

Pin Description
Pin Name I/O Description
Power Inputs
VDD ¾ Power-VDD is the input power for the internal logic.
VSS ¾ Ground-VSS is ground connection for the internal logic.
A logic ²1² on this pin puts the chip in power down mode. When a logic ²0² is on
PDWN I
this pin, the chip is activated. This is a schmitt trigger input.
Clock
A crystal or ceramic resonator should be connected to this pin and X2.
X1 I
This pin may be driven from an external clock source.
X2 O A crystal or ceramic resonator should be connected to this pin and X1.
Ring Detections
It detects ring energy on the line through an attenuating network and enables
RDET1 I
the oscillator and ring detection. This is a schmitt trigger input.
It couples the ring signal to the precision ring detector through an attenuating
RDET2 I network. RDET=²0² if a valid ring signal is detected. This is a schmitt trigger in-
put.
An RC network may be connected to this pin in order to hold the pin voltage be-
low 2.2V between the peaks of the ringing signal. This pin controls internal
RTIME I/O power up and activates the partial circuitry needed to determine whether the
incoming ring is valid or not. The input is a schmitt trigger input. The output
cell structure is an NMOS output.
FSK Signal Inputs
This input pin is connected to the tip side of the twisted pair wires. It is inter-
TIP I nally biased to 1/2 VDD when the device is in power up mode. This pin must be
DC isolated from the line.
This input pin is connected to the ring side of the twisted pair wires. It is inter-
RING I nally biased to 1/2 VDD when the device is in power up mode. This pin must be
DC isolated from the line.
Detection Results
This open drain output goes low when a valid ringing signal is detected. When
RDET O
connected to PDWN pin, this pin can be used for auto power up.
This open drain output goes low indicating that a valid carrier is present on the
CDET O line. A hysteresis is built-in to allow for a momentary drop out of the carrier.
When connected to PDWN pin, this pin can be used for auto power up.
This pin presents the output of the demodulator whenever CDET pin is low.
DOUT O This data stream includes the alternate ²1² and ²0² pattern, the marking, and
the data. At all other times, this pin is held high.

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HT9032

Pin Name I/O Description


This output presents the output of the demodulator whenever CDET pin is low
and when an internal validation sequence has been successfully passed. This
DOUTC O
data stream does not include the alternate ²1² and ²0² pattern. This pin is al-
ways held high.

Absolute Maximum Ratings


Voltages are referenced to VSS, except where noted.
Supply Voltage..............................-0.5V to 6.0V All Input Voltages ....................................25mW
Operating Temperature Range .......0°C to 70°C Storage Temperature Range .....-40°C to 150°C

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maxi-
mum Ratings² may cause substantial damage to the device. Functional operation of this device
at other conditions beyond those listed in the specification is not implied and prolonged expo-
sure to extreme conditions may affect device reliability.

D.C. Characteristics Crystal=3.58MHz, Ta=0~70°C

Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions
VDD Supply Voltage ¾ 9032B/C/D 3.5 5 5.5 V
9032F 3.0 5 5.5 V
IDD1 Supply Current 5V PDWN=0 (3.58MHz OSC on) ¾ 3.2 5 mA
PDWN=1 and RTIME=0
IDD2 (3.58MHz OSC on and
Supply Current 5V ¾ 1.9 2.5 mA
internal circuits
partially on)

ISTBY PDWN=1 and RTIME=1


Standby Current 5V ¾ ¾ 1 mA
(3.58MHz OSC off)
VIL Input Voltage Logic 0 5V ¾ ¾ ¾ 0.2V VDD
VIH Input Voltage Logic 1 5V ¾ 0.8V ¾ ¾ VDD
IOL Output Voltage Logic 0 5V IOL=1.6mA ¾ 0.1V VDD
IOH Output Voltage Logic 1 5V IOH=0.8mA 0.9V ¾ ¾ VDD

IIN Input Leakage Current,


5V ¾ -1 ¾ 1 mA
All Inputs

VT- Input Low Threshold


5V RDET1, RTIME, PDWN 2.0 2.3 2.6 V
Voltage

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HT9032

Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions

VT+ Input High Threshold


5V RDET1, RTIME, PDWN 2.5 2.75 3.0 V
Voltage
VTRDET2 Input Threshold Voltage 5V RDET2 1.0 1.1 1.2 V
RIN Input DC Resistance 5V TIP, RING ¾ 500 ¾ kW

T IP V D D
R IN G D O U T C
R D E T 1 0 .1 m F
D O U T
R D E T 2 C D E T
R T IM E R D E T
P D W N X 1
V S S X 2
3 .5 8 M H z
~
H T 9 0 3 2 C
1 0 M W

3 0 p F

S u p p ly c u r r e n t te s tin g : A ll, e x c e p t P D W N a n d R T IM E ,
u n w ir e d p in s a r e le ft flo a tin g .

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HT9032

A.C. Characteristics - FSK Detection


VSS=0V, Crystal=3.58MHz, Ta=0 to 70°C, 0dBm=0.7746Vrms @ 600W
Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions
Input Sensitivity: TIP,
5V -40 -45 ¾ dBm
RING
S/N Signal to Noise Ratio 5V ¾ 20 ¾ dB
Band Pass Filter
60Hz Frequency Response -64
550Hz 5V Relative to 1700Hz @ ¾ -4 ¾ dB
2700Hz 0dBm -3
3300Hz -34
Carrier Detect Sensitivity 5V ¾ -48 ¾ dBm
tDOSC Oscillator Start Up Time 5V ¾ ¾ 2 ¾ ms

tSUPD Power Up to FSK Signal


5V ¾ 15 ¾ ¾ ms
Set Up Time

tDAQ Carrier Detect


5V ¾ ¾ 14 ¾ ms
Acquisition Time

tDCH End of Data to Carrier


5V ¾ 8 ¾ ¾ ms
Detect High

2 S e c

0 .5 S e c
0 .5 S e c

R in g S ig n a l 0 1 0 1 0 1 .. 1 D A T A

tD O S C

R T IM E

R D E T

P D W N tS U P D

C D E T
tD A Q tD C H

D O U T R a w D A T A

D O U T C C o o k e d D A T A

X 1 3 .5 8 M H z

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HT9032

Functional Description
The HT9032 is designed to be the physical layer · Logical 0 (Space)=2100Hz
demodulator for products targeted for the caller · Transmission rate=1200bps
ID market. The data signaling interface should
Since the band pass filter of the HT9032 can
conform to Bell 202, which is described as fol-
pass the V.23 signal, hence the HT9032 also can
lows:
demodulate the V.23 signal.
· Analog, phase coherent, frequency shift keying
· Logical 1 (Mark)=1200+/-12Hz Ring detection
· Logical 0 (Space)=2200+/-22Hz The data will be transmitted in the silent pe-
· Transmission rate=1200bps riod between the first and second power ring be-
· Data application=serial, binary, fore a voice path is established. The HT9032
asynchronous should first detect a valid ring and then per-
form the FSK demodulation. The typical ring
The interface should be arranged to allow sim-
detection circuit of the HT9032 is depicted be-
ple data transmission from the terminating
low. The power ring signal is first rectified
central office, to the CPE (Customer Premises
through a bridge circuit and then sent to a re-
Equipment), only when the CPE is in an
sistor network that attenuates the incoming
on-hook state. The data will be transmitted in
power ring. The values of resistors and capaci-
the silent period between the first and second
tor given in the figure have been chosen to pro-
power ring before a voice path is established.
vide a sufficient voltage at RDET1 pin to turn
The transmission level from the terminating
on the Schmitt Trigger input with approxi-
C.O. will be -13.5dBm+/-1.0. The worst case at-
mately a 40 Vrms or greater power ring input
tenuation through the loop is expected to be
from tip and ring. When VT+ of the Schmitt is
-20dB. The receiver therefore, should have a
exceeded, the NMOS on the pin RTIME will be
sensitivity of approximately -34.5dBm to han- driven to saturation discharging capacitor on
dle the worst case installations. The ITU-T V.23 RTIME. This will initialize a partial power up,
is also using the FSK signaling scheme to with only the portions of the part involved with
transmit data in the general switched tele- the ring signal analysis enabled, including
phone network. For mode 2 of the V.23, the RDET2 pin. With RDET2 pin enabled, a portion
modulation rate and characteristic frequencies of the power ring above 1.2V is fed to the ring
are listed below: analysis circuit. Once the ring signal is quali-
· Analog, phase coherent, frequency shift keying fied, the RDET pin will be sent low.
· Logical 1 (Mark)=1300Hz

P D W N

2 7 0 k W R T IM E
V D D
P o w e r U p
0 .2 m F L o g ic

In te rn a l
4 7 0 k W R D E T 1 P o w e r U p
T o L o g ic
B r id g e
1 8 k W
R D E T
R D E T 2
R in g
A n a ly s is
1 5 k W C ir c u it
1 .2 V

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HT9032

Operation mode
There are three operation modes of the HT9032. They are power down mode, partial power up mode,
and power up mode. The three modes are classified by the following conditions:
Current
Modes Conditions
Consumption
Power down PDWN=²1² and RTIME=²1² <1mA
Partial power up PDWN=²1² and RTIME=²0² 1.9mA typically
Power up PDWN=²0² 3.2mA typically

Normally, the PDWN pin and the RTIME pin 1.9mA typically. Once the PDWN pin is below
control the operation mode of the HT9032. VT-, the part will be fully powered up, and ready
When both pins are HIGH, the HT9032 is set at to receive FSK. During this mode, the device
the power down mode, consuming less than 1mA current will increase to approximately 3.2mA
of supply current. When a valid power ring ar- (typ). The state of the RTIME pin is now a
rives, the RTIME pin will be driven below VT- ²don¢t care² as far as the part is concerned. Af-
and the portions of the part involved in the ring ter the FSK message has been received, the
signal analysis are enabled. This is partial PDWN pin can be allowed to return to VDD and
power up mode, consuming approximately the part will return to the power down mode.

Application Circuits

Application circuit 1

T IP V D D
0 .2 m F
~ 0 .0 1 m F 2 0 0 k W H T 1 0 5 0

9 V 0 .1 m F
~

0 .2 m F 4 7 0 k W
R IN G
0 .0 1 m F 2 0 0 k W T IP V D D
R IN G

D O U T
1 8 k W m C

1 5 k W
P D W N X 1 3 .5 8 M H z
V S S X 2 1 0 M W
H T 9 0 3 2 B /D
3 0 p F 3 0 p F

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HT9032

Application circuit 2

T IP V D D
0 .2 m F
~ 0 .0 1 m F 2 0 0 k W H T 1 0 5 0

9 V 0 .1 m F
~
4 7 0 k W
0 .2 m F
2 0 k W 2 0 k W
R IN G
T IP V D D
0 .0 1 m F 2 0 0 k W
R IN G D O U T C
R D E T 1 D O U T
1 8 k W R D E T 2 C D E T m C
R D E T
V D D R T IM E
P D W N
1 5 k W X 1 3 .5 8 M H z
2 7 0 k W V S S
X 2 1 0 M W

0 .2 m F H T 9 0 3 2 C
3 0 p F 3 0 p F

Application circuit 3

T IP V D D
0 .2 m F
~ 0 .0 1 m F 2 0 0 k W H T 1 0 5 0

9 V 0 .1 m F
~

0 .2 m F 4 7 0 k W
R IN G 2 0 k W
0 .0 1 m F 2 0 0 k W T IP V D D
R IN G

D O U T
1 8 k W m C

C D E T
1 5 k W
P D W N X 1 3 .5 8 M H z
V S S 1 0 M W
H T 9 0 3 2 F
3 0 p F 3 0 p F

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HT9032

Holtek Semiconductor Inc. (Headquarters)


No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C.
Tel: 886-3-563-1999
Fax: 886-3-563-1189
Holtek Semiconductor Inc. (Taipei Office)
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Tel: 886-2-2782-9635
Fax: 886-2-2782-9636
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Holtek Semiconductor (Hong Kong) Ltd.
RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong
Tel: 852-2-745-8288
Fax: 852-2-742-8657

Copyright ã 2000 by HOLTEK SEMICONDUCTOR INC.


The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek
assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are
used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications
will be suitable without further modification, nor recommends the use of its products for application that may pres-
ent a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior
notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.

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