MPC5554 Sci & Emios

- Motorola Power Controller
By
Sasi Kumar C
Development Engineer
TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

Sponsored by Dept. of Science & Technology, Govt. of India
Overview
The eSCI allows asynchronous serial communications with peripheral devices and other
CPUs.
The eSCI has special features which allow the eSCI to operate as a LIN bus master,
complying with the LIN 2.0 specification.

Features
• Full-duplex operation
• Standard mark/space non-return-to-zero (NRZ) format
• Configurable baud rate
• Programmable 8-bit or 9-bit data format
• LIN master node support
• Configurable CRC detection for LIN
• Separately enabled transmitter and receiver
• Programmable transmitter output parity
• Two receiver wake-up methods:
— Idle line wake-up
— Address mark wake-up
• Interrupt-driven operation
• Receiver framing error detection
• Hardware parity checking
• Two-channel DMA interface

Signal Description
SCI Transmit (TXDx)
This pin serves as transmit data output of eSCI.
SCI Receive Pin (RXDx)
This pin serves as receive data input of the eSCI.
Memory Map/Register Description

Register Definition
eSCI Control Register 1(ESCIx_CR1)

Register Definition

Register Definition

Register Definition

Register Definition
eSCI Data Register (ESCIx_DR)
NOTES
In 8-bit data format, only bits 8–15 of ESCIx_DR need to be accessed.
When transmitting in 9-bit data format and using 8-bit write instructions, write first to
ESCIx_DR[0–7], then ESCIx_DR[8–15]. For 9-bit transmissions, a single write may
also be used.

Register Definition
eSCI Status Register (ESCIx_SR)
The ESCIx_SR indicates the current status. The status flags can be polled, and some
can also be used to generate interrupts. All bits in ESCIx_SR except for RAF are cleared
by writing 1 to them.

Register Definition

Register Definition

Programming Steps: (Loop Back Mode)
(I) Initialization of system clock (lock the system clock by FMPLL)
1. Initialization of eSCI
2. Transmit Data
3. Read and Echo Back Data
(I) Initialization of system clock
a. Set System Clock
b. Wait Until PLL gets Lock
a. Enable the module of esCI
b. Initialize eSCI control.
c. Configure Pads
2. Transmit Data
a. Wait for Transmit Data Empty register Status Flag.
b. Clear Status Flag.
c. Load data to Data Register.
3. Reading the Echo back

a. Wait for Receive Data Full Register Status Flag to set
c. Read result from Data Register.

a. Set System Clock
Set System Clock [Synthesizer Control Register (FMPLL_SYNCR)]
For example, required Fsys = 64 MHZ

Reference Clock = 8 MHz
Hence low value to RFD = 0
PREDIV = 0
Hence, 64 MHz = 8 MHz x ( MFD + 4)
-----------------------------
((0 + 1) x 1)

a. Set System Clock
Hence,
MFD = ( 64MHz / 8MHz) – 4
= 4
Therefore,
MFD = 00100
RFD = 000
PREDIV = 000
FMPLL.SYNCR.R = 0x0200000;

while(FMPLL.SYNSR.B.LOCK != 1);

Module Disable
MDIS When 1 - Disable
0 - Enable
ESCI_A.CR2.R = 0x0000;

b. Initialize esCI Control
• Baud Rate value = 64 M / (16 × 9600) ~= 417 SBR = 417(0x1A1)

• Word length = 8 bits M=0
• Parity is not enabled PE = 0
• Enable transmitter TE = 1
• Enable receiver RE = 1
• Enable Loop Back mode LOOPS = 1
ESCI_A.CR1.R = 0x01A1800C;

c. Configure Pads
Pad Configuration Register (PCR)
The pin 89 is TXDA and the pin 90 is RXDA
Hence, these pins (pads) functionality can be configured by using SIU
(System Integration Unit)
3,4,5 - PA
SIU.PCR[90].R = 0x0400;
SIU.PCR[89].R = 0x0400;

2. Transmit Data
TDRE When
0 - No byte transferred to transmit shift register
1 - Byte transferred to transmit shift register; transmit data register empty
Hence, poll for 1.
while(ESCI_A.SR.B.TDRE == 0);
b. Clear the Status Flag.
To Clear, place TDRE=1.
ESCI_A.SR.B.TDRE = 1;

c. Load Data to the data register
ESCI_A.DR.B.D = txdata;
3. Reading the Echo back

a. Wait for Receive Data Full Register Status Flag to set
RDRF When
0 Data not available in eSCI data register
1 Received data available in eSCI data register
Hence, poll for 1.
while(ESCI_A.SR.B.RDRF == 0);
• Clear the Status Flag.

ESCI_A.SR.B.RDRF = 1;
To Clear, place RDRF=1.
c. Load Data from the data register eSCI Data Register (ESCIx_DR)
rxdata = ESCI_A.DR.B.D;

Program:
# include “MPC5554.h”
uint8_t recdata[10];
uint8_t j; ESCI_A.DR.B.D = txdata;
const uint8_t transdata[ ] = { “HELLO” };
void main(void)
{
SIU.PCR[90].R = 0x0400;
SIU.PCR[89].R = 0x0400;
while(1) {
for( j=0; j<size of(transdata); j++) {
rxdata[j] = ESCI_A.DR.B.D;
}
}
}

Programming Steps: (In Transmitter Side)
(I) Initialization of system clock (lock the system clock by FMPLL)

2. Transmit Data
3. Read and Echo Back Data
a. Set System Clock
b. Initialize eSCI control.
c. Configure Pads
2. Transmit Data
c. Load data to Data Register.

a. Set System Clock

PREDIV = 0
-----------------------------
((0 + 1) x 1)

a. Set System Clock
Hence,
MFD = ( 64MHz / 8MHz) – 4
= 4
Therefore,
MFD = 00100
RFD = 000
PREDIV = 000


Module Disable
0 - Enable


• Disable Loop Back mode LOOPS = 0

c. Configure Pads
The pin 89 is TXDA.
3,4,5 - PA
SIU.PCR[89].R = 0x0400;

2. Transmit Data
TDRE When
0 - No byte transferred to transmit shift register
1 - Byte transferred to transmit shift register; transmit data register empty
Hence, poll for 1. while(ESCI_A.SR.B.TDRE == 0);
To Clear, place TDRE=1. ESCI_A.SR.B.TDRE = 1;
c. Load Data to the data register


Program:
uint8_t j;
const uint8_t transdata[ ] = { “HELLO” };
void main(void)
{
SIU.PCR[89].R = 0x0400;
while(1) {
for( j=0; j<size of(transdata); j++) {
}
}
}

Programming Steps: (Receiver Side)
a. Set System Clock

PREDIV = 0
-----------------------------
((0 + 1) x 1)

a. Set System Clock
Hence,
MFD = ( 64MHz / 8MHz) – 4
= 4
Therefore,
MFD = 00100
RFD = 000
PREDIV = 000


Module Disable
0 - Enable


• Enable Loop Back mode LOOPS = 0

c. Configure Pads
The pin 89 is TXDA and the pin 90 is RXDA
3,4,5 - PA
SIU.PCR[90].R = 0x0400;

2. Receive Data
a. Wait for Receive Data Full register Status Flag.
RDRF When
0 Data not available in eSCI data register
1 Received data available in eSCI data register
Hence, poll for 1. while(ESCI_A.SR.B.RDRF == 0);
To Clear, place RDRF=1. ESCI_A.SR.B.RDRF = 1;
c. Load Data from the data register

rxdata = ESCI_A.DR.B.D ;

Program:
uint8_t recdata[10];
uint8_t j;
void main(void)
{
SIU.PCR[90].R = 0x0400;
while(1) {
for( j=0; j<10; j++) {
rxdata[j] = ESCI_A.DR.B.D;
}
}
}

Overview:
The eMIOS builds on the MIOS

concept by using a unified channel
module that provides a superset of the
functionality of all the individual MIOS
channels, while providing a consistent
user interface.

Features:
• 24 unified channels
• Unified channels features
— 24-bit registers for captured/match values
— 24-bit internal counter
— Internal pre scalar
— Dedicated output pin for buffer direction control
— Selectable time base
— Can generate its own time base
• Four 24-bit wide counter buses
— Counter bus A can be driven by unified channel 23 or by the STAC bus.
— Counter bus B, C, and D are driven by unified channels 0, 8, and 16,
respectively.
— Counter bus A can be shared among all unified channels. UCs 0 to 7, 8 to 15,
and 16 to 23 can share counter buses B, C, and D, respectively.
• One global pre scalar
• Shared time bases through the counter buses
• Synchronization among internal and external time bases
• Shadow FLAG register
• DMA request capability for some channels
• Motor control capability

Modes:
The eMIOS operates in one of the modes described below:
User mode
This is the normal operating mode.
When EMIOS_MCR[FRZ] = 0, and EMIOS_CCR[FREN] =0,
the eMIOS is in user mode.
Debug mode
Debug mode is individually programmed for each channel. When entering this mode, the
UC registers’ contents are frozen, but remain available for read and write access
through the slave interface.
After leaving debug mode, all counters that were frozen upon debug mode entry will
resume at the point where they were frozen.
In debug mode, all clocks are running and all registers are accessible; thus, this mode is
not intended for power saving, but for use during software debugging.


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- Motorola Power Controller

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

Memory Map/Register Description

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

In 8-bit data format, only bits 8–15 of ESCIx_DR need to be accessed.

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

3. Reading the Echo back

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

For example, required Fsys = 64 MHZ

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

eSCI Control Register 2(ESCIx_CR2)

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

• Baud Rate value = 64 M / (16 × 9600) ~= 417 SBR = 417(0x1A1)

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

Hence, poll for 1.

b. Clear the Status Flag.

To Clear, place TDRE=1.

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

3. Reading the Echo back

• Clear the Status Flag.

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

(I) Initialization of system clock (lock the system clock by FMPLL)

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

For example, required Fsys = 64 MHZ

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

eSCI Control Register 2(ESCIx_CR2)

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

• Baud Rate value = 64 M / (16 × 9600) ~= 417 SBR = 417(0x1A1)

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

Hence, poll for 1. while(ESCI_A.SR.B.TDRE == 0);

b. Clear the Status Flag.

To Clear, place TDRE=1. ESCI_A.SR.B.TDRE = 1;

c. Load Data to the data register

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

For example, required Fsys = 64 MHZ

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

eSCI Control Register 2(ESCIx_CR2)

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

• Baud Rate value = 64 M / (16 × 9600) ~= 417 SBR = 417(0x1A1)

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

TIFAC - CORE IN AUTOMOTIVE INFOTRONICS, VIT

Hence, poll for 1. while(ESCI_A.SR.B.RDRF == 0);

b. Clear the Status Flag.