Design of a 60 GHz Receiver front-end in 90nm CMOS

MM wave IC design Final Project

Anandaroop Chakrabarti (ac3215)
Jian Chen (jc3659)
Dept. of Electrical Engineering
Columbia University
Fall 2010
 Technology characterization:

Device characterization for the particular technology is important since it enables us to get an approximate estimate of the
various device parameters (Cgs,Cgd, NF) etc which can then be utilized to get a preliminary design.

The test benches for various simulations are shown below:

1. DC characterization

The DC parameters of the device are (gm,sat/W),

m,sat/W), r0,r_linear,Vth. These can be obtained by sweeping Vds & Vgs (each
from 0 to 1.2V),, plotting Ids & using the following relationships:

∂I ds
gm = , Vds = const (1.1)
∂Vgs

∂I ds
r0 = , Vgs = const (1.2)
∂Vds
 k1
rlinear = ,Vds ≈ 0 (1.3)
Vgs − k2

1
λ= (1.4)
r0 I ds

Eqns. 1.1 & 1.2 are to be evaluated in saturation while eqn 1.3 is evaluated in linear region of operation. We are interested
g m, sat
in knowing which can be obtained from the flat region of the plot of gm vs Vgs. Similarly, r0 can be obtained from
W
∂I ds
the values of at high values of Vds & Vgs>Vth. Strictly speaking, for short channel devices, eqn. 1.3 is not valid,
∂Vds
but to keep things simple, k2 in eqn. 1.3 can provide an approximate estimate of the threshold voltage.

An NMOS device with Wf=1um & nf=1 was used for characterization.

g m, sat
A.
W

8.00E-04

7.00E-04

6.00E-04

5.00E-04

4.00E-04

3.00E-04

2.00E-04

1.00E-04

0.00E+00
0 0.2 0.4 0.6 0.8 1 1.2 1.4
-1.00E-04

Id vs Vgs
 1.40E-03

1.20E-03

1.00E-03

8.00E-04

6.00E-04

4.00E-04

2.00E-04

0.00E+00
0 0.2 0.4 0.6 0.8 1 1.2 1.4
-2.00E-04

g m − vs − Vgs (lower curves, without saturation, have been eliminated)

g m, sat 1.1mA / V
∴ ≈ = 1.1mA / V − µ m
W 1µ m

B. λ

8.00E-04

7.00E-04

6.00E-04

5.00E-04

4.00E-04

3.00E-04

2.00E-04

1.00E-04

0.00E+00
0 0.2 0.4 0.6 0.8 1 1.2 1.4
-1.00E-04

Id vs Vds
 3.50E+09

3.00E+09

2.50E+09

2.00E+09

1.50E+09

1.00E+09

5.00E+08

0.00E+00
0 0.2 0.4 0.6 0.8 1 1.2 1.4

r0 − vs − Vds
Considering the region of Vgs beyond 0.5V (below which device is in sub-threshold), we get
Vgs(V) Vds(V) λ ( V −1 )
0.8 0.8 .247
1 0.8 .205
1.2 0.8 .201
0.8 1 .213
1 1 .173
1.2 1 .158
0.8 1.2 .199
1 1.2 .158
1.2 1.2 .139

Hence, λavg =0.188 V −1

C. rlinear *W − & − Vth

The resistance in linear region was found to remain constant from Vds=0 to Vds=0.024V. thus, by using different
values of Vgs, we get different resistance values which can be used to calculate k1 & Vth
Since we also require a high Vgs value in linear region, the parameters were evaluated from resistance values
corresponding to Vgs=1V & Vgs=1.2V.
Vgs 1V 1.2V
R_linear 511.1 408.9
K1 408.9
K2=Vth .2V
R_linear*W,avg 460 Ω − µ m

Using 2 more Vgs values, we get

Vgs .8V 1V
R_linear 732.9 511.1
K1 337.76
K2=Vth .339
R_linear*W,avg 622 Ω − µ m
 Thus, the threshold voltage of the device is probably around Vth=.3V, while R_linear*W,avg can be estimated to
be about Ron*W=550 Ω − µ m
2. AC characterization
Modeling the MOS device with rg,Cgs,Cgd,Cdb,gm & r0, it can be shown that the 2 port Y parameters of the
device are given by the following Y-matrix:
 1 
 s (C + C ) −(rg || ) 
sC gs
 gs gd

 srg (C gs + Cgd ) + 1  1 1  
 rg  + (rg || ) 
 y11 y12    sC gd sCgs  
Y = = 
 y 21 y 22    1 
g (
 m g sCr || ) + 1 
 g m − sC gd 1
 + sCdb +  gs

 srg (C gs + Cgd ) + 1 r0  (r || 1 ) + 1  
  g sC sCgd  
 gs

Consequently, all the parameters can be calculated by simple mathematical manipulation.

The Y parameters are plotted across different frequencies & a MATLAB code is used to fin the parameter values
at 60 GHz.
In saturation, for NMOS device of Wf=2.5um & nf=1, with Vgs=0.8V & Vds=1.2V
Cgs=2.49fF, Cgd=0.894fF, Cdb=2.55fF, r0=4.63K Ohms, gm=2.42mA/V, rg=20.65 Ohms
C gs C gd Cdb
Hence, = 1 fF / µ m , = 0.3576 fF / µ m , = 1.02 fF / µ m
W W W

3. MAG, NFmin, fmax simulations

For an NMOS device with Wf=1um & Vds=1.2V (to ensure saturation always), the relevant parameters at 60
GHz are tabulated below:
nf(no. of fingers) Vgs NFmin(dB) MAG(dB) fmax(GHZ)
10 0.7 .417 8.276 816
1 0.7 .42 8.276 900
10 1 .45 9.169 850
1 1 .45 9.169 937

For an NMOS device with Wf=2.5um & Vds=1.2V (to ensure saturation always), the relevant parameters at 60
GHz are tabulated below:
Nf(no. of fingers) Vgs NFmin(dB) MAG(dB) Fmax(GHZ)
10 1.051 .417 9.14 380
1 0.7 1 8.19 333
10 1 1 8.19 348
1 1 1.043 9 377

4. fT simulation
For an NMOS device with Wf=1um & Vds=1.2V (to ensure saturation always), the unity gain frequency values at
60 GHz are tabulated below:
nf Vgs fT(GHz)
10 1 141.8
1 0.7 111.84
1 0.7 113
10 1 132
 For an NMOS device with Wf=2.5um & Vds=1.2V (to ensure saturation always), the unity gain frequency values
at 60 GHz are tabulated below:

nf Vgs fT(GHz)
10 1 143
1 0.7 112
1 0.7 110
10 1 140

5. Noise corner ( f 1 ) & γ calculation

f

For an NMOS device of Wf=1um, nf=10 & Vds=1.2V (to always ensure saturation):
I nd2
Drain − current − thermal − noise = = 4kT γ g d 0
∆f

Where gd0 is the drain-source conductance at zero drain-source voltage & can be obtained from DC
characterization. This expression can then be used to calculate γ
Drain thermal noise (A^2/Hz)
Vgs 1KHz 10KHz 1 γ
gd 0
0.7V 1.1706e-22 1.1706e-22 974.6/10 0.689
1V 2.0371e-22 2.0371e-22 511.1/10 0.628
1.2V 2.49565e-22 2.49565e-22 408.9/10 0.616

Flicker Noise (A^2/Hz)

Vgs Gm(mA/V) 1KHz 10KHz 100KHz 1MHz 10MHz 100MHz 1GHz 10GHz
0.7V 8.637 5.949e- 6.5686e- 7.2523e- 8.007e- 8.84e-21 9.76e-22 1.077e-22 1.1989e-
17 18 19 20 23
1V 11.06 1.8064e- 1.994e-17 2.2019e- 2.43e-19 2.684e- 2.9635e- 3.27196e- 3.6125e-
16 18 20 21 22 23
1.2V 11.75 2.855e- 3.15216e- 3.4802e- 3.8425e- 4.2424e- 4.6839e- 5.1714e- 5.7096e-
16 17 18 19 20 21 22 23

Flicker noise corner calculation:

( flic ker − noise @ f 0 ) * f 0
f1 =
f Drain − thermal − noise
f1 f1
,simulated ,theory
f f

Vgs 1KHz 10KHz 100KHz 1MHz 10MHz 100MHz 1GHz 10GHz

0.984GH 0.7 0.508GH 0.56GHz 0.619GH 0.684GH 0.755GH 0.8338GH 0.9205GH 1.016GH
z V z z z z z z z
0.985GH 1V 0.887GH 0.9788GH 1.081GH 1.19GHz 1.317GH 1.455GHz 1.606GHz 1.773GH
z z z z z z
1.085GH 1.2 1.144GH 1.263GHz 1.395GH 1.539GH 1.699GH 1.877GHz 2.072GHz 2.287GH
z V z z z z z
As can be seen, the theoretical flicker noise corner varies significantly from the simulated value. The plots for
flicker noise corner for Vgs=0.7V, 1V & 1.2 V are shown below, in that order:
VCO design
Desired Characteristics

1. Center frequency =60 GHz

2. Phase noise <=-90dBc/Hz @ 1MHz offset
3. Tuning Range>7% with buffer

Design procedure

1. Choice of topology
The cross-coupled LC oscillator is the most widely used choice for the oscillator core, the main reason being
better phase noise performance. With a sufficiently high-Q LC tank, good phase noise performance of the
oscillator can be achieved. The cross-coupled LC oscillator topology is shown below.

The idea is to cancel out the loss in the tank (due to finite quality factors of L &C) by the power supplied by the
active devices. Thus, for oscillation, we require:

1
ω0 = (1.1)
LC

&

g m RL > 1 (1.2)

If we incorporate device parasitic, a more accurate representation of the circuit would be :

 Consequently, the design equations are modified as:

1 RL (C + C gs + 4C gd )
2

ω0 = 1− (1.3)
L(C + C gs + 4C gd ) L

&

1 RL (C + C gs + 4C gd )
gm ≥ + (1.4)
rds L

At mm-wave frequencies, the capacitance isn’t put separately into the circuit, but is contributed by the device
parasitics only. Also, rg needs to be taken into account for a more accurate design formulation.
The phase noise of a cross-coupled LC oscillator can be expressed as:

 π 2 kT γ  ω0  2 
L(∆ω ) = 10 log10  2 2    (1.5)
 4 I bias RQ  ∆ω  

It would be worthwhile to consider some design tradeoffs at this point.

Assuming that the oscillator operates in the voltage limited region, the differential output voltage is
2 
Vout , diff = 2VDD =  I bias R 
π 
A. If Q increases, then R increases as well for a given L. Hence to maintain the same output voltage, I bias
decreases. This implies that phase noise improves linearly
 R
B. For a constant Q, Q = . Hence, if L decreases, R decreases as well. Consequently, I bias & C increases to
ω0 L
maintain same output voltage & oscillation frequency. Thus, Phase noise improves linearly, but at the expense
of linearly increasing power.

Clearly, phase noise depends to a large extent on the quality factor of the frequency selective network, which is a measure
of its ability to reject out-of-band frequency components. Since the quality factor of on-chip spiral inductors at mm-wave
frequencies is quite low, an alternative to spiral inductors would be to use transmission lines as inductive components.
The microstrip transmission line provided in the design kit was used to implement the frequency selective network. This
stems from the fact that a short circuited quarter wave Tx-line can act as a 2nd order LC tank.

The important parameters of the Tx-line are its RLCG parameters which were extracted from the input impedances with
the Tx-line terminated separately by a short ckt & an open ckt. The relevant equations are:

Z in , short − ckt = Z 0 tanh(γ ℓ) (1.6)

Z in ,open − ckt = Z 0 coth(γ ℓ) (1.7)

Thus,

Rline + jω Lline x
Z0 = = (1.8)
Gline + jωCline y

γ = ( Rline + jω Lline )(Gline + jωCline ) = xy (1.9)

∴ Z 0γ = x
γ (1.10)
& =y
Z0

Rline = Re al ( x)
Gline = Re al ( y )
Im ag ( x)
Lline = (1.11)
ω
Im ag ( y )
Cline =
ω
γ = α + jβ
β (1.12)
Q=
2α

The microstrip Tx-line was simulated for a length of 1200um (approx quarter wave at 60 GHz) with varying widths in
order to estimate its characteristics impedance & Quality factor (MATLAB code attached). The test bench & relevant
plots at 64 GHz are shown below:
Clearly
ly the quality factor is poor & hence in the presence of large device parasitic, a much shorter length of line has to be
chosen for functionality.

2. Design steps
As a starting point for the design, the parasitic capacitances were estimated from Y parameter characterization, for a
device with 1 finger & finger width=1um. The capacitances are expected to scale linearly with width, but not rg. Ibias was
implemented using a PMOS current source to reduce its noise contribution. To keep power consumption to a minimum,
an Ibias of 2mA was chosen at the outset. Since Vgs=Vds~1V, the gm found from DC characterization was ~1mA/V for
a device with 1 finger of width 1um. With a device of 10 fingers, the gm would be 10 times higher. Thus, with a startup
RL
gain of 4, eqn. (1.2) yields RL ≥ 400Ω . Since Q = , this gives L ≈ 35.37 pH at 60GHz.The resultant circuit was
ωL
found to have decaying oscillations & hence Ibias had to be bumped up to 5mA to get better startup conditions. Also, the
device size had to be changed from 10 fingers to about 16 fingers to reduce the oscillation frequency to ~60GHz. Next,
the quarter wave microstrip Tx-line was inserted instead of the inductor. The resultant circuit was found to have
oscillation frequency of ~ 35 GHz owing to additional parasitic of the line. Consequently, a shorter length of line was used
for optimal performance. The width of the line was also adjusted to get appropriate functionality.

The actual length of line used in the design was with l=150 um & w=1um. Its characteristics are shown below, at 64 GHz:

Next, the ideal current source was replaced by PMOS current source & the devices were sized so as to supply the desired
bias current of ~5mA.

3. Frequency tuning

For frequency tunability, NMOs varactors were used. To get logical Q=5 for varactors at 60GHz, an external source-
drain resistance was added in series with the Control voltage (as shown below) while characterizing the varactor.
For a device with finger width=1um & 50 fingers , the additional series resistance was found to be ~60 Ohms at 60 GHz.
The resultant varactor had a maximum Q of 5.842 when the gate bias & control voltage were both at 0 volts, &
Cmax
= 1.73 at 60 GHz. A large number of fingers were chosen to increase the tuning range & meet the desired specs.
Cmin

Finally, a tuned buffer was placed at the output to isolate the VCO core from the input characteristics of the next stage
(mixer). Thee buffer was designed using a cascode stage to achieve better unilaterization (along with higher gain) between
VCO output & buffer output.

The final schematic of the VCO is shown below:

The various device sizes & parameters are delineated next:
next

A. Core NMOS: Wf=1um, nf =12

B. Buffer NMOS:
1. Top device: Wf=1um, nf=97
2. Bottom device: Wf=1um,nf=5
C. Current source PMOS devices:
1. Diode-connected
connected PMOS: M=2
2. Tail PMOS : M=200
3. Biasing resistor: 1.5K Ohms
D. Tx-line: W=1um, L=150um
E. Varactor NMOS: nf=50, series resistance
resistance=60 Ohms

The VCO performance is summarized below:

Operating frequency: 56.23GHz to 63.03 GHz

Power consumption: 15.73mW including buffer

Phase noise @ 1MHz offset: -86.78dBc/Hz

86.78dBc/Hz @63.3 GHz & -89.2dBc/Hz @ 56.13 GHz

Tuning range: 11.4%

The tuning characteristics

racteristics of the VCO are shown below:
This clearly shows that the tuning characteristics is non-linear & also, beyond Vctrl=0.6V, there is not much change in
frequency.

The phase noise plots at 56GHz & 63 GHz are shown below, in that order:
The buffered output waveforms at the two extreme frequencies are shown next:

1. 56 GHz

2. 63 GHz
 Critique of the present design:
1. The buffer output swing is low
2. The best case phase noise doesn’t meet the specifications
3. The power consumption is rather high

Possible solutions:

1. The phase noise performance can be improved by using switched capacitor banks to implement coarse tuning
range, while the fine tuning can be accomplished by a smaller varactor. Varactors convert amplitude noise to
phase noise & hence larger the varactor, larger is its contribution to phase noise. At present, the tuning range
is much more than required. So by reducing the tuning range, phase noise specifications can be met.
2. The buffers need to be appropriately sized to improve the output swing.
3. Finally, the spiral inductors from ASITIC were found to have a much larger Q (~30, as compared to Q=18 for
microstrip) than the Tx-line. Hence using those is likely to improve phase noise performance.
 Low Noise Amplifiers

Preliminary Design Considerations

The overall receiver linearity of the receiver front end is -30dBm. Since the mixer was designed before the
LNA, the power gain of the LNA can then be determined based on the -1dB compression point of the mixer.
The doubly-balanced mixer provides a linearity of about -10dBm. Then the power gain of the overall LNA
block should be 20dB or less. If the power gain is greater than 20dB, the signal will be compressed at the mixer
block.

A three-stage LNA design is considered in this scenario, with the power gain of each stage being no more than
7dB. It also must be ensured that each stage has a reasonable linearity so that the signal does not get compressed
at any of the three stages (particularly in the last stage). Hence, ideally, the linearity should be increased for
each successive stage. Generally speaking, the gain of the LNA block should not be too high so that the design
of the mixer in terms of linearity becomes less demanding.

Design Procedure and Simulation

The design of the three-stage LNA begins with the first stage, and each stage is of cascode topology. The top
cascode transistors are biased at VDD, while the bottoms ones serve as the input of each stage.

Inductive Source Degeneration

For the first stage it is sensible to consider minimizing noise in the design, based on the Noise Chain Rule.
Hence, in addition to using cascode, the inductively degenerated common-source LNA topology is adopted. The
gain of this stage will be reduced due to the source degeneration. The gain of the subsequent stages must be
increased accordingly in order to achieve the 20dB goal.

From the derivation in class, assuming the source impedance to be matched is 50 Ω, the source degeneration
inductor can be determined by:



 =  ∙

However, it is observed in the simulation that the predicted Ls value can have a deviation of as much as 15 Ω in
the real part of the input impedance. This can be explained by the fact that other parasitics, such as Cgd, were
not considered in the derivation of this equation. Based on the measured input impedance, the Ls inductance is
adjusted to meet the 50 Ω. Another inductor Lg is placed at the gate of the bottom transistor to cancel the
imaginary part of the input impedance.

However, the 50Ω value may not be necessarily the optimal impedance for both power and noise matching. It is
chosen in this case for the ease of design, since the impedance of the antenna is also given 50Ω.

Device Sizing
Assuming the device is biased to the point of velocity saturation, so that Cgs becomes just the function of
device width and that ωT = gm / Cgs is relatively constant and independent of the width. For the optimal Cgs that
minimizes the Noise Figure, the expressions derived in Homework 3 can be used:

5 5
  = 1 + + 2 
 

1
  =
   

For the 90nm technology, γ = 2, δ = 4, c = 0.395. The resultant optimal Cgs is then about 63fF. If 2.5µm-finger
width devices (per-width Cgs = 2.489fF) are used in implementing the LNA, then there should be about 25~30
fingers in each device. In this design, each of the six transistors has 30 fingers. (Of course, Ls and Lg are chosen
to match 50Ω at this device size.)

The resultant first-stage amplifier is given in the figure below. The DC gate bias is 600mV.

Stage Output Matching

It is also desirable to achieve inter-stage matching to ensure maximum power transfer between stages and at the
output. Therefore, a matching network needs to be positioned at the output node of each of the N-1 stages to
match to the input impedance of the next stage. In this case, a shunt inductor (between VDD and the drain node)
is needed to also give output gain. Then a series capacitor is placed to complete the network. The values of
shunt inductor and series capacitor are determined by the input impedance of next stage.

Input Matching and the Middle Inductor

(Unless otherwise noted, the inductor vlaues

An inductor is placed between the two cascoded transistors in order to boost gain. In this design, the value of it
can range from 40pH to 230pH depending on the amount of gain desired. It is observed that the placement of
the middle inductor has little influence in changing the output matching conditions, possibly due to the isolation
from the top cascode transistor. However, placing the middle inductor will alter the input matching to a certain
extent, depending on the size of this inductor. Therefore Ls and Lg must be adjusted accordingly to maintain the
input matching, but changing Ls will in return vary the gain of the LNA. A trade-off point must be appreciated
for a desired gain and input matching condition.

A table documenting the final matching network configurations for all three stages is given as:

First stage Second stage Third stage

Ld 109pH 96pH 166.4pH
Ls 98.12pH N/A N/A
Lg 83.51pH N/A 45.4pH
Zin 36-j10 8.8-j65 6.2-j62

The schematics of the second and third stages are also given below. Initially all three stages have middle
inductors, and the configurations of the 2nd and 3rd stages are identical, but adjustments have been made
according to the first few simulation results. This configuration will be explained in the “Simulation Results”
section.

Simulation Results

S-parameter simulation is employed to measure the per-stage and overall LNA power gain and noise, as well as
to verify the input and output matching conditions. Transient simulation is used to find the -1dB compression
point. Power gain can also be measured using transient, and under perfectly matched condition, the power gain
measured by transient should match that by the S-parameter.

The initial simulation results of the per-stage LNAs are given below:

First stage Second stage Third stage

Power Gain 6.1dB 10.34dB 11dB
Noise Figure 3.65dB 2.781dB 3.03dB
S11 -17.39dB -15.57dB -14dB
S22 N/A -12.15dB -14.4dB
-1dB CP -9dBm -16dBm -16dBm

The problem with this performance is that the gains of the 2nd and 3rd stages are too high, and the linearity of the
third stage is not good enough, such that the signal is already compressed at the 3rd stage.

To alleviate this problem, the size of the inductor of the 3rd stage is reduced by about 10pH (from 60pH to
50pH) in order to lower the gain. As mentioned previously, the input impedance of this stage is changed as a
result. Since the amount of inductance reduction is not large, the real part of the impedance is only changed
slightly. An inductor is placed at the input to compensate for the variable in the imaginary part. The DC bias is
also reduced from 600mV to 550mV to lower the gain.

After the first adjustment, the signal at the 3rd stage won’t be compressed, but the gain of the LNA is still too
high such that the signal will be compressed in the mixer. Hence, second adjustment is made by eliminating the
middle inductor and lowering the DC biasing at the second stage to reduce the gain from 10.4dB to 6.5dB. (The
output matching network of the first stage is adjusted accordingly).

The adjustments made ensures that the input signal will not be compressed anywhere in the receiver. The final
per-stage and overall LNA performances are summarized in the table below.

First stage Second stage Third stage Cascaded

Power Gain 5.6dB 6.52dB 9dB 20dB
Noise Figure 3.7dB 3.7dB 3dB 4.44dB
S11 -17.4dB -19dB -17.6dB -17.31dB
S22 -11.5dB -22dB -20dB -15.85dB
-1dB CP -9dBm -10.5dBm -14dBm -25.6dBm

It was observed that the linearity of the 2nd and 3rd stage amplifiers was improved after reducing the DC bias.
This contradicts with the theoretical drain current expression in saturation region.

1
 =    ! "#$%& − #( + #% )*
2

The output stays linear if the Vbias – Vth term is much larger than Vin. Increasing the drive will then increase the
linearity of the circuit. This observation can be explained by the fact that, before the adjustments, the gains of
the 2nd and 3rd stage amplifiers were too high, leading to large swings at the output of each, causing the linearity
to become output-limited.

(Performance of the cascaded LNA)

(-1dB Compression Point of the Cascaded LNA)
 Mixer
Preliminary Design Considerations
Although there is no specific feedthrough requirement in this project, we would like our system to have good
signal quality. Hence the doubly-balanced mixer architecture has been chosen to eliminate the LO feedthrough.
The complete mixer circuit structure is shown below:
Design Procedure
RF Transistors Design

The starting point of the design is the mixer voltage conversion gain:

2
#+ =
-
,
However, the problem with this expression is that it is a rather rough estimation of the voltage conversion gain.
Since each single-ended half of this entire circuit structure is a quasi-inductively degenerated common-source
(IDCS) amplifier, we can therefore use the effective IDCS Gm derived in class to arrive at a more accurate

voltage conversion gain expression. (The IDCS configuration was also chosen for noise consideration.)

+
=
2 

∙ -
#+ =
, 

For our design, the VCG is initially decided to be 5dB. Hence, the preliminary load resistance RL is calculated
to be 177Ω, given from characterization that ωT = gm / Cgs = 2π(125GHz), and assuming Rs = 50Ω. For the
chosen device size (2.5µm x 10), the effective Cgs = 25fF from the characterization data, and the resultant gm is
about 20mS. Then the RF devices are biased accordingly (Vbias = 800mV).

Input Matching

The source degeneration inductor and gate inductor are chosen in the same fashion described in the LNA
chapter. Under matched condition, it is expected to see the voltage swing at the input of the mixer being half of
the source input. In this design simulation, the source voltage swing is set at 100mV. Hence the differential
voltage swing is 50mV, and the mixer input should be about 25mV for matching, as shown on the graph below
(the Vin swing is about 23.1mV).

For 2.5um RF devices of 10 fingers (each), the resultant Ls and Lg values are 45.41pH and 128.9pH
respectively.
LO Transistors Design

The LO transistors are driven by the output of the VCO. Hence the DC biasing the LO is about the level of VDD
(1V ~ 1.2V), and the AC swing is 500mV max, based on the simulation result from the VCO. The size of each
LO transistor is chosen to be (2.5um x 20) for 10-finger RF devices.

The sizing the LO transistors involves considering the switching speed of these transistors, as well as the
voltage at the mixed node. The size of the LO transistor should be small enough for the given swing such that
they can have fast switching (or sharper Idiff transition slope, given by Ibias / gm in class). At the same time, their
size should also be large enough so that the voltage drop at the mixed node (VDS for the RF transistors) is
sufficient to keep RF transistors in saturation region during the mixer operation.

The size of the LO transistors must also be increased/decreased linearly with the sizing variations of the RF
transistors to avoid the velocity saturation at the LO transistors, which limits the voltage gain.

Simulations

The voltage gain and linearity of the mixer (10-finger RF devices) is given below:
The small-signal voltage conversion gain of this mixer design is about 10dB, and the -1dB compression point is
about -10dBm. The resultant VCG is much higher than the pre-determined value is because various gain-
boosting techniques have been employed in the design:

• Placement of Lres. Inductors are placed at the mixed node to cancel out the parasitic capacitances.
Through parametric sweep, and optimal inductor value that gives highest voltage gain based on the
given configuration can be found.
• Increasing RL. The load resistors can be increased to some reasonable extent (from the VCG equation)
to boost gain, but it should not be increased for too much that results in severe linearity degradation (RF
transistors can go to triode region with too-large RL).
• Current stealing. By placing PMOS devices at the mixed node to give extra current through the RF
transistors to boost gain, while the size of LO transistors can then be reduced without losing switching
speed. Lres value should be adjusted accordingly after placing the PMOS.

Future Task:

• One thing to explore is to replace the load resistor RL with active devices (PMOS). The load resistance
will then be represented by the ro of the PMOS devices, which can be in the kilo-ohm range. This can
significantly increase the gain of the mixer without having too much voltage drop across the load, which
causes linearity degradation.
• From the Vin = Vac / (2ωCgsRs) equation, it is expected that increasing the size of the RF transistors
can increase linearity (decrease gain), with all other things being equal. This trend is to be explored.
Baseband Amplifier
A differential baseband amplifier with unity voltage gain is constructed at the end of the receiver to be
connected with the mixer. The differential inputs of the baseband are connected with the outputs of the mixer.
Each resistor is of 100Ω. The device size is 25µm (2.5µm x 10).

The power gain (of the mixer) is given by

#567 * 
.+ = 10 log34 " ∙ )
#89 * -

Since the mixer is driving a larger RL than the baseband amplifier is, the resultant output resistance will become
that of the baseband amplifier (in this case, 100Ω) once these two components are connected together, leading
to an improved power gain.
Receiver System
The performance of the receiver after combing the components is given on the plots below:
Since the LNA was designed to be single-ended, and we have a mixer with differential inputs, the mixer was
configured in the quasi-differential fashion, leading to the LO feedthrough at the output of the receiver, as
shown on the graph above.

With the output load being 100Ω and input impedance being 50Ω, it is expected that the voltage gain is 33dB
(equivalent to 30dB power gain). However, our receiver achieved only 29dB voltage gain. Improvements on the
overall gain can be made by adjusting gains of one or more stages of the LNA and/or the baseband amplifier.

Besides the power gain, all other performance matrices have met the design requirements.
Full System Schematic
Full system floor plan