25

CMOS/SOS VLSI TECHNOLOGY

TAI SATO, JUN IWAMURA, HIROYUKI TANGO AND KATSUYUKI DOI

Toshiba Corporation, Kawasaki, JAPAN

ABSTRACT

CMOS is considered as a prospective technology in the VLSI era because

of its low power consumption and high driving capability. While ordinary
bulk silicon CMOS devices are inferior to SOS CMOS devices in chip area,
operation speed and latch-up problem due to the need for isolation wells.
SOS is an inherent good partner of the CMOS circuits owing to the simple and
perfect isolation. SOS technology, however, has the problem of high wafer
cost. Consequently, SOS technology is best applied to high performance logic
devices. Latest results of 8k-gate CMOS/SOS gate array and 16xl6bit
multipliers show 0.87ns 2-NAND gate delay and 27ns multiplication time,
respectively, which compete with ECL devices. Application of SOS devices
down to Ipm is also promising for very high speed operation. A 78ps gate
delay is achieved by double solid phase epitaxy and 1pm technology.

INTRODUCTION

Silicon on sapphire technology was initiated by Manasevit and

Simpson[l] in 1963. From that time SOS technology advanced as shown in the
Table 1.
TABLE 1. SOS TECHNOLOGY

1963 Idea of SOS ( Manasevit and Simpson

1971 SOS Wafers Commercially Available
1973 3-inch SOS Wafers
1975 1k CMOS RAM ( RCA
1976 16-bit Microprocessor ( HP
1977 4k CMOS RAM ( RCA )
1978 8-bit High Speed Microprocessor ( RCA
16-bit 7000 Gate Microprocessor C TOSHIBA
1979 16k CMOS RAM ( RCA )
SOS Solid-phase Epitaxy ( HP
1980 4-inch SOS Wafers
16-bit High Speed Microprocessor ( TOSHIBA
1981 SOS Double Solid-phase Epitaxy C TOSHIBA
16-bit Multiplier-Accumulator C TOSHIBA
1982 5-inch SOS Wafers ( KYOCERA )
1984 8k-gate SOS/CMOS Gate Array ( TOSHIBA
This paper deals with VLSI application of CMOS/SOS. Material aspects of
SOS films and process are also overviewed. Then CMOS/SOS processes are
reviewed. Concerning the bulk vs. SOS issues, some examples of the
comparison will be shown. Recent high performance devices such as 8-k gate
gate array and 27ns multiplication time 16bit multiplier are examined. They
compete with ECL devices. Then 1Iam design rule high speed CMOS device
characteristics and the device downward scaling are discussed. Finally, the
direction of SOS technology and remaining issues of SOS will be discussed.

MATERIALS

An SOS technology depends on sapphire and silicon quality. The

problems of SOS films are:

Mat. Res. Soc. Symp. Proc. Vol. 33 (1984) CElsevier Science Publishing Co., Inc.
26

1) Impurity introduced from sapphire films.

2) Imperfection of crystal due to the mismatch of crystalline
constants.
3) Thermal expansion difference of Si and sapphire film causes large
residual strain after cooling.
The mobility difference of bulk MOS and SOS MOS can be attributed to these
defects. The study of residual strain can explain the mobility ratio
difference of bulk and SOS MOS. In the bulk MOS, (100) surface is known to
show the highest electron mobility and the lowest hole mobility[2] among
other surfaces. On the other hand, in the SOS (100) surface, the compressive
stress is applied to silicon surface and the population of kx and ky
electron ellipsoids becomes more than kz ellipsoids as shown in Fig.1. Thus
#Kit Fig.1 Si conduction band
Y structure under strain

KY
uniform an: or-
Uo: 3-4x I16- Kx Si oonductlon ban

K,,Ky. Kz ,E
KX,Ky
unStralned uniformly stramnd
(compressive)

the effective mass in the inversion field becomes heavier than usual bulk
one which populates kz ellipsoids. On the contrary , hole effective mass
becomes lighter under compressive stress. These effect result in lower
electron and comparable hole mobility compared to bulk MOS[3,4]. Residual

700
-- NOSi IMPLANTED $i1',0.-22pm
"-"---- Si IMPLANTED0,.. %, 550 Fig.2
600' ,,..• 190keY, I x 1O"7=m2 Effective
E
U "4z10
.oO V .-
I
/cm"
WL a,50#m/5Opm
I VD I uO.IV mobility
500 of SOS

g. Q MOS FET
•--.,...,.,,..__ .0 ,-

:3
I--
400 •-- N-CHANNEL
300
,ti
200 "-'"----.----- P-CHANNEL

I.--
2U
100
IiJ
i•il I i I i i i l I I -

WO0 1 2 3 4 5 6 7 8 9 10
VG -VT (V)
stress can be reduced by solid phase epitaxy at low temperature. Figure 2
shows effective mobilities of n- and p- channel transistors. The dotted
lines show Si-implanted and regrown transistor mobilities. Large increase of
n-channel mobilities after regrowth is partly due to the relaxation of
 27

stress.
Silicon film has high density of imperfection. These imperfections can be
reduced by silicon ion implantation followed by high temperature
annealing[5]. Double solid-phase epitaxy [6,7) is a combination of a deep
silicon implantation and shallow silicon implantation. Process sequence of
the double SPE is shown in Fig.3. For 0.3pm silicon films, 1 sil* on sapphire
interface is amorphized by first silicon implant of Ixi0 /cm at 180keV.
Then, it is anneal ir N for 20 minutes at 1000 ° C. Second silicon
implantation of 2xi0 /cm done at 100keV for surface region amor-
phization. Subsequent annealing induces a second regrowth from the silicon-
sapphire interface region towards the silicon surface. By •oub e solid 7 pha e
epitaxy defect density of silicon film is reduced from 10 /cm to 10 /cmr.
As a result, effective mobility of electron of DSPE is about 1.3 times as
high as those of as-grown epi-film as shown in Fig.2. Effective mobility of
p-MOS is improved about 1.1 times as shown in Fig.2. Leakage current is also
reduced as shown in Fig.4.

10-5
(a0 as-grown film •Sopph ire
tsi =0 3pm

(b)Si implaniation near

the Si-sapphire interface
190keV , I x 10/cmZ SI÷ I-
z
(11 annealing
1)I

n-

(dWSiimpimtation near AmAmc

phous
the Si surface
iOOkeV . 2x•!05/cm'

(9) annealing

-4 -3 -2 -1 0 I 2 3 4
(f) double solid-phase GATE VOLTAGE. Ve VIV
expitaxial film

Fig. 4 Drain current as a function

of gate voltage
Fig.3 Double solid
phase epitaxy process 600
W

o E
0 550~
0
w
0
M
(n, * ~500w
Fig 5 Effective mobility w I.
and threshold voltage as
* IL~U.
a function of X-ray half
width 8 9 10 11 12 13 14
X-RAY HALF WIDTH (min.)
28

Epitaxial film quality is very important factor to determine the device

characteristics. Film quality is evaluated non destructively before process-
ing by UV reflection [8) or X-ray rocking curve half width. Figure 5 shows
the correlation between half width and the mobility.

DEVICE FABRICATION

The typical process sequence of SOS device fabrication is shown in Fig. 6.

In order to reduce back channel leakage, boron and phosphorous are implanted
in n-channel and p-channel, respectively. Threshold voltages are controlled
by shallow implantation of boron for both n and p channel transistors. An
advantage of SOS is that the lateral diffusion length of p channel SOS is
less than that of bulk MOS transistors due to small lateral to vertical
diffusion ratio. Using the 4" or 5" P wafers, the process is quite compatible
with the bulk process except the slow pulling speed to avoid wafer breakage.

SOS-CIRCUIT AND VLSI CONSIDERATION

Figure 7 shows typical propagation delay time vs. power dissipation for
bipolar technologies, MOS technologies, GaAs devices and Josephson devices.
For CMOS devices power dissipation per gate could be very low if the duty
cycle is low. As is clearly shown CMOS/SOS is fast and provides very low
power devices suitable for VLSI system application. Device speed comparison
of bulk and SOS devices are done for several devices. 16 bit n-channel ED
circuit microprocessors were fabricated by both bulk and SOS device using
the same mask. Cycle time ratio is about 2.6 as shown in Fig.8 [9]. This is
explained partly due to low SOS capacitance and also due to nonideal load
line characteristic of bulk device resulting from substrate bias effect.
Another example of speed comparison using the same mask is shown in Fig.9,
which is the speed comparison of the SOS and bulk CMOS one chip
microcomputer

PROCESSING STEPS
SOS Wafer .O6-m.OO")
0, undoped.''",."
(P-to o
Si- Island
Definition

IP-Chonnel DeepIm-plant1( Phosphoflh5) I t

Gate
Oxide
Growth] do,49OA A NMOS
|P-Channel Shallow o4N
(Boron) 3M 6
N-Channel DeepImplant I IBoron)
IN-Chorine' Shallow rMplant IanI
(Bo. CaO ?-_MO

(n- Pal licon Gate CMOSProcess z

0 CM0s/SOS l
no-Potysiio 4 loops
4 OSEPNSOPJ
1
O E

0.

POWERDISSIPATION
PER GATE
N- Channel P - Channel

Fig. 6 SOS process flow Fig. 7 Gate delay power

dissipation diagram
 29

700
-5V

600 -
n 1.2

5001-
w

E 4001F E)

0)
300 F SOS

200
7
100
200 30 400 3500 600 Supply Voltage (V)
Jc (mA)

Fig. 9 8bit CMOS microcomputer

Fig. 8 16bit microprocessor cycle times as a function of
cycle times as a function supply voltage
of supply current

Fig. 10 16bit CMOS/ED microprocessor T88000

30

using the 3 pm design rule. This mask is optimized for the bulk device and
still shows the ratio of 1.6. As an example of CMOS/ED MOS LSI, T88000, a 16
bit SOS micro-processer is shown in Fig.10 [102. The cycle time is
decomposed as is shown in Fig.11.

Internal delay in T88000

"Add" operation

Decoding 35 ns 16 %
Register access 20 ns 10%
ALU operation 60ns 28%
Writing in register 20 ns 10%
Wire propagation 75 ns 36%

Cycle time 210ns 100%

Fig.11 Internal delay time analysis of T88000

It is shown that delay time due to bus charge and discharge is a large
portion of the delay. If the bulk device were used this delay would be more

a!1 II SI 11111 IIh'I I i-il 11111 iii N

a 11 I1
Fig.12 8K CMOS/SOS gate array
 31

than twice as large as SOS. The gate array, which recently catch attention
to custom LSI user, is also made by using SOS technology. The photo of 8K
SOS/CMOS gate array is shown in Fig.12 [11]. The gate delay of the circuits
is shown in Table 2 with the comparison of the bulk device. This
subnanosecond capability and CMOS low power(about 0.3W) enables to assemble

TYPICAL PROPAGATION DELAY TIME Table 2. Typical

delay time of SOS
and bulk
SOS SOS BULK gate array
FAN OUT 3 FAN OUT 3
FAN OUT I + +
AL 2 mm AL 2 mm
INVERTER 0.25 0.67 1.74
2-INPUT NAND 0.43 0.87 2.20
2-INPUT NOR 0.48 0.99 2.52
(NANOSECOND)

the high speed system in few chips. If the ECL circuits were used, gate
delay might be one half of the CMOS/SOS, but we need as much as 8
interconnections for 8k gate logic. As a result system speed might be
comparable to CMOS/SOS logic. Other examples of good SOS applications are
16bit x 16bit multipliers. A multiplier with accumulator(T6354) and a
multiplier without accumulator(T7429) (Fig.13) are made by SOS optimized
design[12].

Fig. 13 16xl6bit SOS multiplier T7429

These two devices use 2pm geometry and multiplication times are 45ns and
32

27ns respectively. These values are 2-3 times faster than ECL devices. This
facts clearly shows the advantage of SOS/CMOS devices over bipolar devices,
provided that the optimized design technique is used for SOS.

FUTURE SOS/VLSI

There were questions about the feasibility of SOS in the Ipm design rule
range compared to bulk CMOS. lum devices are studied by using the solid
phase epitaxy film[13,7). The propagation delay time of the lightly doped
drain structure ring oscillator as a function of the effective channel
length is shown in Fig.14. A 78ps stage delay time and a 0.24mW stage power

1000
CMOS/SOS N- DRAIN isi =0.3gm
tox=2104
WNWP Z=lOpm
800 Lp =LN OQ3rm
U,
"0 VDDO=5V
0'
As-Grown

600
-
0.

>-
- SPE

0 400
0
a-
W
20 )0

-
2,
" ° .ý _ "
51 Stage Ring OSC.
((FO.I)

0 05 , ,.. 1.0
.. I. - 5 1.5
20
2,0

EFFECTIVE CHANNEL LENGTH (N-ch). Lff) AMm)

Fig. 14 Propagation delay as a function of effective channel length

COMPARISON OF 16-BIT LPU's

LJ
Gate Length
[pm version xO.9 #I xO.9 #2 unit
3.5 3.5 3.15 ILm
Tox 700 500 500 -4
Poly-Si Pitch 6.5 5.85 5.85 f.m
Al Pitch 9.0 8.1 8.1 .m
f MAX 13.3 15.4 17.4 MHz
OUTPUT Delay 130 110 95 ns
Speed Ratio I 1.16 1.31

Fig. 15 Speed comparison of T88000 at three feature sizes

 33

dissipation/stage were obtained.As an example of VLSI circuit's downward

scaling, Fig.15 shows the comparison of three mask size T88000 which was
shown in Fig.10. The basic instruction execution times for 3pm version,
xO.9#1( 0.9 times shrank device except gate length) and xO.9#2(totally 0.9
times shrank device) are 300ns, 260ns and 230ns,respectively. From these
data, it can be estimated that if the feature size is reduced to 2pm, the
basic operation time of 100ns, which corresponds to 10 MIPS operation, can
be achieved.

SOS - WHERE TO GO ?

The cost of SOS wafer is still about 3 times more expensive than bulk
devices, and it is not a wise choice to use SOS for very cost sensitive
devices, such as high volume memory products. But if the speed and the
system performance are major concerns, it is the right place to use SOS. SOS
is 1.5-2.5 times faster than bulk and occupies about 30% less area than
bulk. Latch up free characteristic is also an important characteristic. Some
other advantages are a low temperature coefficient, ease of design due to
little constraints and small lateral diffusion of p-channel devices. Special
purpose application such as a radiation hardened devices and an optical
sensors are suitable for SOS, which are intentionally not discussed in this
paper, because the above mentioned applications have wider markets.

REMAINING ISSUES

For SOS, always the silicon film quality has been a major concern. Thin
film, low defect densities, high mobility are required for silicon film on
the sapphire. These requirements are partly solved by solid phase epitaxy.
In order to go to submicron technology, requirements are similar to bulk
devices. A characteristic specific to SOS is a floating substrate effect,
which can be avoided by not using a transfer gate type circuit for critical
path or connecting the substrate to a fixed node. CAD tools specific to SOS
are needed to use the full advantage of SOS. Process and device simulators
for SOS, capacitance evaluation and optimization program and special cell
libraries for SOS are necessary.

CONCLUSION

SOS still has the performance advantage over bulk devices and in system
level, SOS can compete with ECL. SOS is suitable for CMOS applications. SOS
is the only mature SOI technology for the time being.

REFERENCES

1. H.M.Manasevit and W.I.Simpson: J.Appl.Phys. 35, 1349-1351 (1964).

2. T.Sato, Y.Takeishi and H.Hara: Phys.Rev.B 947-956 (1968).
3. H.Schl6tterer: Solid-State Electron. 11, 947-956 (1968).
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and T.Cass: Appl.Phys.Lett. 34, 76-79 (1979).
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34

H.Tango: Proc. 10th Conf. Solid State Devices, Tokyo, 1978, Japanese J.
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