Delay Locked Loops

and
Phase Locked Loops

DLLs and PLLs 1

 Motivation: System
U1 U2
G1 FF2
FF1

B2 B4

B1 B3

CLK

DLLs and PLLs 2

 Analysis
Setup Time Calculation
The setup time at FF2 is calculated from the common point CLK.
Use the maximum delay to set up FF2:D (G1 output)
Use the minimum delay to drive FF2:CLK (B4 output)

To drive the data we add (max)

B1
B2
FF1 (CLK -> Q)
G1
FF2 (tsu)

If the CLK at FF1 would occur at exactly the same time as CLK
on the board, then the delays for B1 and B2 would effectively
be zero.

Note that this technique relies on the max delays being

eliminated being greater then losing the minimum delays in the
clock path.
DLLs and PLLs 3
 Setup Time Flow
U1 U2
Use max for data path G1 FF2
FF1

B2 B4

B1 B3

CLK

Use min for clock path

DLLs and PLLs 4

 Analysis
Hold Time Calculation
The hold time at FF2 is calculated from the common point CLK.
Use the minimum delay to set up FF2:D (G1 output)
Use the maximum delay to drive FF2:CLK (B4 output)

To drive the clock we add (max)

B3
B4
FF2 (th)

If the CLK at FF2 would occur at exactly the same time as CLK
on the board, then the delays for B3 and B4 would effectively
be zero.

Since the delay through U1 and U2/G1 can not be zero, then if
FF2:th = 0, we can design the system as if flip-flops in U2
have a zero hold time at the device’s input pins. That is
typically how we designed with “good” SSI and MSI devices.

DLLs and PLLs 5

 Hold Time Flow
U1 U2
Use min for data path G1 FF2
FF1

B2 B4

B1 B3

CLK

Use max for clock path

DLLs and PLLs 6

 Motivation: Clock Control
• Locking to external signals
• Phase control
• Frequency Multiplication
• Frequency Division

DLLs and PLLs 7

 Basic Phase Locked Loop

Phase Low
Detector Pass
Filter

Voltage
Controlled
Osc.

Analog Circuit
DLLs and PLLs 8
 Example: PLL Multiplication

Phase Low Voltage

Detector Pass Controlled
Filter Osc.

Divide
by
n

DLLs and PLLs 9

 Example: PLL Multiplication

Phase Low Voltage

Detector Pass Controlled
Filter Osc.

Divide
by
n
Single Event Upset
Heavy Ion or Proton
DLLs and PLLs 10
 DLL Another Technique
Goal: System Clock Matches Clock at F-F
U1
FF1

CLK

Ideal
0 ns

DLLs and PLLs 11

 Buffer Tree Delays Not Negligible

CLK

FF1:CLK

DLLs and PLLs 12

 Buffer Tree Delays Not Negligible
So Add A Delay

CLK

FF1:CLK

Delayed CLK

DLLs and PLLs 13

 Buffer Tree Delays Not Negligible
Add A Bit More Delay

CLK

FF1:CLK

Delayed CLK

More Delay

DLLs and PLLs 14

 Buffer Tree Delays Not Negligible
Add Just A Bit More Delay

CLK

FF1:CLK

Delayed CLK

More Delay

A Bit More

DLLs and PLLs 15

 What Did We Do?

CLK

FF1:CLK

Delayed CLK

More Delay

A Bit More

DLLs and PLLs 16

 DLL Another Technique
Insert “Proper” Delay
U1
FF1

CLK

Goal: Insert Delay to Make The Difference Zero If We Delay

Things “Enough” To Line Up Corresponding Edges of
Different Cycles. 17
DLLs and PLLs
 DLL Principle Of Operation

Delay Line

DLLs and PLLs 18

 DLL Principle Of Operation

Delay Line

Single Event Upset

Heavy Ion or Proton
DLLs and PLLs 19
 Manufacturers’ Selections
• Actel
– AX: PLL
– ProAsic, ProAsic+ ???????
• Xilinx Virtex: DLL
• Chip Express
– QYH500: DLL
– CX2000: PLL
– CX3000: PLL

DLLs and PLLs 20

 Virtex Architecture Overview

IOB = I/O Block

DLL = Delay-locked loop
BRAM = Block RAM
(4,096 bits ea.)
CLB = Configurable Logic
Block

DLLs and PLLs 21

 Virtex DLL
• Uses discrete digital delay line
• Latency: 1 to 4 clock periods
• 4 Quadrature phases
• Can double frequency
– quadruple if two DLL’s used
• Divide by 1.5, 2, 2.5, 3,4,5,8, or 16
• Deskew board clock
• Multiple FPGAs, other devices

DLLs and PLLs 22

 Board Level Clock De-Skewing

Note: Can include

multiple Virtex devices.

DLLs and PLLs 23

 Chip Express QYH500 DLL

DLLs and PLLs 24

 Chip Express QYH500 DLL

Single Event Upset

Heavy Ion or Proton
DLLs and PLLs 25
 AX PLL Architecture

DLLs and PLLs 26

 AX PLL

• Fout = Fin * i / j
– 1 ≤ i,j ≤ 64
• Programmable delays
– 250 ps steps, Range ± 3.75 ns
• Can cascade up to 8 PLLs

DLLs and PLLs 27

 AX PLL: External Components
+1.5V

Board FPGA
DLLs and PLLs 28
 Key Parameters
• Minimum and Maximum Frequencies
• Tolerance on input signals
– Frequency
– Jitter
• Lock Time
• Output Phase Offset
• Output Jitter

DLLs and PLLs 29

 Timing Analysis

CLK

With a crystal clock oscillator, the time from rising edge to

rising edge (or falling edge to falling edge) is quite stable,
with crystal clock oscillators having relatively low jitter and
good short term stability.

DLLs and PLLs 30

 Timing Analysis
Max

Min

CLK

• With DLL and PLL, one must check the jitter

specifications carefully, to assure that worst-case timing
must be met.
• Analysis must include the time before the loop locks.
• Analysis must include the effects of SEU’s on the loop’s
control circuits.
DLLs and PLLs 31