IMPACT-2009
A High-Speed, Hierarchical 16×16 Array of Array
Multiplier Design
Abhijit Asati 1 and Chandrashekhar 2
1
EEE Group, BITS, Pilani, India, abhijitmicro@gmail.com
2
CEERI, Pilani, India, chandra@ceeri.ernet.in
Abstract—Array multipliers are preferred for smaller operand
sizes due to their simpler VLSI implementation, in-spite of their
linear time complexity. The tree multipliers have time
complexity of O (log n) but are less suitable for VLSI
implementation since, being less regular, they require larger
total routing length, which may degrade their performance.
Some hybrid architectures called ‘array of array’ multipliers
have intermediate performance. These multipliers have a time
complexity better than array multipliers, and therefore becomes
an obvious choice for higher performance multiplier designs of
moderate operand sizes. In this paper a 16×16 unsigned ‘array
of array’ multiplier circuit is designed with hierarchical
structure and implemented using conventional CMOS logic in
0.6μm, N-well CMOS process (SCN_SUBM, lambda=0.3) of
MOSIS. The proposed multiplier implementation shows large
reduction in propagation delay and the average power
consumption (at 20MHz) as compared to 16-bit Booth encoded
Wallace tree multiplier by F Jalil [3]. The total transistor count,
maximum instantaneous power, leakage power, core area, total
routing length and number of vias are also presented.
I. INTRODUCTION
The multiplier is a fundamental building block in Standard
Digital Signal Processors and ASIC Digital Signal Processors
used for Digital Signal Processing. Multiplication process is
used in many Neural computing and DSP applications like
instrumentation and measurement, communications, audio and
video processing, Graphics, image enhancement, 3-D
rendering, Navigation, radar, GPS, and control applications
like robotics, machine vision, guidance. It is mainly used to
implement algorithms like frequency domain filtering (FIR
and IIR), frequency-time transformations (FFT), Correlation
etc. Most DSP tasks require real-time processing; it must
perform these tasks speedily while minimizing Cost and
Power. The multiplication algorithms differ in the means of
‘partial product generation’ and ‘partial product addition [1].
The array multiplier has linear time complexity i.e O (n)
therefore delay degrades for multipliers having larger operand
sizes. Also it has poor space complexity O (n2), as it requires
approximately n2 cells to produce multiplication. Therefore as
the operand size grows, the circuit takes larger area and power
[2], [5], [6]. A radix-m booth encoding, where m=2n reduces
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the partial product rows by factor of n. Booth radix-4
(m=4=22) encoding can reduce the number of partial product
rows by a factor of two [3]. Since the numbers of partial
product rows is reduced to half, the hardware required to
generate partial products is reduced to n2/2 cells [2]. In
Wallace tree multipliers, since ripple effect is reduced they
produce products in far less time. The time complexity is
reduced to O (log n) but larger routing area is required as
compared to regular array multipliers making them less
suitable for VLSI implementation [2]. The advantage of
reduction in hardware using Booth encoding scheme can be
combined with accelerated Wallace tree accumulation of
partial product to obtain the reduced time complexity of O
(log n), which are very much suitable for large operand size
multipliers [2], [3]. In sub-micron/deep sub-micron era for the
multipliers of moderate operand sizes, where tree based
architectures may degrade their performance due to larger
routing lengths some hybrid architectures shows better
performance, since gate level analysis of these architectures
shows moderate area and delay performance. These multiplier
architectures have moderate area requirements and time
complexity of O ( N ) [4]. In this paper we present a
hierarchical implementation of 16×16, multiplier design using
array of array technique. The VLSI implementation of
multiplier circuit is done using 0.6μm, N-well CMOS process
(SCN_SUBM, lambda=0.3) of MOSIS, using conventional
CMOS logic. Simulation results are compared with Booth
encoded Wallace tree multiplier of [3]. Section II explains the
design of a 2×2 multiplier, Section III describes hierarchical
design of a 4×4 multiplier; Section IV describes hierarchical
design of 8×8 multiplier and 16×16 multiplier. Physical
implementation and results are described in section V. Section
VI concludes the paper.
II. DESIGN OF A 2×2 MULTIPLIER
In this architecture the 2×2 unsigned multiplier is used as a
basic building block in a hierarchical design of a larger bit size
multiplier. The truth table for a 2×2 combinational multiplier
is shown in table I. The truth table can be solved using K-
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IMPACT-2009

map, which generates the equation (1). A 2×2, combinational IV. DESIGN OF A 8×8 MULTIPLIER AND 16×16
circuit can be realized using these equations. MULTIPLIER

P 0 = A0 • B0 In the design of 8×8 multiplier the first step will be finding

the different combinations of input bit pairs that are derived in
P1 = A0 B1( B0 + A1) + A1B0( B1 + A0) terms of 4×4 multiplier. Each input bit-pair is handled by a
P 2 = A1B1( A0 + B0) separate 4×4 combinational multiplier which has been already
designed using 2×2 multiplier as explained in section III.
P3 = A1A0 B1B0 (1) These separate 4×4 combinational multipliers produce 4
partial product rows. These partial products rows are then
TABLE I. TRUTH TABLE OF 2×2 MULTIPLIER added optimally to generate final product bits of 8×8
A1 A0 B1 B0 P3 P2 P1 P0 multiplier as shown in Fig. 2 Similarly, in the design of 16×16
0 0 0 0 0 0 0 0 multiplier the first step is to find the different combinations of
0 0 0 1 0 0 0 0 input bit pairs that are derived in terms of 8×8 multiplier. The
0 0 1 0 0 0 0 0 each input bit-pair is handled by a separate 8×8 combinational
0 0 1 1 0 0 0 0 multiplier to produce 4 partial product rows (the 8×8
0 1 0 0 0 0 0 0
0 1 0 1 0 0 0 1
combinational multiplier design has already been discussed).
0 1 1 0 0 0 1 0 These partial products rows are then added optimally to
0 1 1 1 0 0 1 1 generate final product bits of 16×16 multiplier as shown in
1 0 0 0 0 0 0 0 Fig. 3.
1 0 0 1 0 0 1 0
1 0 1 0 0 1 0 0
1 0 1 1 0 1 1 0
1 1 0 0 0 0 0 0
1 1 0 1 0 0 1 1
1 1 1 0 0 1 1 0
1 1 1 1 1 0 0 1

III. DESIGN OF A 4×4 MULTIPLIER

The first step in the design of 4 bit multiplier will be
finding the different combinations of input bit pairs that are
derived in terms of 2×2 multiplier. Each input bit-pair is
handled by a separate 2×2 combinational multiplier to produce
4 partial product rows. These partial products rows are then
added optimally to generate final product bits. The design
procedure for 4×4 combinational multiplier is shown in table
II, while Fig. 1 shows the schematic of a 4×4 combinational
multiplier designed using 2×2 combinational multiplier. These
partial products rows are then added optimally using 5-bit full
adder cells.

TABLE II. DESIGN OF A 4-BIT MULTIPLIER USING 2×2 COMBINATIONAL

MULTIPLIER

Pair A3 A2 A1 A0
Group II Group I
B3 B2 B1 B0
Figure 1. A 4×4 combinational multiplier
Group IV Group III
I × III PP3 PP2 PP1 PP0
II ×III PP7 PP6 PP5 PP4
I × IV PP11 PP10 PP9 PP8 At each level of hierarchy in design four partial product
II × PP15 PP14 PP13 PP12
rows are to be handled. Therefore accumulation of partial
IV
Sum P7 P6 P5 P4 P3 P2 P1 P0
product rows at each level of hierarchy is much simplified as
compared to other multiplier architectures.

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IMPACT-2009

Figure 1.

Figure 2. A 8×8 combinational multiplier

Figure 3. A 16×16 combinational multiplier

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IMPACT-2009

V. PHYSICAL IMPLEMENTATION AND RESULTS TABLE III. COMPARISON TABLE

Layout for a 16×16 unsigned multiplier circuit shown in Algorithm VDD Propagation Average Transistor
(technology) (V) delay (τ) ns power count
Fig. 3 is implemented in 0.6μm, N-well CMOS process (mW)
(SCN_SUBM, lambda=0.3) of MOSIS, using conventional Proposed 3.3 10.94 31.58 16032
CMOS logic. A schematic library consisting of 4 functional (0.6μm)
cells is defined for static CMOS design styles comprising of 1-
bit Full Adder, 2-input NAND, 2-input NOR, and inverter. BEWM 5 60 100 7858
The selected 1-bit full adder and other logic cells show better (1.25 μm)
power delay products as compared to other logic design styles
[7]. Corresponding to the schematic library, physical libraries TABLE IV. OTHER IMPLEMENTATION DETAILS
were designed using conventional CMOS logic design styles Algorithm Maximum Leakage Core Total Number
using the design principles of [8], [9], [10], [11]. Three (technology) Power Power area routing of Via
different versions of each physical library were developed by (mW) (nW) (mm2) length
respectively sizing the W/L ratios of the NMOS transistor to (mm)
Proposed 543.34 64.02 35.07 2101.75 5704
values of 3,5 and 7 (W/L values smaller than 3 were also (0.6μm)
experimented with but not considered further as they resulted
in parasitic dominated slower speeds due to weak drives of
transistors and were not considered good candidates for high REFERENCES
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VI. CONCLUSION Limited, 2004.
This paper describes a array of array unsigned multiplier
design. The accumulation of partial product rows at each level
of hierarchy is much simplified as compared to other
multiplier architectures. Multiplier circuit is implemented in
0.6μm, N-well CMOS process using conventional fully static
CMOS logic design style using appropriate transistor sizes.
The simulation results are compared with Booth encoded
Wallace tree multiplier architecture and show reduction in
propagation delay by a factor of six and average switching
power by approximately a factor three. The maximum
instantaneous power, leakage power, core area, total routing
length and number of vias are also presented.

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