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SEPTEMBER-2009 PAPER–(SUPPLEMENTARY)
1.a) Explain how cost and delay of a logic gate varies with different IC technologies.
b) What are the deficiencies of MOS technology? How they can it be over come?
2.a) Explain the principle of CMOS inverter with V-I wave forms.
b) What is latch-up condition in CMOS circuits? How it can be eliminated.
3.a) What are λ -based design rules? Give them for each layer.
b) Draw the stick diagram of 2-impact Ex-or gate.
4. Explain about-nmos logic, domino logic and DCVS logic and compare them.
5.a) What are the various simulators used for combinational logic design? Explain their need.
b) What are different testing methods for testing combinational gate? Explain with an example.
6.a) Distinguish between clock skew and signal skew with an example.
b) Explain about 2-phase clouding disciplines
7.a) Explain how clock routing design optimizes the clock skew in floor planning.
b) What is the need for package of a chip? Explain about input and output pad circuits.
MARCH-2009 PAPER–(REGULAR)
1.a) What are the various marks used in CMOS p-well process? What is the significance of each.
b) Compare bipolar and CMOS technologies.
2.a) What is threshold voltage? What are various factors that influences threshold voltage.
b) Explain the principle of BICMOS inverter.
3.a) What are various symbols used in sticks notation? Draw the stick diagram of CMOS inverter.
b) What are scalable design rules? Explain.
4. What are various switch logic circuits? Compare their merits and demerits.
5. Explain how fan-out and path delay influences delay in combinational networks.
6. Explain about 1 -φ clocking rules for flip-flops and 2 -φ clocking disciplies for latches.
SEPTEMBER-2008 PAPER–(SUPPLEMENTARY)
1.a) What are the various processes of CMOS fabrication? Illustrate the main steps in a typical n-well process.
b) Tabulate the comparism between CMOS and Bipolar Technologies.
2.a) Determine the Pull-up to Pull-down ratio for an nMOS inverter driven through one or more pass
transistors.
b) Draw a simple BiCMOS inverter circuit diagram and explain its operation.
3.a) Explain about scalable Design rules related to NMOS and CMOS Technologies.
b) With suitable diagrams explain some switch logic arrangements.
4.a) With neat sketches describe the various Layout Design methods.
b) Explain the clocking Analysis related to sequential systems.
5.a) With relevant diagrams explain about various Floorplanning methods used in Layout design.
b) Explain the design Methodology for IBM ASICs.
6.a) Give the device structure for CMOS inverter and explain the same.
b) Draw Latch-up circuit model and explain its operation.
FEBRUARY-2007 PAPER
3.a) Explain the delay in combinational logic network and how combinational delay can be reduced.
b) Compute the zero delay signal probabilities for all signals in the network shown
4.a) What is clock skew? Explain how clock skew affects the digital system. What is the maximum allowable
skew for the parameters T =10 ns, tpr = 1 ns, tsr = 1 ns, tsl = 1 ns, tpl = 5 ns, tp = 5 ns. What is the minimum
allowable clock period under these conditions?
b) What is ATPG? DFT? Generate a set of Sequential tests for the “01” – string recognizer which test for all
stuck – at – 0/1 faults, assuming you don’t know the initial state.
8.a) How would you translate a register transfer structure into a legal 2-phase latched sequential machine?
b) Write short notes on any two of the following:
i) Differentiate the devices PAL, PLA and FPGA
ii) Cross-talk
iii) Placement and routing in floor planning.