Proceedings of the 26th Chinese Control Conference

July 26-31, 2007, Zhangjiajie, Hunan, China

Efficient Parallel Control Scheme of Single

Phase Inverters*
Liu Xiaozhu 1, Zhu Rongbo 2
1. School of Automation, Wuhan University of Technology, Wuhan 430070,P.R. China
E-mail: lxz_h@163.com
2. College of Computer Science, South-Central University for Nationalities, Wuhan 430073, P.R. China
E-mail: rongbozhu@gmail.com

Abstract: In order to parallel several single phase inverters to increase power capacity and system reliability, several control
schemes are proposed: a parallel control scheme, a voltage control scheme and a load sharing control scheme. The parallel
control technique is based on preemptive priority, which makes no absolute master or slave inverter into reality. In order to
ensure N+1 redundant structure, synchronization signal generating mechanism, a parallel digital bus and a no-conflicted
protocol on the bus also are introduced. In order to control voltage, the voltage control scheme employs a local feedback
controller. To implement load sharing, the load sharing control scheme introduces an improved droop method to droop
voltage and frequency. The analysis of the proposed method and design procedure are provided. Based on the simulation and
experiment results, it shows that the proposed scheme can implement load sharing effectively. The experimental results with
different type loads show that the output current error is less than 1% rating current for each inverter.
Key Words: Parallel control, synchronization, load sharing, inverter

connected DC/DC inverters. Previous studies on

1 INTRODUCTION
Paralleling of lower-power inverter modules offers a
number of advantages over a single, high-power,
centralized power supply. It is convenient to increase
power capacity and can satisfy different load power
requirement. It is very flexible to build up redundant
structure and to improve system’s reliability. A power
supply that is used to power telecommunication
equipments can be composed to parallel-connected
DC/DC inverters. These inverters require categorical
current sharing mechanism to ensure proper operation.
The main advantage of using parallel inverters
configuration with current sharing control is to increase
the power process capability that improves a reliability
of the whole system. At the same time, the system can
only bears 150%~200% overload, its output resistance
is very low, output current is variable quickly, so it is
very difficult to control and design a parallel inverter
system. What’s more, the parallel inverter system has to
satisfy such conditions as frequency and phase
synchronism between all inverters, output voltage and
current balance.
There are several control ways to a parallel system,
concentrate control[3], master-slave control[4], distributed
control[5] and no interconnections control[6]. Those
ways have their advantages and disadvantages
respectively. The current sharing scheme can be
achieved by injecting a signal proportional to the
desired converter output current into the voltage loop.
The increased voltage loop error signal forces the duty
cycle and then the output current of the converter to
increase. An excessive work has been done in the field
of modeling, analysis, and control design of parallel-
* This work is supported by Nature Science Foundation of South-
Central University for Nationalities under Grant YZZ07006.
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parallel-connected DC/DC inverters have not fully
addressed the modeling problem of interconnection
resistances [1-2] and the analysis problem of interactions
among converters [1-2]. Most current-loop controllers are
designed separately to ensure stability. However, the
interactions affect the stability properties and the
dynamic performance has not been studied. Models of
parallel connected DC/DC converters, which are
presented in can never be perfect because certain
characteristics were not modeled at all, e.g. variations
of power stage components, changes of operating
points, load alterations, etc. The uncertainties cannot
easily be modeled; however they must be included in
the analysis. Various measures of robustness can be
used; robust stability and robust performance guarantee
that the system performs well in spite of disturbances and
model uncertainties. Previous studies emphasized the
applications of robust control theory to DC/DC converters
but never tried to utilize theory in practical issues.
In this paper, we emphasize on parallel operation of
single phase inverters with the same capacity and
having similar dynamic characteristics. In order to
implement parallel several single phase inverters to
increase power capacity and system reliability, several
control schemes are proposed: a parallel control scheme,
a voltage control scheme and a load sharing control
scheme. The paper is organized as following. In
section 2, a parallel control scheme is proposed, which
includes preemptive priority control method and N+1
redundant structure scheme. Section 3, a simple single
inverter model is given and a local controller is
designed to improve load carrying. In section 4, after
analyzing the simple parallel model, an improved
drooping method also proposed to share load.
Simulation and experiment results validate the
feasibility and validity of proposed method in section 5.
Finally, section 6 concludes the paper.
 i
Di = ¦ Ai + E (1)
2 PROPOSED CONTROL SCHEME j =1

2.1 Proposed Control Scheme N+1 redundant structure [7] system is a very stable and
economical redundant way. N+1 redundancy in an
In the conventional control approach to paralleling inverter system requires two key conditions: The first is
inverters, usually there is a common circuit block which, each inverter has independent detecting circuit, and can
if it fails, renders the entire system inoperable, monitor and modify itself input and output voltages and
especially in master-slave system, if the master is currents. The second is that each inverter can share load
damaged and there is no master and no synchronization current perfectly. There is no master/slave concept, and
signal, such case is deadly to the system. To overcome each inverter can work independently.
this problem, each inverter could not depend on center
control unit or some master inverter. When the master
inverter faults, the system can generate a new master in
some rules in time and implement the
synchronization signal jointing seamless. In actual
system, there is alternating current (AC) supply, so it
is clear that the AC supply parameters (frequency,
phase and amplitude) must be the synchronization
signal and the static switch become the master
accordingly. The priory of AC supply signal is higher
than that of inverter because the system must switch
in the light of AC supply parameters immediately at
the moment AC supply power off. There are also
master and slave in the system, but not absolutely, so
the combination method of priority and preemptive is
a good choice: Fig.1 Synchronization signal generating mechanism
If there is AC supply signal anytime in the system,
static switch is the temporary master, which means AC It is clear that the first condition is very easy to fulfill.
supply signal’s priory is higher. Each inverter in the The preemptive priority satisfies the no master/slave
system tracks and captures AC supply signal and tries concept. To share load current perfectly, the
to synchronize itself output signal with AC supply communication protocol on the parallel bus is very
signal. important to the parallel system to change information.
If there is no AC supply, the temporary master is The no-conflicted protocolütoken bus protocol can be
generated by the way of preemptive, other inverters used on the bus, for the stations connected on the bus
become temporary slaves. When this temporary master make up of a logical ring, and each station has a logical
fails, it is also can generate the temporary master by number in order. It is easy to distinguish each member
preemptive. for each member station knows it’s pre-station and
In this model, for each inverter sends out successive station. Further more, it is not complex to
synchronization signal all the time though the signal is implement the protocol in actual system.
not work at most time, the time of generating the master Fig.2 shows the paralleling N+1 redundant structure
by preemptive is almost negligible, which ensures the system, where several inverters parallel each other by
master switching seamlessly. the parallel bus, when the “AC input” is switched off by
2.3 Synchronization Scheme and Redundant static switch unit, the inverters will converter the DC
Structure input to AC to supply AC output for other systems.
When the static switch unit switches on, it will send
It is clear synchronization signal is sent by the temporary commands to each inverter by the parallel bus, and then
master, so the synchronization signal generating all inverters will stop work, the AC input will output
mechanism is the same mechanism of generating directly.
temporary master.
In Fig.1, Ai is the synchronization signal output point
generated by each inverter. Di is the detected point of
synchronization signal in each inverter. E is the
sending point of static switch unit’s synchronization
signal, if there are AC supply and static switch in the
parallel inverters system. As long as we chose
resistances R1, R2, R3 and R4 appropriately in the circuit,
it can ensure the preemptive priority logic. To some
extend, synchronization signal generating logic can
describe as the following equation: Fig.2 Paralleling redundant system

205
 1
3 VOLTAGE CONTROL SCHEME H v ( s) = (7)
τ 1s + 1
The inverter can be presented as shown in Fig.3. The H i ( s ) = k1 (8)
PWM just as a switch and switch rate is controlled. If H r ( s ) = k2 (9)
PWM unit has a duty ratio λ , ideally the output
voltage is λ E . It is clearly that by varying λ as 4 LOAD SHARING CONTROL SCHEME
λ = λ sin ω t , we can get the desired output voltage
A simple schematic of two parallel inverters can be got
V1 = λ0 E sin ω t .
easily by Fig. 3. For the nature of the line impedance
has a profound effect on the load sharing control, the
line impedance is represented by a pure inductance X ,
V0 is output voltage on the load. The complex power at
the load due to the inverter1 is given by:
S1 = P1 + jQ1 = V0 I1* (10)
Fig.3 Inverter model
where I1* is the conjugate of inverter1’s and is given
From the model we can get: by:
v1 = ( s 2 LC + sRL C + 1)vo + ( sL + RL )io (2) V (cos θ1 + jsin θ1 ) − V0
where iL is inverter filter inductor current, io is load I1* = 1 (11)
jX
current, ic is capacitance current, vo is output where θ1 is the phase angle of V1 .
voltage and v1 is PWM output voltage. Then, we can get:
Usually, the output voltage Vo is used as a feedback V V (cos θ 1 + sinθ 1) − V0 2
S1 = 1 0 (12)
signal to correct the PWM unit’s duty radio. However, jX
this method, used in almost all switched mode DC/DC
The real power P1 and reactive power Q1 is:
power supplies, can not be used in an inverter
developed to operate in parallel since its setting time is V1 V0 sin θ1
P1 = (13)
much too slow. X
V V cos θ 1-V02
Q1 = 1 0 (14)
X
For the error between V1 and V0 is very tiny, then
sin θ1 = θ1 , assume that V1 = k1V0 , we can get:
k1 V 02θ1
P1 = (15)
X
Fig.4 Proposed voltage controller (k cos θ1 − 1)V02
Q1 = 1 (16)
X
In order to increase the loop gain we have taken the LC Similarly for inverter2, if V2 = k2V0 :
filter out of the feedback loop [8]. A block diagram of
the voltage controller is shown in Fig.4, where Vref is k2 V 02θ 2
P2 = (17)
the sine wave reference. Then we can get the equation: X
(1+ H v kv ki A ) v1 = kv ki Avref − H i ki Aic − H r Aio (3) (k cos θ 2 − 1)V02
Q2 = 2 (18)
Using (2), and (3) we can get: X
where θ 2 is the phase angle of V2 .
vo + Gi ( s )io = Gv ( s ) vref (4)
Equations (15), (16), (17) and (18) show that the real
where: power flow predominantly depends on the power angles
§ Hr A · θ1 and θ 2 , and the reactive power flow is mostly
sL + ¨ RL + ¸
© 1 + H v k v ki A ¹ influenced by the amplitude of voltages V1 and V2 .
Gi ( s ) = (5)
§ H i ki A · To avoid overloading one inverter, it is efficient to
s 2 LC + sC ¨ RL + ¸ +1 control real power by modifying phase error ( θ1 , θ 2 )
© 1 + H v k v ki A ¹
and control reactive power by voltage amplitude ( V1 ,
k v ki A
V2 ).
1 + H v k v ki A
Gv ( s ) = (6) Further, we can get:
§ H i ki A ·
s 2 LC + sC ¨ RL + ¸ +1 kV 2
© 1 + H v k v ki A ¹ ΔPi = i o Δθ i (19)
X
Here, we select the signal filters as follows: The varying of output voltage phase is implemented by
varying the output voltage frequency:
206
 d(Δθ i ) 6 show the frequency and circular current between two
Δf i = (20) inverters respectively.
dt
So we can get the equation: From Fig.5 and 6, we can see that the frequencies are
X d(ΔPi ) adjusted quickly and there is little error between two
Δf i = (21) inverters’ frequencies after 0.5 s, the inverters are
kiV02 dt
almost synchronized after 1 s and the average frequency
Vo cos θ i errors of two inverters are 0.00003. From Fig 6, we can
ΔQi = ΔVi (22)
X see that the circular current is decreased distinctly after
Though voltage and frequency drooping is a effective 0.5 s to 0.7 A, which also implies the phase error is a
method, there are also defects [9]. For the frequency key factor to the system. The adjusting process is
character is not only affected by real power P , also almost 0.5 s and the system comes into steady. The
affected by ΔP . At the same time, from the parallel results prove that the load sharing scheme is very
bus each inverter can get others real power and reactive effective.
power, which means that each inverter knows other’s 7DE6LPXODWLRQ3DUDPHWHUV
statement and that information is very useful to
implement load sharing control, therefore the drooping Parameter Value

method can take other’s statement into consideration. Output Power 3 kVA
f n +1 = f n + k1 Δ P − k 2 Pn +1 (23) Voltage, Frequency 220 V, 50 Hz
where: Capacitance 20 ȝF
1 N
ΔP = ε ( Pn +1 − Pn ) + (1 − ε )( ¦ Pin − Pn ), 0˘ ε İ1 (24) Inductance 1 mH
N i =1 RL, τ 1 0.02 Ω , 0.5 ȝs
Similar to equation (23), we can get: kv , A 0.74, 0.95
Vn +1 = Vn + k3ΔQ − k4 (Vn +1 − Vn ) (25)
H i ( s ) , H r (t ) 0.93, 0.015+0.1( cos 2ω t + 1 )
where:
1 N ki , k1 , k2 1.87, 8e -9, 3e -9
ΔQ = ¦ Qi − Qn (26) k3 , k 4 , ε
N i =1 0.08, 0.5, 0.5

In the voltage and frequency droop method the system

control is achieved by slightly reducing the output
voltage and frequency according to the active and
reactive power of each inverter. However, in the system
the different units are usually close, so the impedance
between them is negligible.
In order to have a strong capability of load carrying,
inverter should have low output impedance, but if the
impedance is low, the inverters have a tendency to
oscillate against each other. To make the system more
robust the virtual impedances can be increased.
To damp the oscillation, an effective method is giving
apparent ohmic impedance for these oscillations. But Fig.5 Frequency control and synchronization
considering the rectifier load, to retain the performance
while increasing the robustness, it is necessary to adjust
the impedance within a period. The regulation is simple,
when voltage crosses zero the system should have large
impedance, and when voltage crosses peaks the system
should have small impedance. It is obvious that the
adjusting period is half of the period of output voltage.
This impedance signal can be given as
H r (t ) = λmin + λ (cos 2ω t + 1) . Choosing the parameters
appropriately in actual systems, inverter will be more
robust.
5 SIMULATION AND EXPERIMENTAL Fig.6 Circular current between inverters
RESULTS 5.2 Experimental Results
5.1 Simulation Results The follows figures are got when two single phase 220
The well-known simulation tool MATLAB is used to V/50 Hz 3kVA inverters were operating in different
validate the proposed scheme. All the parameters used conditions.
in the simulation system are shown in Tab. 1, Fig. 5 and When the parallel system carries the non-linear loads,

207
though we choose the low power factor cos φ with 0.6,
in Fig. 7 and 8, the output voltages and currents of two
inverters still have little errors about 0.34 A and 3.1 V,
which ensure the little circular currents error and load
sharing. To some extend, output voltages and currents
are misshapen, but in such lower factor condition, the
results are reasonable. The results imply the parallel
system has power capability to bear non-linear loads.
Fig.7 Output current of each inverter with
non-liner load
Fig.8 Output voltage of each inverter with
non-liner load
From Fig.9, it is clear that two inverters can bear the
rectified loads well and the output current waveforms
are better than that in Fig.9 also demonstrates the
validity of virtual impendence.
Fig.9 Output voltage and current of one inverter
with rectified load
208
6 CONCLUSION
In this paper, an efficient control scheme is proposed
for parallel operating single phase inverters, which
ensures that each inverter is equal and system
redundant structure. A feedback controller increases the
loop gain and ensures stability for smaller load currents
and rectifier loads. An improved droop method is also
proposed for the inverter parallel operation, which
adaptively controls the reference voltage of each
inverter. This improves the output voltage regulation
and the current sharing. For engineering practical
project application and detailed requirements for power
supply, negligible influence by factors such as
nonlinear and instability of system are taken to careful
consideration. Two 3 kVA forward converters are built
and parallel connected for the experimental set up.
Simulation and experimental results verify the excellent
performance of the proposed method. The experimental
results with those loads shows that each inverter’s
output current error is less than 1% rating current.
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