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Multi-Channel Streaming DMA Controller IP

SDI Audio IP
Streaming PCIe SDI AV Reference Design
Altera UDX 2.1 Up Down Cross Converter
Arria II GX AV Development Kit
OmniTek Design Consultancy

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Multi-Channel Streaming DMA Controller IP
BAR Port
interface
(BARs 1 – n)
OmniTek’s Multi-Channel Streaming DMA
Controller is designed for implementation in Top-Level DMA Controller
Altera® FPGAs that include a PCIe Hard IP
block. It supports data transfer over either a
PCIe Gen1 (as supported by Arria® II FPGAs)
Multi-Channel DMA Controller
or a PCIe Gen2 bus (as supported for example Avalon-ST
Rx
Avalon-ST
Rx
Avalon-MM
Master PCIe
DMA
by the Altera Stratix® IV FPGA family).
Completer PCIe
Completer Capability
(BAR 0)
Registers
PCI Express Bus Altera
The controller offers both memory-based PCIe
Interface PCIe
Translation DMA
‘MDMA’ for handling transfers to and from Hard IP Scatter-Gather

addressed memory such as on-board SRAM

Avalon-ST Avalon-ST PCIe Avalon-MM Master
and SDRAM, and FIFO-based ‘FDMA’ for Tx Tx Requestor
DMA
MDMA Channel

streaming applications. The FDMA channels PCIe

Requestor Master
Controller
Avalon -ST
are optimised to only use FPGA-embedded FDMA channel Video
Interface

memory blocks to transfer video and other

streamed data.

DMA Controller Features High Bandwidth Efficiency

PCIe-based DMA Controller Core for Altera Stratix IV GX
and Altera Arria II GX
Supports both PCIe Gen1 and PCIe Gen2
Highly efficient use of PCIe bandwidth,
making it particularly suited to data streaming applications
Configurable for 1, 2 and 4-lane buses (8-lane available on
request)
Supports 32-bit addressing (with future extension to 64-bit)
Configurable number of FIFO DMA and memory DMA
channels
Configurable number of 32, 64 or 128bit FDMA streaming
channels
Supplied in SOPC Builder-ready form with Avalon-
compatible interfaces and wrapper linking FDMA channels
to 20bit Avalon-ST video interfaces
Controller block, PCIe translation block and wrappers
optionally available as source code in either Verilog or VHDL
Controller IP includes drivers and API for Windows® Vista™
and XP™ (available as C source code)
A major feature of the DMA Controller is its high level of PCIe
bus bandwidth efficiency, which it achieves through:
i. Support for multiple outstanding read requests. This
minimises the effects of PCIe latency.
ii. Pre-fetching of the next descriptor in Scatter-Gather
mode to ensure a smooth transition from one descriptor to the
next. This is essential when working with streaming video to
ensure that buffers do not overflow.
iii. Optimisation of the arbiter controlling access to the PCIe
bus for back-to-back packing of TLP packets while processing
multiple channels.
Example Applications
• Data servers
• Video disk recorders
• Video capture cards

Audio Embed and Audio Extraction IP

OmniTek also offer IP both for embedding audio in SD/HD/3G
SDI SDI video and for extracting audio embedded in SD and
HD SDI video.
The audio embedded by the Embed block is formatted either
in accordance with the SMPTE272M standard (for SD video)
or in accordance with the SMPTE299M standard (for HD and
(provisionally) for 3G video).
The input audio may be at any of the sample rates permitted
by the above SMPTE standards and can be provided in either
I2S Audio, AES Audio or Parallel Audio format. It can also be
either synchronous or asynchronous to the video.
The Extract block is designed to extract both audio delivered
as SMPTE272M packed data from standard definition SDI
and audio delivered as SMPTE299M packed data from high
definition SDI. The extracted audio may be output in either I2S
Audio, AES Audio, Parallel Audio or Avalon-ST Audio format.
The Embed block allows audio to be embedded in up to
16 channels (8 channel pairs). The Extract block is designed
to extract audio from a single channel pair but multiple blocks
may be used together to extract the audio from multiple
channel pairs. Operations in both blocks are carried out in
accordance with settings in associated sets of slave registers.

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 SDI SDI
In Out

Reference Design Firmware

Video-Streaming Reference Design Video Video
Test
Out In
Target

The video streaming reference design uses Altera SDI I/O IP

alongside OmniTek audio and DMA IP to create a video- DMA Controller Wrapper
streaming SDI – PCI Express bridge. This bridge design is Avalon-
ST
Avalon-
ST
Avalon-
ST
Video Video Video
supported on Altera’s Stratix IV GX A/V Development Kit and Interface Interface Interface

OmniTek’s Arria II GX A/V Development Kit. Also supplied are

DMA Controller Core

FDMA channels

MDMA channel
FDMA channel

FDMA channel
the Quartus project files used to implement the reference

Further
designs on the host boards included in the development kits
and an example Windows application written in C++. DMA DMA
DMA
FPGA Control Capability Scatter-
Master Controller
The application demonstrates the ability of the DMA controller to Registers Gather

read both of the input video streams being fed into the
transceiver card at the same time as writing to both output video PCIe Translation Block

streams, even where 3G video is processed.

Altera PCIe Hard IP
Audio embed/extract is also provided on the first of these video
streams. The Audio Extract on the input routes a single channel
pair to the AES outputs on the transceiver card. The Audio
Embed on the output allows up to 4 channels of AES audio to be Host PC
added. In the example application, this audio may either be the
audio extracted from the first input video stream, or audio that is Driver (IP)

input through the AES ports on the transceiver card or the output
from a built-in sine wave generator. API (IP)

The application can work with video in any of the following

Ref. Design Application
formats*:
PAL, NTSC
1080i (at 50/59.94/60 Hz)
720p (at 50/59.94/60 Hz)
3G A 1080p (at 50/59.94/60 Hz)
The application also demonstrates the use of the Windows
driver and API supplied with the DMA Controller.
The various elements of the Reference Design are also available
in source form (alongside the other OmniTek IP).

* Note: The number of streams that can be read or written

may be limited by the bandwidth of the PCIe bus. In
particular, 4 lanes are needed to handle two 3Gbps type A
streams in an Arria II implementation of the reference design.

Resource Use
Memory Blocks (M9Ks)
Combinational ALUTs

Combinational ALUTs

The following table summarises The following table summarises

Dedicated Regtisters
Dedicated Registers

the FPGA resources used by the FPGA resources used by

Memory Blocks

the various components of the the Audio Embed and Audio

DMA Controller design. Extract designs.

Base DMA Controller 1000 960 3 Embed Block Base 305 434 0
plus for each audio group (4 channels) 405 215 3 M9K
Optional:
MDMA Channel (64 bits) 660 700 8
Channel Status Memory (max) 0 0 16 MLUT
Clock Generator 60 50 0
FDMA Input Channel (32 bits) 430 320 6 Sine Wave Generator 105 110 2 M9K

FDMA Output Channel (32 bits) 290 270 20 Extract Block (supports 1 channel pair) 235 255 1 M9K
Optional:
PCIe Translation Block 1370 1750 11 Channel Status Memory 32 25 512 bits
Error Checker 176 125 0
DMA IP (Base, 1 MDMA, 4FDMA In, 4 FDMA Out) 4640 4020 115 FIFO Status Logic 24 48 0
Audio IP (Embed (4 ch), Extract (2 ch) + options) 1595 1487 6 48kHz Clock Recovery 253 225 104 bits
Avalon-ST Audio Interface 140 305 2 M9K

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UDX 2.1 Image Processing Reference Design – from Altera

The UDX 2.1 Reference Design illustrates the use of the suite. A NIOS II processor embedded in the FPGA (also
various image format conversion cores included in Altera’s included in the OmniTek Arria II GX Development Kit) provides
VIP suite (see below) to deliver high-quality two-channel up, detailed control over the transformations that take place.
down, and cross conversion of standard definition (SD), high Image format conversion is a commonly used function in various
definition (HD), and 3G-SDI video streams. The design broadcast infrastructure systems, such as servers, switchers,
handles both interlaced or progressive format video streams. head-end encoders, and specialty studio displays. The need for
The design ingests video over two serial digital interface (SDI) image format conversion is driven by the multitude of input
channels, then passes it through a series of video and image image formats that must be converted to HD or a different
processing functions provided by the cores of the Altera VIP resolution before they can be stored, encoded, or displayed.
Quartus (HDL)
Frame Rate
SOPC Builder Input Channel Conversion

to444 to422 Constant 1

NTSC MA AFD Frame
Y Y Chroma Scaler Chroma Alpha
Clipper Deinterlacer Clipper Buffer
Resampler 30 Resampler 20 Source
Cb Cr
Y
SDI Y Y
AFD
SDI Clocked Cr
Extractor
20* Video Input 20 Cb Cr
Cb
NIOS II
DDR2 HP2
Multi-port Front-end Memory
Controller

SDI
AFD
SDI Clocked
Extractor
20* Video Input 20
Input Channel

* 20 (for SD use to444 to422 Constant 2

10 least signifcant NTSC MA AFD Frame
Chroma Scaler Chroma Alpha
bits) Clipper Deinterlacer Clipper Buffer
Resampler 30 Resampler 20 Source

Frame Rate
Conversion

Color OSD Colour to422 3

Frame Space Chroma
Plane
Reader Converter Resampler
Sequencer
Output Channel
Test
Pattern OSD Channel
Generator

1 Control SDI Clocked

Interlacer AFD Inserter SDI
Synchronizer Video Output
OSD 20*
OSD
Mixer
Mixer
Switch

Output Channel

Test
Pattern Control SDI Clocked
Generator AFD Interlacer AFD Inserter SDI
AFD Synchronizer Video Output
Mixer 20*
Mixe
Bypas
r
s
2 Switch * 20 (for SD use
10 least signifcant
bits)

Run-time configurable via register map (Avalon-MM Slave interface).

VIP
= Configuration changes (eg. viewing mode changes, scaler coefficient
Core
reload) performed by software executing on Nios II processor

Supporting IP Blocks – from Altera

SDI Interface VIP Suite

The SDI interface of the reference designs is provided by Altera’s Video and Image Processing (VIP) Suite is a collection
Altera’s Triple-Speed SDI MegaCore®. of MegaCores that provide the various image format conversion
This SDI core comprises receive and transmit blocks that facilities required by image processing and display applications,
together provide a full-duplex serial digital interface (SDI), such as video surveillance, broadcast, video conferencing, and
working at either 270Mbps for SD, 1.485Gbps for HD video or medical and military imaging. These cores are also included
2.97Gbps for 3G video. among the Altera IP offered by OmniTek’s Audio/Video
Development Kit for the Altera Arria II GX.
An important feature of the SDI MegaCore is its ability to auto-
The functions provided by the VIP Suite range from simple
switch between these standards, allowing triple-rate SDI on the
building block functions such as colour space conversion to
same FPGA transceiver pin. The core also offers auto-detection
sophisticated video scaling functions that can implement
of the input video standard.
programmable polyphase scaling. The use of these MegaCores
The Altera Triple-Speed SDI MegaCore is included among the is illustrated by the UDX 2.1 Reference Design.
Altera IP offered by OmniTek’s Audio/Video Development Kit for
The streaming interfaces on the VIP MegaCores all follow
the Altera Arria II GX.
Altera’s Avalon® ST interface standard which makes them easy
to use to provide a sequence of format conversion functions.

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OmniTek Audio/Video Development Kit for the Altera Arria II FPGA

The Arria II AV Development Kit provides a

virtually risk free way to evaluate the Altera
Arria II GX, along with the comprehensive
IP and reference designs from OmniTek
and Altera described elsewhere in this
brochure. The bundled OpenCore Plus
licenses enable users to test out
applications based on this IP without
having to make any further purchase.

Comprises:

Altera Arria II GX FPGA Development Kit –

which includes the main board shown here
Terasic Technologies SDI (Serial Digital Interface)
Transceiver High-Speed Mezzanine Card (HSMC) –
also shown to the right
Altera Arria II CD ROM
Altera Complete Design Suite DVD – which includes:
Quartus II Software Development Kit Edition
(1-year licence)
Nios II Embedded Design Suite
OpenCore Plus access to MegaCore® IP Library
OpenCore Plus access to Altera Triple-Speed
(3G, HD and SD) SDI IP The Altera Triple-Speed SDI IP and the OmniTek DMA
Controller and Audio IP are initially provided encrypted and
OpenCore Plus access to OmniTek Multi-Channel tethered to the Altera Arria II development environment.
Streaming DMA Controller IP (complete with Windows drivers)
OpenCore Plus access to OmniTek Audio Embed/ On application to OmniTek, however, the Development Kit
Extraction IP may be upgraded to include fully-featured, untethered versions
of the DMA Controller IP, Audio IP, the Triple-Speed SDI IP and
Compiled SDI to PCIe Bridge Video Streaming Reference supporting IP – still only targetable at Arria II devices but
Design offering 2x video input, 2x video output available at a considerable discount on the full cost of this IP.
Compiled UDX2.1 Image Processing Reference Design
A further upgrade to full source code versions of the OmniTek IP
Design examples, schematics and complete documentation and Reference Design is also available from OmniTek.

Easy Integration of All Components

All the components described in this brochure are provided

‘SOPC Builder-ready’ and have Altera Avalon-compatible
interfaces to allow easy integration with other Altera SOPC
Builder-ready components.
The DMA Controller, the Audio Embed and the Audio
Extract blocks are also available as source code in either
Verilog or VHDL. Users therefore have the choice of either
instantiating the components directly in their own top-level
design or both configuring them and linking them with other
components within SOPC Builder.
The top-level module of each Reference Design may also
be used within SOPC Builder as the basis for similar
designs.

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 Sales Information

Access to the products described in this brochure is available at different levels in line with the stages of product design
and production. The options are detailed in the following table.

Option Notes
Inspection of documentation Registered users of OmniTek web-site (www.omnitek.tv) may
and IP Block Pin-outs download the Altera Fileset ZIP file. The documentation and
pin-outs are un-encrypted and can be inspected for free. Other
parts of the fileset require the appropriate licence (see below).

Demonstration Arrange a free demonstration with EBV in Europe;

OmniTek in the rest of the world.

Audio/Video Development Kit for Arria II Cost $3,245. Includes ‘OpenCore Plus’ access both to OmniTek IP
and to the Altera IP suite.

OpenCore Plus Licence: Allows the creation of a working design.

Note: Included with Audio/Video Development Kit for Arria II
OmniTek DMA controller Apply to OmniTek
Altera IP Apply to Altera

Encrypted IP Licence: Allows IP to be used in a production system.

OmniTek DMA controller Apply to OmniTek
Altera VIP suite Apply to Altera
Altera SDI interface Apply to Altera
Bundle of above with Audio IP and Nios II embedded processor
Apply to OmniTek

Source Code Licence: Allows customisation of IP.

OmniTek DMA controller Apply to OmniTek
OmniTek Audio Embed/Extract Apply to OmniTek

Consultancy OmniTek is able to offer consultancy on designs based around

its IP blocks and Audio/Video Development Kit.

To order the Audio/Video Development Kit in Europe, please contact:

EBV via their website : www.ebv.com For post-sales support,
(Search for Audio/Video Development Kit) please contact:
To order the Audio/Video Development Kit in the rest of the world and support@omnitek.tv
for licences and consultancy, please contact: consulting@omnitek.tv

THE COMPANY

OmniTek is a consultancy company specializing in the design of
products and systems for TV broadcast and post-production
applications. Formed in 1998, the company has completed many
successful product designs for leading equipment manufacturers in
the USA, Europe and Asia. The company also designs and
manufactures a range of advanced test and measurement
equipment, for engineers working in video R&D, broadcast, and
post-production. The various OmniTek products include signal
generators, waveform monitors, and picture quality analyzers.
See www.omnitek.tv for more information.
OmniTek is an Altera Certified Design Center.

V1.0 © 2010 Image Processing Techniques Ltd.

Intec 2 Unit 3, Wade Road

Basingstoke RG24 8NE
United Kingdom
Tel +44 (0) 125 634 5900
Fax +44 (0) 125 634 5901

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