2017 IEEE Transportation Electrification Conference and Expo, Asia-Pacific (ITEC Asia-Pacific)

Research on Active Disturbance Rejection Controller

Integrated in TSVG
Dongxin JIN Liguo WANG Haochen ZHU
Dept. of Electrical Engineering Dept. of Electrical Engineering Dept. of Electrical Engineering
Harbin Institute of Technology Harbin Institute of Technology Harbin Institute of Technology
Harbin, China Harbin, China Harbin, China
dongxinjin_hit@outlook.com wlg2001@hit.edu.cn 16s006085@stu.hit.edu.cn

Abstract—A control strategy for TSVG is proposed in this
paper, which is a kind of hybrid static var generator (SVG),
based on Active disturbance rejection controller (ADRC) theory.
TSVG is a parallel topology between thyristor switch filter (TSF)
and SVG, and integrates the good features of reactive power
compensation and harmonic suppression together. In order to
improve the performance of SVG, a controller is proposed in this
paper that uses ADRC to replace the traditional PID controller of
current inner loop, and it could improve response speed and
reduce current overshoot at the same time to suppress power grid
voltage fluctuation at the point of common coupling (PCC) to do
good effects to power quality. Simulation and experiment results
provide evidence of the effectiveness of proposed TSVG system
and the feasibility and robustness of it in practical engineering
application. According to comparing with the traditional PID
controller, TSVG based on ADRC has advantages in shortening
response time and reducing output compensation current
overshoot, and the good performance in rejecting disturbance
from the uncertainty of internal parameters and outside is shown
in the results at the same time. Above all this paper can also
provide guiding reference for design of TSVG with ADRC in
theory and engineering.
Keywords-component: Auto Disterbance Rejection Controller
(ADRC); Hybrid Static Var generator (SVG); Reacive Power
Compensation; Power Quality
I. INTRODUCTION
In recent years, static var compensator (SVC) has been
widely used as an outstanding approach of reactive power
c
b
Grid
a
compensation. The traditional TSF has the advantages of low
product cost, simple design and construction, large capacity
and high reliability and widely used to compensate reactive
power and suppress harmonics, but due to the limitation of
response time and accuracy of TSF, SVG as a new reactive
power compensator has been put into use to provide reactive
power support fast and precisely to suppress the grid voltage
fluctuation [1-3].
A kind of new hybrid static var compensator is proposed in
the paper, which is composed of TSF and SVG [4], and the
topology of TSVG (TSF+SVG) is shown in Fig.1. The passive
TSF is used to compensate most of the reactive power and
suppress the main low-order harmonics, moreover the active
SVG is used to suppress the voltage fluctuation rapidly and
accurately. In order to improving response speed of SVG, lots
of control strategies have been studied. ADRC theory as a
inheritance of the traditional PID control strategy was proposed
by Professor Han at the end of 1990s[5]. In the literature [6], the
SVG based on the traditional PID controller is difficult to adapt
to the changing parameters, and can’t avoid the problem of
overshoot and delay in some complicated working condition at
the same time, and the design of the traditional PID controller
depends on the exact model of the SVG. Adaptive control can
improve the performance of traditional PID, but the complex
parameters will affect the control speed, resulting in time delay,
and affect the accuracy [7-8]. And SVG based on sliding mode
control theory has achieved good control effect, however, the
algorithm needs a very high sampling frequency, and it may
Load

SVG TSF

Fig.1 The diagram of TSVG (TSF+SVG)

cause the system chattering due to its discontinuity, and
produce high harmonics which are not easy to filter [9-10].
Project Supported by National Natural Science Foundation of China
(51177028).
Compared to the methods above, the controller based on
ADRC doesn’t depend on the exact model of the system and
doesn’t distinguish between internal and external disturbances,
and can reduce the overshoot of the traditional PID due to the
integral saturation without sacrificing the response speed, and

978-1-5386-2894-2/17/$31.00 ©2017 IEEE

978-1-5386-2894-2/17/$31.00 ©2017 IEEE

 2017 IEEE Transportation Electrification Conference and Expo, Asia-Pacific (ITEC Asia-Pacific)

has good adaptability and robustness by observing the system if v1 (t ) is close to v(t ) enough, v2 (t ) can be approximated as
mode to generate real-time compensation control signal [11-12]. a derivative v(t ) .
Intelligent control generally is no need for accurate model of
ESO is used to observe the status of the system as well as
the controlled object, but the convergence speed is slow, and it the disturbances from the system model itself and outside,
is difficult to be used in practical engineering[13].The which is the core of ADRC strategy by subtracting the
parameters in ADRC can be set by adaptive genetic algorithm, disturbances from the control signal directly to achieve the
chaos genetic algorithm, immune binary particle swarm purpose of feedback, instead of the traditional PID integrator to
optimization and linearization method etc [14-18]. The first-order eliminate the static error of the system. An unknown nonlinear
ADRC is proposed in this paper, whose parameters are based system affected by external disturbances is given by：
on simulation debugging, and compered with traditional PID
controller, the advantage in dynamic and static performance is x ( n ) (t )  f ( x(t ), x (1) (t ),..., x( n 1) (t ), t )   (t )  b0 u (t ) (3)
(1) ( n 1)
proof, besides, simulation and experiment results indicates the where f ( x(t ), x (t ),..., x (t ), t ) is the function of the
good operation of TSVG system. unknown system,  (t ) is the unknown external disturbance,
u (t ) is the input control quantity, x(t ), x(1) (t ),..., x( n 1) (t ) are
II. TSVG WITH ADRC n state variables of the nonlinear system. And we add a state
ADRC is a kind of improved control strategy based on the variable x ( n ) (t )  f ( x(t ), x(1) (t ),..., x( n 1) (t ), t )+ (t )   (t )
traditional PID control, which is used in the SVG part of the which reflect the sum of the unmodeled dynamics and external
hybrid static var compensator TSVG, so the basic principle and disturbance of the system to the state variables above and all of
structure of ADRC will be proposed in the section as well as the n  1 state variables consist of ESO, which is defined
the mathematical model of DQ transform and the control by: ：
strategy based on ADRC.  z1 (t )  z2 (t )  g1 ( z1 (t )  y (t ))
A. The theory of ADRC  z (t )  z (t )  g ( z (t )  y (t ))
 2 3 2 1
The typical ADRC consists of three parts, and the principle ...... (4)
of ADRC is shown in Fig.2, they are the tracking differentiator  z (t )  z (t )  g ( z (t )  y (t ))
(TD), the extended state observer (ESO) and the nonlinear state  n n 1 n 1

error feedback (NLSEF) control law.  zn 1 (t )   g n 1 ( z1 (t )  y (t ))

where z1 (t ), z2 (t ),..., zn 1 (t ) are the output of ESO, and
+
.
.
. gi ( ), i  1, 2,..., n  1 are suitable nonlinear functions. And in
.
. - +
TD NLSEF System
+
- order to satisfy that the estimated value zn 1 (t ) close to
-
 (t ) enough. gi ( ), i  1, 2,..., n  1 are defined by：
gi ( z1 (t )  y (t ))  i fal ( z1 (t )  y (t ),  ,  ) (5)
   sign( ),   
. 
.
.
.
ESO fal ( ,  ,  )    (6)
.
 1 sign( ),   
Fig.2 The principle diagram of ADRC 
where i ,  ,  are adjustable parameters, and fal is a kind of
TD can smooth the input signal to suppress overshoot and normal nonlinear control function, when 0    1 ,it has the
reduce the oscillation cycle, compared to the PID controller
characteristic: the more errors, the less gains, vice versa.
does not have actual differential element and can’t calculate
smoothing and reasonable errors. The input of TD is the given NLSEF control law is a kind of nonlinear feedback
input of the system and the output is the input signal and its structure using the past, present and future information of the
differentia of each order. Using the second-order system as an system errors, and beneficial to improve the speed and
example，the typical design of is defined by： robustness of the system at the same time, compared to the
v1 (t )  v2 (t ) traditional PID controller which uses the weighted sum of the
 (1) proportion, differential and integral of the system errors simply,
v2 (t )   f (v1 (t ), v2 (t )) that will result in contradiction between improving response
By second-order fast optimal control design algorithm，taking speed and reducing overshoot. NLSEF control law is expressed
f as an appropriate nonlinear function, TD is expressed as： as following function：
v1 (t )  v2 (t )  i (t )  vi (t )  zi (t ), i  1, 2,..., n
 
(2)  n (7)
 v2 (t ) v2 (t )
v2 (t )   r  sign(v1 (t )  v (t )  ) u0 (t )    i fal ( i (t ),  ,  )
 2r  i 1

where, r is the speed factor, which determines the tracking where  i ,  ,  are adjustable parameters. The final control
speed, when v1 (t )  r , it can track input signal v(t ) rapidly, signal with the total disturbance compensation is given as
follow.
 2017 IEEE Transportation Electrification Conference and Expo, Asia-Pacific (ITEC Asia-Pacific)

zn 1 (t ) some adjustable setting parameters in order to realize optimal

u (t )  u0 (t )  (8) control.
b0
The control strategy of TSVG based on ADRC is shown in
B. Modeling and control strategy design
Fig.3, and it is a kind of double closed-loop control. The DC
According to the SVG topology in Fig.1, the three-phase voltage loop is designed with traditional PI controller, the input
mathematical model of SVG and its model of DQ transform
error signal is the between the reference and the real measured
based on instantaneous reactive power theory are shown by：
value of the DC voltage of the DC bus capacitor, and the
 diCa (t ) output signal of the PI controller is reference value of the inner
 L dt  U Ca (t )  U Sa (t )  RiCa (t ) current loop, which is in d axis named iCd*
,and the outer loop

 diCb (t )
L  U Cb (t )  U Sb (t )  RiCb (t ) (9) DC Voltage Loop
 dt
 diCc (t ) PI ADRC
L  U Cc (t )  U Sc (t )  RiCc (t )
Inner
 dt dq PWM abc
Current SVG
 did (t ) Loop abc Diver dq
 L dt   Rid (t )   Liq (t )  U Sd  U Cd PI ADRC
 (10)
 L diq (t )   Ri (t )   Li (t )  U  U
q d Sq Cq PCC Voltage Loop
 dt
We can learn from (10) that id and iq are coupled with Fig.3 Block diagram of double closed-loop controlled SVG based on ADRC
each other, and grid voltage U Sd and U Sq , other parameters has the function of maintaining the stability of DC bus voltage.
such as L and R are difficult to measure exactly at the same Similarly, the PCC voltage loop designed with traditional PI
time. According to the basic idea of ADRC, U Sd and U Sq controller outputs the reference value iCq*
,and could suppress
could be regarded as the uncertainty of the SVG system model, the disturbance of the PCC voltage. The inner current loop is
and the sum of the uncertainties and the coupling terms is based on ADRC, which could reduce overshoot and improve
regarded as the disturbances of the SVG system, as response speed of the SVG system compared to the traditional
 d (t )   Liq (t )  U Sd and  q (t )   Lid (t )  U Sq ， and then PID controller, when there is reactive power disturbance.
we can establish a simplified model, which is expressed as
follow. III. EXPERIMENT AND ANALYSIS OF TSVG
 did (t )
 L dt   Rid (t )   d (t )  U Cd The simulation based on Matlab/SIMULINK and
 (11) experiment in lab have been done, and the feasibility and
 L diq (t )   Ri (t )   (t )  U reliability of the TSVG system are proved by the stable
q q Cq
 dt
On the basis of (11), we could design the decoupling active operation of the system. The hardware parameters and design
disturbance rejection controller. Assuming the given reference capacity of TSVG system are listed in Table I, and the
* *
value of inner current loop are iCd and iCq , since the d and q simulation is fully in accordance with this set of parameters.
axis controller principle are exactly the same, we could design And the ADRC parameters are 1   2   3 =0.005 , r1 =85 ,
the first-order ADRC based on q axis as an example, and TD 1 =0.8 , r21  650, r22  1000 ,  2 =0.75 r3 =800 ,  3 =0.8 , and
function is given by： the PID parameters are K P  25 , K I  10 . The performance
*
1  v1 (t )  iCq of TSVG is shown in Fig.4 and Fig.5.
 (12) The working condition in Fig.4(a) is that inputting reactive
v(t )  r1 fal (1 , 1 , 1 )
load at 0.32s, then switching on TSF 5th and 7th channel
ESO is shown by：
* respectively at 0.36s and 0.4s, operating SVG at 0.44s finally.
 2  z1 (t )  iCq
 We can learn from the diagram that TSF can compensate
 z1 (t )  z2 (t )  r21 fal ( 2 ,  2 ,  2 )  b0 u (t ) (13)
reactive by step, and the SVG can solve the rest of reactive
 z (t )  r fal ( ,  ,  )
 2 22 2 2 2 power, and the voltage at PCC can restore to the normal level.
NLSEF control law is shown by： THDu at PCC is 1.48% in Fig.4(b), which meets GB/T-14549-
 3  z1 (t )  v1 (t ) 93 standards. TSF can also suppress harmonics in Fig.5, and
 (14)
u0 (t )  r3 fal ( 3 ,  3 ,  3 ) we can learn from Table II that the harmonic current flows into
where the fal function is shown by (6), and the final control the TSF 5th and 7th channel respectively, and the THDi reduce
signal is shown by (8), and r1 , 1 , 1 , r21 , r22 ,  2 ,  2 , r3 ,  3 ,  3 are to 2.52%, which meets standards, too.
 2017 IEEE Transportation Electrification Conference and Expo, Asia-Pacific (ITEC Asia-Pacific)

TABLE I THE PARAMETERS OF TSVG TABLE II THE FFT ANALYSIS OF GRID CURRENT

Variable Parameter Time Fundamental THD 6k  1

(s) RMS(A) (%) Harmonic content
3-phase line voltage RMS ( U S ) 200 V
5th 7th 11th 13th 17th 19th
System frequency ( f ) 50 Hz
0.30 14.39 0.04 0.02 0.02 0.02 0.01 0.01 0.01
Connect reactor ( L ) 4 mH
0.34 45.78 8.75 7.49 3.85 1.26 0.94 0.40 0.40
Reactor’s resistance ( R ) 0.2 
0.38 44.52 3.10 1.18 2.07 1.25 0.94 0.37 0.30
DC bus capacitor ( C ) 1000 μF
0.42 44.26 2.52 0.99 1.46 1.06 0.80 0.42 0.32
DC capacitor voltage ( U dc ) 400 V

Current limitation of SVG ( I C max ) 30 A

Switching frequency ( f switch ) 10 k Hz

TSF Capacitor ( C5th ) 270 μF

th
5 Inductance ( L5th ) 1.6 mH

TSF Capacitor ( C7th ) 180 μF

th
7 Inductance ( L7th ) 1.2 mH
Fig.5 The of harmonic suppression performance of TSVG
Maximum active power ( Pmax ) 18 kVA

Maximum reactive power ( Qmax ) 16.7 kVA

90 deg

(a) The dynamic response of current inner loop

(a) The voltage of 3-phase grid and PCC

Fundamental (50Hz) = 163.2V , THDu= 1.48%

1.0
Mag (% of Fundamental)

0.8

0.6
(b)The dynamic response of current inner loop with disturbance
0.4

0.2

0
0 5
15 10
20 25 30 35 40
Harmonic order
(b) The FFT analysis of grid voltage after compensating
Fig.4 The reactive power compensation performance of TSVG with ADRC

(c) The voltage fluctuation at PCC

Fig.6 Comparison of ADRC and PID controller
 2017 IEEE Transportation Electrification Conference and Expo, Asia-Pacific (ITEC Asia-Pacific)

The comparison of ADRC and PID controller is indicated

in Fig.6. From Fig.6(a), the overshoot and response delay of
compensation current of SVG with are less than those of SVG
with PID controller, so SVG with ADRC is better in dynamic
performance. We can learn from Fig.6(b) that if there is a
disturbance at 150ms, current of PID has a greater unexpected
increment, so ADRC does better in anti-interference ability.
Fig.6(c) indicates the comparison of ADRC and PID controller
in suppressing voltage fluctuation due to reactive power, and
SVG with ADRC can restrain the disturbance more rapidly.
Above all, SVG with ADRC can suppress overshoot and
reduce the response delay to improve dynamic and static
performance, and can reject the disturbance from the unknown
of the system inside or the operation condition outside as an
ability of robustness.
The experiment results are shown in Fig.7 and Fig.8. The
experiment is carried out in lab, and the diagram of hardware is
(b) 3-phase voltage and grid current at PCC
shown in Fig.7(a). The HIOKI 3196 power quality analyzer
and Tektronix DPO 4104 digital phosphor oscilloscope are Fig.7 Reactive power compensation and harmonic suppression with TSVG
used to detect 3-phase voltage and current and compensations
current of SVG respectively. The 3-phase voltage at PCC and
grid current are shown in Fig.7(b), which reveal that the
proposed TSVG has good performance in compensating Voltage of bus capacitor(U dc )
reactive power and suppressing harmonics without causing
voltage and current distortion that is harmful to power quality, Compensation current of SVG(iC )
since THDu=2.27% and THDi=4.06%.The comparison of
ADRC and PID controller in dynamic and static performance
are shown in Fig.8 respectively. The response delay of Voltage at PCC(U PCC )
compensation current of ADRC is 16.8ms, but that of PID is
26.4ms, and the current has a overshoot peak at the same time,
which could be harmful to the robustness of the system and
equipment in heavy-load condition. And the voltage of the bus
capacitor of ADRC is smoothing than PID, too. All above
indicates the ADRC could improve the performance of inner
current loop of SVG, and enhance the compensation accuracy (a) SVG with PID
and speed.

Voltage of bus capacitor(U dc )

Compensation current of SVG(iC )

Voltage at PCC(U PCC )

(b) SVG with ADRC

Fig.8 Performance of SVG

(a) Diagram of experiment hardware in lab
IV. CONCLUSION
In this paper, A kind of hybrid var compensator called
TSVG, which is composed of TSF and SVG in parallel, is
proposed to compensate reactive power and suppress harmonic
and maintains the voltage at PCC stability to improve the
power quality. Due to the analysis of the simulation and
 2017 IEEE Transportation Electrification Conference and Expo, Asia-Pacific (ITEC Asia-Pacific)

experiment, the control strategy that using ADRC instead of [17] WU Lei, BAO Hong, DU Jing-li, WANG Cong-si. A learning algorithm
PID controller to ameliorate the inner current loop has a good for parameters of automatic disturbances rejection controller[J]. ACTA
automatica sinica, 2014, 40(3):556-560.
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[18] Han J Q. From PID to Active Disturbance Rejection Control[J]. IEEE
accuracy, the proposed method can reduce the overshoot and Transactions on Industrial Electronics, 2009, 56(3); 900-906.
the disturbance from unknown system inside and outside at the
same time. The work of the paper verify the good performance
in adaptability and robustness of the proposed compensation
system and also provide guiding reference for design of TSVG
with ADRC in theory and engineering

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