VHDL MCQ

DIGITAL SYSTEM DESIGN USING VHDL EC406
VIII SEM, ECE

In what aspect, HDLs differ from other computer programming languages?
A. No aspect; both are same
B. HDLs describe hardware rather than executing a program on a computer
C. HDLs describe software and not hardware
D. Other computer programming languages have more complexity
ANSWER: B
Which of the following HDLs are IEEE standards?
A. VHDL and Verilog
B. C and C++
C. Altera and Xilinx
D. Quartus II and MaxPlus II
ANSWER: A
Why we needed HDLs while having many traditional Programming languages?
A. Traditional programming languages are complex
B. HDLs are complementary to traditional programming languages to complete the design

process
C. Some characteristics of digital hardware couldn't be captured by traditional languages
D. HDLs offer more complexity than traditional programming languages.
ANSWER: C
Why do we need concurrent processing for describing digital systems in HDLs?
A. Faster processing than conventional programming languages
B. Concurrent processing is easier than sequential processing

VIII SEM, ECE
C. It allows taking timing constraints into consideration
D. Complexity of digital systems needs concurrent processing
ANSWER: D
VHDL is based on which of the following programming languages?
A. ADA programming language
B. C
C. Assembly
D. PHP
ANSWER: A
What is the advantage of using VHDL instead of any other HDL?
A. Week typing
B. Based on ADA
C. Portability
D. Easy to code
ANSWER: C
Which of the following is a characteristic of VHDL?
A. Case sensitive
B. Use of simple data types
C. Based on C programming language
D. Strongly typed language
ANSWER: D
VIII SEM, ECE
Which of the following is the basic building block of a design?
A. Architecture
B. Entity
C. Process
D. Package
ANSWER: B
A package in VHDL consists of _________
A. Commonly used architectures
B. Commonly used tools
C. Commonly used data types and subroutines
D. commonly used syntax and variables
ANSWER: C
Complete description of the circuit to be designed is given in _________
A. Architecture
B. Entity
C. Library
D. Configurations
ANSWER: A
What is the use of Configuration statement?
A. To configure the components exactly in design
B. To complete the design process by adding libraries
C. To add more than one entities into a single architecture

VIII SEM, ECE
D. To add some component in any entity architecture pair
ANSWER: D
In VHDL, Bus is a type of ________
A. Signal
B. Constant
C. Variable
D. Driver
ANSWER: A
What is the use of Generics in VHDL?
A. To turn on and off the drivers
B. To pass information to the entity
C. To describe architecture
D. To divide code into small processes
ANSWER: B
Driver can be seen as a _______ of the signal.
A. Part
B. Type
C. Final value
D. Source
ANSWER: D
Predefined data for an VHDL object is called ________

VIII SEM, ECE
A. Generic
B. Constant
C. Attribute
D. Library
ANSWER: C
Which of the following statement is true?
A. Package is a collection of Libraries
B. Library is a collection of Packages
C. Entity is a collection of Packages
D. Architecture is a collection of Entities
ANSWER: B
Which of the following is not an EDA tool?
A. Visual C++
B. Quartus II
C. Xilinx ISE
D. MaxPlus II
ANSWER: A
The process of transforming a design entry information of the circuit into a set of logic
equations in any EDA tool is known as _________
A. Simulation
B. Synthesis
C. Optimization
VIII SEM, ECE
D. Verification
ANSWER: B
Which of the following can be the name of an entity?
A. NAND
B. Nand_gate
C. Nand gate
D. AND
ANSWER: B
Which of the following mode of the signal is bidirectional?
A. IN
B. OUT
C. INOUT
D. BUFFER
ANSWER: C
In an assignment statement, OUT signal can be used only to the ___________
A. Left of <= operator
B. Right of <= operator
C. Any side of <= operator
D. Right of := operator
ANSWER: A
What does the architecture of an entity define?

VIII SEM, ECE
A. External interface
B. Internal functionality
C. Ports of the entity
D. Specifications
ANSWER: B
What does the declarative part of architecture contain?
A. Declaration of another entity
B. Declaration of libraries and packages
C. Declaration of local signals, constants or subprograms
D. Declaration of Architecture type
ANSWER: C
The statements in between the keyword BEGIN and END are called _______
A. Concurrent statements
B. Netlist
C. Declaration statement
D. Entity function
ANSWER: A
Which of the following can be a name of an architecture?
A. arch 1
B. 1arch
C. arch_1
D. architecture
VIII SEM, ECE
ANSWER: C
What is the correct method to declare a SIGNED type signal 'x'?
A. SIGNAL x : IN SIGNED
B. SIGNAL x : IN SIGNED
C. SIGNAL x : IN SIGNED (7 DOWNTO 0 )
D. SIGNAL x : IN SIGNED_VECTOR (7 DOWNTO 0 )
ANSWER: C
If a and b are two STD_LOGIC_VECTOR input signals, then legal assignment for a and b is
A. x <= a.b
B. x <= a OR b
C. x <= a + b
D. x <= a && b
ANSWER: B
What do we call the data type used for representing distance, current, voltage, time etc?
A. Integer
B. Real
C. Physical
D. Imaginary
ANSWER: C
What is the meaning of base unit?
A. Smallest possible unit of any physical literal

VIII SEM, ECE
B. SI unit of any physical literal
C. CGS unit for any physical literal
D. Fundamental building block of any design
ANSWER: A
RECORD in VHDL is similar to________ in C.
A. Array
B. File
C. Structure
D. Pointer
ANSWER: C
What is the difference between SIGNAL and VARIABLE?
A. The value of SIGNAL never varies whereas VARIABLE can change its value
B. SIGNAL can be used for input or output whereas VARIABLE acts as intermediate signals
C. SIGNAL depends upon VARIABLE for various operations
D. SIGNAL is global and VARIABLE is local to the process in which it is declared
ANSWER: D
Access types are similar to _________ in traditional programming languages.
A. Pointers
B. Arrays
C. Structures
D. Files
ANSWER: A
VIII SEM, ECE
How the keyword "TYPE" is used?
A. TYPE datatype_name IS type_from_predefined_datatypes;
B. TYPE datatype_name IS datatype_range;
C. TYPE datatype_range IS datatype_name;
D. USE TYPE datatype_range IS datatype_name;
ANSWER: B
Which of the following is wrong declaration for a new data type?
A. TYPE my_logic IS RANGE 0 to 100;
B. TYPE my_logic IS ('0', '1', '2');
C. TYPE my_logic IS ARRAY (0 TO 3) OF BIT;
D. TYPE my_logic IS <0 TO 20 >
ANSWER: D
A SUBTYPE can be defined as _________
A. A TYPE under a TYPE (nested)
B. A type of INTEGER datatype
C. A TYPE with some constraint
D. A TYPE without any constraint
ANSWER: C
Which of the following is the correct syntax for declaring a SUBTYPE?
A. TYPE type_name IS type_range AND SUBTYPE subtype_name IS subtype_range
B. SUBTYPE subtype_name IS subtype_range TYPE type_name

VIII SEM, ECE
C. SUBTYPE subtype_name TYPE type_name IS subtype_range
D. SUBTYPE subtype_name IS TYPE subtype_range
ANSWER: D
Which of the following logical operator has highest precedence?
A. NAND
B. NOR
C. NOT
D. EXOR
ANSWER: C
Which of the following VHDL statement is equivalent to NAND operation, if y, a and b are
SIGNALS?
A. y <= NOT a AND b
B. y <= NOT a OR NOT b
C. y <<= NOT a AND NOT b
D. y <<= NOT (a OR b)
ANSWER: B
The operator '&' is called the_____ operator.
A. Logical AND operator
B. Bitwise AND operator
C. Arithmetic addition operator
D. Concatenation operator
ANSWER: D
VIII SEM, ECE
What is the type of result of MOD operator?
A. Numeric
B. Integer
C. Array
D. Bit
ANSWER: B
The operators like =, /=, <, >, >= are called _________
A. Arithmetic operators
B. Concatenation operators
C. Logical operators
D. Relational operators
ANSWER: D
What is the type of result for comparison operators?
A. Boolean
B. Integer
C. Numeric
D. Array
ANSWER: A
The most basic form of behavioral modeling in VHDL is_______
A. IF statements
B. Assignment statements
VIII SEM, ECE
C. Loop statements
D. WAIT statements
ANSWER: B
For any concurrent assignment statement, which of the following is true?
A. The statement is executed once
B. The statement is executed twice
C. The value of left operand is assigned to right operand
D. The statement is executed as many times as the value changes
ANSWER: D
The main problem with behavioral modeling is ________
A. Asynchronous delays
B. Simulation
C. No delay
D. Supports single driver only
ANSWER: A
What is the use of simulation deltas in VHDL code?
A. To create delays in simulation
B. To assign values to signals
C. To order some events
D. Evaluate assignment statements
ANSWER: C
VIII SEM, ECE
Which function is used to create a single value for multiple driver signals?
A. Resolution function
B. Package
C. Concurrent assignments
D. Sequential assignments
ANSWER: A
A signal is a is driven by two signals b and c. How the value of b and c will be resolved to
calculate the value of a?
A. By short circuiting both driver
B. By open circuiting one driver
C. By AND operation between two drivers
D. By NOT operation of both drivers
ANSWER: A
Which of the following is default delay in VHDL?
A. Inertial delay
B. Transport delay
C. Delta delay
D. Wire delay
ANSWER: A
The inertia value in inertial delay model is equal to _________
A. Initial value
B. Delay
VIII SEM, ECE
C. Input value at a specific time
D. Output value at a specific time
ANSWER: B
Transport delay is a kind of __________
A. Synthesis delay
B. Simulation delay
C. Inertial delay
D. Wire delay
ANSWER: D
A buffer with single input A and single output B has a delay of 20 nanosecond. If the value
of input A changes after 10 ns from 0 to 1 and it changes again from 1 to 0 at 20 ns. At what
time, the value of output B will be 1, if the inertial delay model is used?
A. 30 ns
B. 40 ns
C. 20 ns
D. Output will remain zero
ANSWER: D
What do you mean by a block?
A. An object of architecture
B. Interconnection of two or more signals
C. A part of an entity
D. A sub module in an architecture body
ANSWER: D
VIII SEM, ECE
What is the scope of variables or signals declared in the block statement?
A. Global to the design
B. Local to the architecture
C. Local to the block itself
D. Local to the entity of which architecture is defined
ANSWER: C
Which of the following defines the interface to the block?
A. Block declaration part
B. Block header
C. Block statement part
D. Generic declaration part
ANSWER: B
Guarded block has an extra ________ expression.
A. Conditional
B. Declarative
C. Block
D. Guard
ANSWER: D
What should be the type of the value of guard expression?
A. BOOLEAN
B. INTEGER
VIII SEM, ECE
C. REAL
D. BIT_VECTOR
ANSWER: A
What is the main purpose of using blocks?
A. To improve reusability
B. To improve conditional execution
C. To improve readability
D. To improve speed of execution
ANSWER: C
Which of the following is defined in structural modeling?
A. The structure of circuit
B. Behavior of circuit on different inputs
C. ata flow form input to output
D. Functional structure
ANSWER: A
Which of the following is not a way of partitioning a design?
A. Component
B. Block statement
C. Processes
D. Generics
ANSWER: C
VIII SEM, ECE
What is the basic unit of structural modeling?
A. Process
B. Component declaration
C. Component instantiation
D. Block
ANSWER: C
Which of the following is similar to entity declaration in structural modeling?
A. Component instantiation
B. Component declaration
C. Port map
D. Generic map
ANSWER: B
What do you mean by component instantiation?
A. To use the component
B. To describe external interface of the component
C. To declare the gate level components
D. To remove any component from the design
ANSWER: A
The structural model is similar to___________
A. Boolean relations of the circuit
B. Schematic block diagram of the circuit
C. Timing relations of the circuit

VIII SEM, ECE
D. Components of the circuit
ANSWER: B
Which of the following is correct syntax for component instantiation?
A. instantiate : component_name PORT MAP (port_list);
B. label : instantiate COMPONENT PORT MAP (port_list);
C. label : component_name PORT MAP (port_list);
D. label : instantiate component_name PORT MAP (port_list)
ANSWER: C
In which part of VHDL code, components must be declared?
A. Library
B. Entity
C. Architecture
D. Configuration
ANSWER: C
Which of the following function is used to map the component?
A. COMPONENT INSTANTIATE
B. PORT MAP
C. GENERIC MAP
D. USE
ANSWER: B
How many ways are there in VHDL to map the components?

VIII SEM, ECE
A. 1
B. 2
C. 3
D. 4
ANSWER: B
What is the property of Positional mapping?
A. Easier to write
B. Less error prone
C. Ports can be left unconnected
D. Difficult to write
ANSWER: A
How can we use an assignment statement as a sequential assignment?
A. By using keyword WAIT
B. By using delay mechanism
C. By using conditional statements
D. By using it in any process
ANSWER: D
The concurrent assignment statement is activated whenever ______
A. The execution is scheduled
B. The value of the target is needed
C. The waveform associated changes its value
D. The process is terminated

VIII SEM, ECE
ANSWER: C
The conditional assignment statement is a _________ assignment.
A. Sequential
B. Concurrent
C. Selected
D. None of the above
ANSWER: B
Delays are generally ignored in________ assignments statements.
A. Concurrent
B. Conditional
C. Sequential
D. Selected
ANSWER: C
The selected concurrent statement is equivalent to ________ sequential statement.
A. If else
B. Loop
C. Wait
D. Case
ANSWER: D
Those statement which are placed under ________ are concurrent.
A. Process
VIII SEM, ECE
B. Function
C. Architecture
D. Procedure
ANSWER: C
Which of the following can't be implemented with concurrent statements only?
A. Multiplexer
B. Decoder
C. Adder
D. Counter
ANSWER: D
Variable assignment statement executes in ______ time.
A. Immediately(zero)
B. After delay specified
C. After one clock cycle
D. After two clock cycles
ANSWER: A
Which of the following statement is a zero delay statement?
A. y <= x AFTER 10 ns
B. y <= TRANSPORT x AFTER 10 ns
C. y <= x
D. y := x AFTER 10 ns
ANSWER: D
VIII SEM, ECE
The process can be __________ by using WAIT statements.
A. Suspended
B. Resumed
C. Suspended as well as resumed
D. Cannot be determined
ANSWER: C
A postponed process runs when ___________
A. All the other processes have completed
B. After completion of one particular process
C. Concurrently with all other processes
D. First of all processes
ANSWER: A
Which of the following statement can't be used inside a process?
A. WAIT
B. IF ELSE
C. Variable declaration
D. PORT MAP
ANSWER: D
A combinational process must have all the _________ signals in its sensitivity list.
A. Input
B. Output
VIII SEM, ECE
C. Declared
D. Used
ANSWER: A
Which of the following circuit can't be described without using a process statement?
A. Multiplexer
B. D flip-flop
C. Decoder
D. Comparator
ANSWER: B
Which of the following signal uses keyword EVENT?
A. Variables
B. Output
C. Input
D. Clock
ANSWER: D
If the condition of IF statement is an expression, then what should be the type of the result
of the expression?
A. Bit
B. Std_logic
C. Boolean
D. Integer
ANSWER: C
VIII SEM, ECE
In a clocked process, IF statement is used to _____
A. To run statements sequentially
B. To use concurrent assignment within process
C. To detect the clock signal
D. To implement sequential circuit
ANSWER: C
What should be the type of choices in the CASE statement?
A. Boolean
B. Integer
C. Same as expression
D. No restriction on the type
ANSWER: C
What kind of circuit may be described by using following statement? ASSERT NOT (s='1'
and r = '1') REPORT ''INVALID! S and R both can't be 1" SEVERITY ERROR
A. Flip flop
B. Multiplexer
C. Decoder
D. Counter
ANSWER: A
A constant is declared in Architecture, it will be accessible in ________
A. Whole code
VIII SEM, ECE
B. Within the same architecture
C. In the entity associated and corresponding architecture
D. In the process within the architecture
ANSWER: B
If a user wants to include his/her own package in the body, which library he/she must use?
A. STD
B. IEEE
C. WORK
D. STD_LOGIC
ANSWER: C
As a VHDL designer, what should you make sure about the design so that it is synthesized
correctly?
A. It must use a configuration, when more than one architecture is used
B. All the component ports and entity ports must be matched
C. A configuration must be there always
D. A configuration is used when ports are mismatched
ANSWER: B
Why we need to include all the input signals in the sensitivity list of the process?
A. To monitor the output continuously
B. To monitor the input continuously
C. To make the circuit synthesizable by EDA tools
D. No special purpose
VIII SEM, ECE
ANSWER: B
A package is designed called mux4to1_package, in which a component called mux4to1 is

defined, which is a 4 to 1 multiplexer. Now a user wants to design a 16 to 1 MUX by using
the same component only, how many times he needs to use the PORT MAP statement?
A. 2
B. 3
C. 4
D. 5
ANSWER: D
Which of the following is not a combinational circuit?
A. Adder
B. Code convertor
C. Multiplexer
D. Counter
View Answer
ANSWER: D
In a given combinational circuit, the concurrent statements are used with selected
assignments using WHEN and ELSE keyword. What is the other alternative to implement
the same?
A. WITH-SELECT
B. WITH-SELECT-WHEN
C. IF-ELSE
D. CASE
VIII SEM, ECE
ANSWER: B
For using a process to implement combinational circuit, which signals should be in the
sensitivity list?
A. Inputs of the circuit
B. Outputs of the circuit
C. Both of the Inputs and Outputs
D. No signal should be in the sensitivity list
ANSWER: A
Shift registers comprise of which flip-flops?
A. D flip-flops
B. SR flip-flops
C. JK flip-flops
D. T flip-flops
ANSWER: A
Four bits shift register enables shift control signal in how many clock pulses?
A. Two clock pulses
B. Three clock pulses
C. Four clock pulses
D. Five clock pulses
ANSWER: C
Which of the following flip-flop is used by ring counter?

VIII SEM, ECE
A. D flip-flops
B. SR flip-flops
C. JK flip-flops
D. T flip-flops
ANSWER: A
How many types of shift operators are there in VHDL?
A. Three
B. Four
C. Five
D. Six
ANSWER: D
In ______ counter universal clock is not used.
A. Synchronous counter
B. Asynchronous counter
C. Decade counter
D. Ring counter
ANSWER: B
Synchronous counter use ____ global clock, unlike asynchronous counter.
A. One
B. Two
C. Three
D. zero
VIII SEM, ECE
ANSWER: A
How many different states does a decade counter count?
A. Eight
B. Nine
C. Ten
D. Eleven
ANSWER: C
Output values of Moore type FSM are determined by its ________
A. Input values
B. Output values
C. Clock input
D. Current state
ANSWER: D
What happens if the input is high in FSM?
A. Change of state
B. No transition in state
C. Remains in a single state
D. Invalid state
ANSWER: A
What happens if the input is low in FSM?
A. Change of state
VIII SEM, ECE
B. No transition in state
C. Remains in a single state
D. Invalid state
ANSWER: B
In FSM diagram what does circle represent?
A. Change of state
B. State
C. Output value
D. Initial state
ANSWER: B
In the FSM diagram, what does arrow between the circles represent?
A. Change of state
B. State
C. Output value
D. Initial state
ANSWER: A
In the FSM diagram, what does the information below the line in the circle represent?
A. Change of state
B. State
C. Output value
D. Initial state
ANSWER: C
VIII SEM, ECE
Moore machine has _____ states than mealy machine.
A. Fewer
B. More
C. Equal
D. Negligible
ANSWER: B
State transition happens _______ in every clock cycle.
A. Once
B. Twice
C. Thrice
D. Four times
ANSWER: A
Output values of mealy type FSM are determined by its ________
A. Input values
B. Output values
C. Both input values and current state
D. Current state
ANSWER: C
What kind of output does mealy machine produce?
A. Asynchronous
B. Synchronous
VIII SEM, ECE
C. Level
D. Pulsed
ANSWER: A
States in FSM are represented by ________
A. Bits
B. Bytes
C. Word
D. Character
ANSWER: A
What is the first step in writing the VHDL for an FSM?
A. To define the VHDL entity
B. Naming the entity
C. Defining the data type
D. Creating the states
ANSWER: A
Which of the following react faster to inputs?
A. Sequencer
B. Generators
C. Mealy machines
D. Moore machines
ANSWER: C
VIII SEM, ECE
What is the first state of FSM?
A. Wait loop state
B. Initial state
C. Output state
D. Activate pulse state
ANSWER: B
Mealy machines have _____ states than Moore machine.
A. Fewer
B. More
C. Equal
D. Negligible
ANSWER: A
Timing performance of design is checked by which of the following simulation mode?
A. Gate-level
B. Behavioural
C. Transistor-level
D. Switch-level
ANSWER: A
The statements in the initial construct constitute ________
A. End block
B. Initial block
C. Begin block
VIII SEM, ECE
D. Always block
ANSWER: B

VHDL MCQ

Transféré par

Informations du document

Copyright

Formats disponibles

Partager ce document

Partager ou intégrer le document

Options de partage

Avez-vous trouvé ce document utile ?

Ce contenu est-il inapproprié ?

Droits d'auteur :

Formats disponibles

VHDL MCQ

Transféré par

Droits d'auteur :

Formats disponibles

DIGITAL SYSTEM DESIGN USING VHDL EC406

VIII SEM, ECE

A. No aspect; both are same

B. HDLs describe hardware rather than executing a program on a computer

C. HDLs describe software and not hardware

D. Other computer programming languages have more complexity

Which of the following HDLs are IEEE standards?

A. VHDL and Verilog

C. Altera and Xilinx

D. Quartus II and MaxPlus II

Why we needed HDLs while having many traditional Programming languages?

A. Traditional programming languages are complex

B. HDLs are complementary to traditional programming languages to complete the design

C. Some characteristics of digital hardware couldn't be captured by traditional languages

D. HDLs offer more complexity than traditional programming languages.

Why do we need concurrent processing for describing digital systems in HDLs?

A. Faster processing than conventional programming languages

B. Concurrent processing is easier than sequential processing

D. Complexity of digital systems needs concurrent processing

VHDL is based on which of the following programming languages?

A. ADA programming language

What is the advantage of using VHDL instead of any other HDL?

Which of the following is a characteristic of VHDL?

B. Use of simple data types

C. Based on C programming language

D. Strongly typed language

A package in VHDL consists of _________

A. Commonly used architectures

B. Commonly used tools

C. Commonly used data types and subroutines

D. commonly used syntax and variables

Complete description of the circuit to be designed is given in _________

What is the use of Configuration statement?

A. To configure the components exactly in design

B. To complete the design process by adding libraries

C. To add more than one entities into a single architecture

In VHDL, Bus is a type of ________

What is the use of Generics in VHDL?

A. To turn on and off the drivers

B. To pass information to the entity

D. To divide code into small processes

Driver can be seen as a _______ of the signal.

Predefined data for an VHDL object is called ________

Which of the following statement is true?

A. Package is a collection of Libraries

B. Library is a collection of Packages

C. Entity is a collection of Packages

D. Architecture is a collection of Entities

Which of the following is not an EDA tool?

Which of the following can be the name of an entity?

Which of the following mode of the signal is bidirectional?

In an assignment statement, OUT signal can be used only to the ___________

A. Left of <= operator

B. Right of <= operator

C. Any side of <= operator

What does the architecture of an entity define?

C. Ports of the entity

What does the declarative part of architecture contain?

A. Declaration of another entity

B. Declaration of libraries and packages

C. Declaration of local signals, constants or subprograms

D. Declaration of Architecture type

Which of the following can be a name of an architecture?

What is the correct method to declare a SIGNED type signal 'x'?