2.

1 The Xilinx XC4000 Series Design Process 1

THE ECE 554 XILINX DESIGN

PROCESS
• Design Process Overview
• Design References
• Xilinx Libraries
• Design Tutorial
• What’s Next
1/23/2001 1

Design Process Steps

• Definition of System Requirements
– Example: ISA (Instruction Set Architecture) for CPU
– Includes software and hardware interfaces including
timing.
– May also include cost, speed, reliability and
maintainability specifications
• Definition of System Architecture
– Example: High-level HDL (Hardware Description
Language) representation - this is not required in
ECE 554 but is done in the real world)
– Useful for system validation and verification and as a
basis for lower level design execution and validation
or verification.
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 2.1 The Xilinx XC4000 Series Design Process 2

Design Process Steps(Continued)

• Refinement of System Architecture
– In manual design, descent in hierarchy, designing
increasingly lower-level components
– In synthesized design, transformation of high-level
HDL to “synthesizable” register transfer level (RTL)
HDL
• Logic Design or Synthesis
– In manual or synthesized design, development of logic
design in terms of library components
– Result is logic level schematic or netlist representation
or combinations of both.
– Both manual design or synthesis typically involve
1/23/2001 optimization of cost, area, or delay. 3

Design Process Steps (Continued)

• Implementation
– Conversion of the logic design to physical
implementation
– Involves the processes of:
• mapping of logic to physical elements,
• placing of resulting physical elements,
• and routing of interconnections between the elements.
– In case of SRAM-based FPGAs, represented by the
programming bitstream which generates the physical
implementation in the form of CLBs, IOBs and the
interconnections between them

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 2.1 The Xilinx XC4000 Series Design Process 3

Design Process Steps (Continued)

• Validation (used at number of steps in the process)
– At architecture level - functional simulation of HDL
– At RTL level- functional simulation of RTL HDL
– At logic design or synthesis - functional simulation of
gate-level circuit - not usually done in ECE 554
– At implementation - timing simulation of schematic,
netlist or HDL with implemention based timing
information (functional simulation can also be useful
here)
– At programmed FPGA level - in-circuit test of function
and timing

1/23/2001 5

Xilinx HDL/Core Design Flow

DESIGN ENTRY

RTL HDL EDITING CORE GENERATION

RTL HDL-CORE
SIMULATION

SYNTHESIS

IMPLEMENTATION

TIMING FPGA PROGRAMMING

1/23/2001 SIMULATION & IN-CIRCUIT TEST 6
 2.1 The Xilinx XC4000 Series Design Process 4

Xilinx HDL/Core Design Flow

- HDL Editing
Accessed within
DESIGN WIZARD HDL Editor LANGUAGE ASSISTANT

HDL Module Language Construct

Frameworks Templates

HDL EDITOR

RTL HDL Files

1/23/2001 7

Xilinx HDL/Core Design Flow

- Core Generation
Select core and
specify input
parameters

CORE GENERATOR

EDIF netlist for HDL instantiation Other core_name files

core_name module for
core_name
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 2.1 The Xilinx XC4000 Series Design Process 5

Xilinx HDL/Core Design Flow

- HDL Functional Simulation
HDL instantiation Set Up and Map RTL HDL Files
module for work library
core_name

Testbench HDL EDIF netlists for

Compile HDL Files core_names
Files

Test Inputs or MODELSIM

Force Files
Functional Simulate

Waveforms
or List Files
1/23/2001 9

Xilinx HDL Design Flow

- Synthesis
All HDL Files

Edit FPGA Express Select Top Level EDIF netlists for

Synthesis Constraints core_names

Synthesis/Implement- Select Target Device

ation Constraints FPGA
EXPRESS
Synthesize

Gate/Primitive Netlist Synthesis Report

Files (EDIF or XNF) Files

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 2.1 The Xilinx XC4000 Series Design Process 6

Xilinx HDL/Core Design Flow -

Implementation
Gate/Primitive Netlist
Files (XNF or EDN)

Netlist
Translation

XILINX DESIGN
Map MANAGER

Place &
Model Extraction Route
Timing Model Gen
HDL or EDIF for Create
Implemented Design Bitstream Standard Delay
Format File
1/23/2001 BIT File 11

Xilinx HDL/Core Design Flow

- Timing Simulation
HDL or EDIF for
Standard Delay Format File
Implemented Design

Set Up and Map

work Directory

Testbench HDL Files Compile HDL Files

Test Inputs, Compiled HDL

MODELSIM
Force Files

HDL Simulate

Waveforms
or List Files
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 2.1 The Xilinx XC4000 Series Design Process 7

Xilinx HDL Design Flow

- Programming and In-Circuit
Verification
Bit File

Input Byte GXSLOAD

GXSPORT ECE 554 Other Inputs

FPGA Board

Outputs

1/23/2001 13

Design References
• Manuals On-Line Using dtext Viewer (Docsan) -
For printing, download zipped pdf files. Go to:
http://toolbox.xilinx.com/docsan/3_1i/
– FPGA Complier II/FPGA Express Verilog HDL Reference
Manual 3.1i - Essential guide to writing Verilog for FPGA
Express - suggest you download and print a copy for your use 2
pages/page
– Synthesis and Simulation Guide 3.1i - Lots of useful
information on writing HDL code
– CORE Generator Guide 3.1i - You will use cores lots, so can be
useful.
– Libraries Guide 3.1i - Useful only if you want to instantiate parts
– Constraints Editor Guide - Useful if you want to use timing
constraints in particular
– Foundation Series 3.1i Release Notes and Installation Guide -
Good for finding bugs, but always out-of-date - use on-line
1/23/2001 Answers database instead 14
 2.1 The Xilinx XC4000 Series Design Process 8

Design References (Continued)

• Manuals On-Line Using dtext Viewer (Docsan) - For
printing, download zipped pdf files. Go to:
http://toolbox.xilinx.com/docsan/3_1i/
• The following guides are occasionally useful, but far less
frequently:
– Design Manager/Flow Engine Guide
– Development System Reference Guide 3.1i
– Timing Analyzer Guide 3.1i
– Foundation Series 3.1i Quick Start Guide
– Foundation Series 2.1i User Guide
– FPGA Compiler II/FPGA Express VHDL Reference Manual 3.1i

• Databook, App. Notes, and Answers database On-Line at:

http://support.xilinx.com/support/support.htm
1/23/2001 15

The Xilinx Libraries

• Useful only if you have to instantiate (in your
HDL) Xilinx primitives or macros (not all can
be instantiated) from the Libraries Guide 3.1i
• Note selection guide includes CLB counts and
section at front on notation used to describe
macros.

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 2.1 The Xilinx XC4000 Series Design Process 9

Design Practices
• Use Synchronous Design
– CLBs are actually reading functions from SRAM!
– Avoid Clock Gating
– Avoid Ripple Counters
– Avoid Use of Direct Sets and Resets except for
initialization
– Synchronize asynchronous signals as needed.
– Study Timing Issues handout

1/23/2001 17

What’s Next
• Verilog HDL – Introductory lecture next
week will give an overview of Verilog, our
HDL language of choice
• HDL/Core Design Flow – Design tutorial
next week will employ the flow described
for a Verilog HDL/core example

1/23/2001 18