Advanced Power MOSFET SFS9634

FEATURES
BVDSS = -250 V
Avalanche Rugged Technology
Rugged Gate Oxide Technology
RDS(on) = 1.3 Ω
Lower Input Capacitance ID = -3.4 A
Improved Gate Charge
Extended Safe Operating Area
Lower Leakage Current : 10 µA (Max.) @ VDS = -250V
TO-220F
Low RDS(ON) : 0.876 Ω (Typ.)

1
2
3

1.Gate 2. Drain 3. Source

Absolute Maximum Ratings

Symbol Characteristic Value Units
VDSS Drain-to-Source Voltage -250 V
o
Continuous Drain Current (TC=25 C) -3.4
ID o A
Continuous Drain Current (TC=100 C) -2.6
IDM Drain Current-Pulsed O
1 -14 A
VGS Gate-to-Source Voltage +
_ 30 V
EAS Single Pulsed Avalanche Energy O
2 145 mJ
IAR Avalanche Current O
1 -3.4 A
EAR Repetitive Avalanche Energy O
1 3.3 mJ
dv/dt Peak Diode Recovery dv/dt O
3 -4.8 V/ns
o
Total Power Dissipation (TC=25 C) 33 W
PD o
Linear Derating Factor 0.26 W/ C
Operating Junction and
TJ , TSTG - 55 to +150
Storage Temperature Range
o
Maximum Lead Temp. for Soldering C
TL 300
Purposes, 1/8 “ from case for 5-seconds

Thermal Resistance
Symbol Characteristic Typ. Max. Units
RθJC Junction-to-Case -- 3.79 o
C/W
RθJA Junction-to-Ambient -- 62.5

Rev. B

©1999 Fairchild Semiconductor Corporation

 P-CHANNEL
SFS9634 POWER MOSFET

Electrical Characteristics (TC=25oC unless otherwise specified)

Symbol Characteristic Min. Typ. Max. Units Test Condition
BVDSS Drain-Source Breakdown Voltage -250 -- -- V VGS=0V,ID=-250µA
∆BV/∆TJ Breakdown Voltage Temp. Coeff. -- -0.22 --
o
V/ C ID=-250µA See Fig 7
VGS(th) Gate Threshold Voltage -2.0 -- -4.0 V VDS=-5V,ID=-250µA
Gate-Source Leakage , Forward -- -- -100 VGS=-30V
IGSS nA
Gate-Source Leakage , Reverse -- -- 100 VGS=30V
-- -- -10 VDS=-250V
IDSS Drain-to-Source Leakage Current µA o
-- -- -100 VDS=-200V,TC=125 C
Static Drain-Source
RDS(on) -- -- 1.3 Ω VGS=-10V,ID=-1.7A O
4
On-State Resistance
gfs Forward Transconductance -- 3.2 -- Ω VDS=-40V,ID=-1.7A O
4

Ciss Input Capacitance -- 750 975

VGS=0V,VDS=-25V,f =1MHz
Coss Output Capacitance -- 110 165 pF
See Fig 5
Crss Reverse Transfer Capacitance -- 45 65
td(on) Turn-On Delay Time -- 13 35
VDD=-125V,ID=-5.0A,
tr Rise Time -- 20 50
ns RG=12 Ω
td(off) Turn-Off Delay Time -- 40 90
tf Fall Time -- 16 40
See Fig 13 O
4 O
5

Qg Total Gate Charge -- 29 37 VDS=-200V,VGS=-10V,

Qgs Gate-Source Charge -- 5.4 -- nC ID=-5.0A
Qgd Gate-Drain( “ Miller “ ) Charge -- 15.5 -- See Fig 6 & Fig 12 O
4 O
5

Source-Drain Diode Ratings and Characteristics

Symbol Characteristic Min. Typ. Max. Units Test Condition
IS Continuous Source Current -- -- -3.4 Integral reverse pn-diode
A
ISM Pulsed-Source Current O
1 -- -- -14 in the MOSFET
o
VSD Diode Forward Voltage O4 -- -- -5.0 V TJ=25 C,IS=-3.4A,VGS=0V
o
trr Reverse Recovery Time -- 170 -- ns TJ=25 C,IF=-5.0A
Qrr Reverse Recovery Charge -- 1.17 -- µC diF/dt=100A/µs O
4

Notes ;
O1 Repetitive Rating : Pulse Width Limited by Maximum Junction Temperature
o
O2 L=20mH, I =-3.4A, V =-50V, R =27Ω*, Starting T =25 C
AS DD G J
_ _ _
O3 ISD <-5.0A, di/dt < 400A/µs, VDD < BVDSS , Starting T J =25oC
O4 Pulse Test : Pulse Width = 250 µs, Duty Cycle <_ 2%
O5 Essentially Independent of Operating Temperature
 P-CHANNEL
POWER MOSFET SFS9634
Fig 1. Output Characteristics Fig 2. Transfer Characteristics
V GS
Top : - 15 V
[A]

[A]
101 - 10 V 101
- 8.0 V
- 7.0 V
-ID , Drain Current

-ID , Drain Current

- 6.0 V
- 5.5 V
- 5.0 V
Bottom : - 4.5 V

100 100 150 oC

25 oC @ Notes :
1. VGS = 0 V
@ Notes : 2. VDS = -40 V
1. 250 µs Pulse Test 3. 250 µs Pulse Test
- 55 oC
2. TC = 25 oC
10-1 10-1
10-1 100 101 2 4 6 8 10
-VDS , Drain-Source Voltage [V] -VGS , Gate-Source Voltage [V]

Fig 3. On-Resistance vs. Drain Current Fig 4. Source-Drain Diode Forward Voltage
[A]
Drain-Source On-Resistance

3.0
-IDR , Reverse Drain Current

101
2.5
RDS(on) , [Ω ]

2.0

VGS = -10 V
1.5
100

1.0 150 oC

@ Notes :
25 oC 1. VGS = 0 V
0.5 VGS = -20 V 2. 250 µs Pulse Test
@ Note : TJ = 25 oC

0.0 10-1
0 3 6 9 12 15 18 21 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
-ID , Drain Current [A] -VSD , Source-Drain Voltage [V]

Fig 5. Capacitance vs. Drain-Source Voltage Fig 6. Gate Charge vs. Gate-Source Voltage
1500
[V]

Ciss= Cgs+ Cgd ( Cds= shorted )

Coss= Cds+ Cgd VDS = -50 V
10
[pF]

-VGS , Gate-Source Voltage

Crss= Cgd VDS = -125 V

C iss
VDS = -200 V
1000
Capacitance

C oss
5
@ Notes :
500 C rss 1. VGS = 0 V
2. f = 1 MHz

@ Notes : ID =-5.0 A

0 0
100 101 0 5 10 15 20 25 30
-VDS , Drain-Source Voltage [V] QG , Total Gate Charge [nC]
 P-CHANNEL
SFS9634 POWER MOSFET

Fig 7. Breakdown Voltage vs. Temperature Fig 8. On-Resistance vs. Temperature

Drain-Source Breakdown Voltage

1.2 3.0

Drain-Source On-Resistance
-BVDSS , (Normalized)

RDS(on) , (Normalized)
2.5
1.1
2.0

1.0 1.5

1.0
0.9 @ Notes : @ Notes :
1. VGS = 0 V 0.5 1. VGS = -10 V
2. ID = -250 µA 2. ID = -2.5 A

0.8 0.0
-75 -50 -25 0 25 50 75 100 125 150 175 -75 -50 -25 0 25 50 75 100 125 150 175
o
TJ , Junction Temperature [ C] TJ , Junction Temperature [oC]

Fig 9. Max. Safe Operating Area Fig 10. Max. Drain Current vs. Case Temperature
[A]

4
[A]

Operation in This Area

-ID , Drain Current

is Limited by R DS(on)
-ID , Drain Current

101 3
0.1 ms
1 ms
10 ms
0 2
10 DC

@ Notes :
1. TC = 25 oC
2. TJ = 150 oC 1
10-1
3. Single Pulse

0
100 101 102 25 50 75 100 125 150
-VDS , Drain-Source Voltage [V] Tc , Case Temperature [oC]

Fig 11. Thermal Response

Thermal Response

D=0.5
@ Notes :
10 0 o C/W Max.
0.2 1. Zθ J C (t)=3.79
2. Duty Factor, D=t1 /t 2
0.1 3. TJ M -T C =P D M *Z θ J C (t)
0.05 P.DM
0.02
(t) ,

10- 1 0.01 t1.

t2.
θJC

single pulse
Z

10- 5 10- 4 10 - 3 10 - 2 10 - 1 100 10 1

t 1 , Square Wave Pulse Duration [sec]
 P-CHANNEL
POWER MOSFET SFS9634
Fig 12. Gate Charge Test Circuit & Waveform

“ Current Regulator ”
VGS
Same Type
50KΩ as DUT Qg
12V 200nF
300nF -10V

VDS
VGS Qgs Qgd

DUT

-3mA
R1 R2

Current Sampling (IG) Current Sampling (ID)

Charge
Resistor Resistor

Fig 13. Resistive Switching Test Circuit & Waveforms

RL
t on t off
Vout tf
td(on) tr td(off)
Vin VDD
( 0.5 rated VDS ) Vin
10%
RG
DUT

-10V
90%
Vout

Fig 14. Unclamped Inductive Switching Test Circuit & Waveforms

BVDSS
LL 1
EAS = ---- LL IAS2 --------------------
VDS 2 BVDSS -- VDD
Vary tp to obtain ID tp Time
required peak ID
VDD VDS (t)
RG C VDD ID (t)
DUT
-10V IAS
tp BVDSS
 P-CHANNEL
SFS9634 POWER MOSFET

Fig 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms

VDS
DUT
--

IS
L

Driver
VGS
Compliment of DUT
RG
(N-Channel) VDD

VGS • dv/dt controlled by “RG”

• IS controlled by Duty Factor “D”

Gate Pulse Width

VGS D = --------------------------
Gate Pulse Period 10V
( Driver )

Body Diode Reverse Current

IRM
IS
( DUT )
di/dt

IFM , Body Diode Forward Current

Vf
VDS
( DUT )
Body Diode VDD
Forward Voltage Drop

Body Diode Recovery dv/dt

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