Anshul Singh

129, Old Boys Hostel,

International Institute of Information Technology-Hyderabad,
Gachibowli, Hyderabad-500032, Andhra Pradesh, INDIA

Date of Birth: 24th August, 1987

Email: anshul.singh@research.iiit.ac.in, an2sh4ul8@gmail.com Phone No. 9160540204

Objective
To seek a challenging career in an organization that offers ample opportunities for me to continue the
learning process.

Education

• Master of Science by Research in Electronics and Communication Engineering

International Institute of Information Technology-Hyderabad
Major: VLSI
Advisor: Prof. Satyam M, Prof. Vincent J. Mooney III
Expected: July 2011
• Bachelor of Technology
Electronics and Communication Engineering
International Institute of Information Technology-Hyderabad
CGPA: 9.19/10
• Senior Secondary
Kendriya Vidyalaya, Rajahmundry
CBSE Board with 88.2%
• Secondary
Kendriya Vidyalaya, Rajahmundry
CBSE Board with 92.2%

Interests

• VLSI Design
• Probabilistic CMOS Technology
• Computer Arithmetic
• Computer Architecture

Academic Achievements
• Topper of ECE/D batch of 2006.
• Part of Dean’s Merit list for all the 8 semesters of under-graduation.
• Received merit certificate for being among top 0.1% students in Science in AISSE -2003.
• Secured All India Rank 1841 in AIEEE-2006.
• Secured All India Rank 3551 in IIT-JEE 2006.
Work Experience

• Research Assistant at NTU-RICE Institute for Sustainable and Applied Infodynamics (ISAID),
Nanyang Technological University (NTU), Singapore, under Prof. Vincent J. Mooney III and Prof.
Ling Keck Voon, June – Dec 2010.
• Research Intern at Institute for Sustainable Nanoelectronics (ISNE), NTU, Singapore, under Prof.
Vincent J. Mooney III and Prof. Ling Keck Voon, summer 2009.
• Teaching Assistant for Basic Electronic Circuits under Prof. R.N. Biswas, spring 2009 and Prof.
Govindrajulu, spring 2010.
• Teaching Assistant for Digital Logic Processors under Prof. R.N. Biswas, monsoon 2008.
• Research Intern at Centre for VLSI and Embedded System Technology, IIIT-Hyderabad, under Prof.
M. B. Srinivas, summer 2008.

Skill Set

• Programming : C, Matlab
• Operating Systems : Linux, Windows
• HDLs : Verilog, VHDL
• Assembly Languages : SPIM, NASM, 8085, 8086
• Tools : Synopsys Design Compiler, HSPICE, ModelSim, MultiSim, MAGIC, Quartus
• Scripting : Shell Scripting (basic), Perl (basic)

Relevant Coursework
Digital Logic Design, Design for Testability, Digital Design with HDLs, Digital System Design, VLSI Design,
Computer Organization, Modern Computer Architecture, Microprocessor Based System Design, Analog
and Digital Circuits, Electronics Workshop(I and II), Digital Signal Processing, Linear Control Systems,
Signals and Systems, Analog and Digital Communication, C Programming, Data Structures

Major Projects

• Modeling of Noise Based Probabilistic CMOS Circuits

(Project for Master’s Thesis (ongoing), Guide: Prof. Satyam M, Prof. V.J. Mooney, Prof. K.V. Ling)
Quick and accurate error-rate prediction of probabilistic CMOS (PCMOS) circuits is essential for
systematic design and performance evaluation of probabilistic circuits. The aim of the project is to
come up with models of noise based probabilistic circuits which could provide quick and accurate
insights to the error-rates of a noisy circuit.

• Decimal VLSI Arithmetic

(Honors Project-I, Guide: Prof. M.B. Srinivas, Team Size-2)
This project involved study of various unified decimal and binary adders. We came up with a novel
high speed unified BCD and Binary adder/subtractor and wrote a research paper which got accepted
in ISVLSI ’09.
• Design and Implementation of a General Purpose Three Staged Pipelined Processor
(Course Project, Guide: Ipshita Chakrabarty, Team Size-4)
The aim of the project was to design and implement a processor in Verilog HDL and synthesize it on
Synopsys tool. We designed a 32-bit general purpose three-stage pipelined RISC processor, along
with its instruction set architecture, and implemented it in Verilog HDL and synthesized it using
Synopsys's Design Compiler. The designed processor was then tested in Altera’s Cyclone II FPGA.

• Probabilistic Arithmetic with Future Noisy VLSI circuits

(Summer Internship ’09, Guide: Prof. Vincent J Mooney III, Prof. Ling Keck Voon, Team Size-1)
The project aimed at determining the effect of device noise on VLSI arithmetic circuits like ripple
carry, carry skip and carry select adder, array and Wallace tree multipliers. Noise filtering capability
of gates was observed and new precise models of noise based CMOS errors were developed for
ripple carry adder.

• Probabilistic CMOS Design and Sleepy Stack

(Honors Project-II, Guide: Prof. Satyam M, Prof. Vincent J Mooney III, Team Size-2)
This project involved study of newly conceptualized Probabilistic CMOS (PCMOS) Design for
implementation of very low power devices. PCMOS uses noise inherent in the circuits to provide
very low power computation with slight errors and has huge application where slight errors in the
computation can be tolerated. Sleepy Stack is also one of the new concepts which provide a new
approach to low power VLSI logic and memory design. In this approach the two previously well
known techniques, Sleepy Transistors and Stacking, used for reducing the power consumption have
been combined to provide ultra low power logic and memory designs.

• Mobile Interfaced Multi-agents

(Course Project and later extended to Summer Project, Guide: Prof. Bipin Indurkhya, Prof. Kamal
Karlapalem, Team Size-3)
We came up with a design to use a mobile phone as an embedded system and use it in controlling
agents. This non autonomous robot had Bluetooth interfacing and DTMF based mobile
communication. The robot had the ability to video stream around 30 meters through Bluetooth to
our laptop. The agents could be controlled using any mobile phone as the standard DTMF tones of
the phone were used to communicate. The main feature of the robot was its long range of
controllability.

Research Work
• Arun Bhanu, Mark S. K. Lau, Keck-Voon Ling, Vincent J. Mooney III and Anshul Singh, "A More
Precise Model of Noise Based CMOS Errors", DELTA 2010, Ho Chi Minh City, January 13-15, 2010.
• Anshul Singh, Aman Gupta, Sreehari Veeramachaneni, M.B. Srinivas, "A High Performance Unified
BCD and Binary Adder/ Subtractor," isvlsi, pp.211-216, 2009 IEEE Computer Society Annual
Symposium on VLSI, 2009.
• Jairaj Bhattacharya, Aman Gupta, Anshul Singh " A High Performance Binary to BCD Converter
for Decimal Multiplication" VLSI-DAT 2010, Hsinchu, Taiwan, April 26-29,2010.
Extra Curricular Activities

• Bharat Scouts and Guides Rajya Puraskar holder.

• Represented IIIT-H in All India South Zone Inter University Table Tennis Tournament (Dec 2007)
• Member of IIIT-H’s Table Tennis team
• Organizer of Robocamp '08, a National level Robotics workshop which is conducted in different
colleges across South India.
• Member of Technical Committee for IIIT-H’s annual techno-cult festival FELICITY ’09.

End of Curriculum Vitae’