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Virtual Circuit
D C1 D
D2
Mi: ith datagram sent
by Host M. All packets of the same virtual circuit
Two packets of the same user pair can travel along the same path.
travel along different routes. Packet sequencing is guaranteed.
The packets can arrive out of sequence. Packets contain short VC Id. (VCI).
Packets contain full Src, Dst addresses. Each VC occupies routing table entries.
Each host occupies routine table entries. Requires VC setup. First packet has
Requires no connection setup. large delay.
chow CS522 F96-Routing-12/3/96–Page 1-
Virtual Circuit and Datagram Implementation
Internal Operation
Datagram Victual Circuit
Datagram UDP over IP IP over ATM
(packet)
External Service Virtual Circuit TCP over IP TYMNET, SNA over ATM
(message, packet) (Virtual and explicit route)
4 4
3 5 3 5
6 Destination 6 Destination
All links have C=10 pkts/s. All links have C=10 pkts/s.
Traffic can be accommodated by multi-path routing.
If all traffic is via (4,6), congestion occurs.
What is the max. throughput from nodes 1and 2 to 6?
Via (1,3,6) and (2,5,6), the delay is small.
How about the worst case?
chow CS522 F96-Routing-12/3/96–Page 3-
Classification of Routing Algorithms
A’ B’ C’
chow CS522 F96-Routing-12/3/96–Page 4-
(Routing) Optimal Principle
Rejected Load
Routing determines the delay/throughput curve along which flow control operates
pkts delivered Delay
Max. capacity Poor Routing
flow control d X X X: flow control
invoked point
without flow control
congested Good Routing