J. S. S.

ACADEMY OF TECHNICAL EDUCATION, MAURITIUS

B. E: FEB 2011- MAY 2011-EVEN SEMESTER

LESSON PLAN

Name of the faculty : Mr. Chiniah Aatish No. of Students: 8

Semester/Branch : B.E –VIII SEMESTER

Subject/Subject Code : ACA - Advanced Computer Architecture

Holidays Planned Topics Covered Actual Date of No. of Executed Remarks

Date Completion Classes Date

Unit 1:

5th FUNDAMENTALS 1 hour

February OF COMPUTER
DESIGN:
Introduction;
Classes of
computers;

12th FUNDAMENTALS 1 hour

February OF COMPUTER
DESIGN: Defining
computer
architecture; Trends
in Technology
19th FUNDAMENTALS 1 hour
February OF COMPUTER
DESIGN: Power in
Integrated Circuits and
cost; Dependability

26th FUNDAMENTALS 1 hour

February OF COMPUTER
DESIGN:
Measuring,
reporting and
summarizing
Performance;

5th March FUNDAMENTALS 1 hour

OF COMPUTER
DESIGN:
Quantitative
Principles of
computer design

Unit 2: 3 Hours

PIPELINING:
Introduction;
Pipeline hazards;
Implementation of
pipeline;
PIPELINING: What 3 Hours
makes pipelining
hard to implement?

Unit 3: 3 hours
INSTRUCTION –
LEVEL
PARALLELISM – 1:
ILP: Concepts and
challenges; Basic
Compiler
Techniques for
exposing ILP;

Reducing Branch 4 hours

costs with
prediction;
Overcoming Data
hazards with
Dynamic
scheduling;
Hardware-based
speculation.

Unit 4: 3 hours
INSTRUCTION –
LEVEL
PARALLELISM – 2:
Exploiting ILP using
multiple issue and
static scheduling;
Exploiting ILP using
dynamic scheduling,
multiple issue and
speculation;

Advanced 4 hours
Techniques for
instruction delivery
and Speculation;
The Intel Pentium 4
as example.

Unit 5: 3 hours
MULTIPROCESSOR
S AND THREAD –
LEVEL
PARALLELISM:
Introduction;
Symmetric shared-
memory
architectures;
Performance of
symmetric shared–
memory
multiprocessors;

Distributed shared 4 hours

memory and
directory-based
coherence; Basics
of synchronization;
Models of Memory
Consistency.
Unit 6: REVIEW OF 3 hours
MEMORY
HIERARCHY:
Introduction; Cache
performance;

Cache 3 hours
Optimizations,
Virtual memory.

Unit 7: MEMORY 3 hours

HIERARCHY
DESIGN:
Introduction;
Advanced
optimizations of
Cache performance;

Memory technology 3 Hours

and optimizations;
Protection: Virtual
memory and virtual
machines.

Unit 8: HARDWARE 3 hours

AND SOFTWARE
FOR VLIW AND
EPIC: Introduction:
Exploiting
Instruction – Level
Parallelism
 Statically; Detecting
and Enhancing
Loop-Level
Parallelism;
Scheduling and
structuring code for
parallelism;
Hardware support
for exposing
parallelism;

Scheduling and 4 hours

structuring code for
parallelism:
Hardware support
for exposing
parallelism;
Predicated
instructions;
Hardware support
for compiler
speculation; The
Intel IA-64
Architecture and
Itanium Processor;
Conclusions.

Revision 2 hours

IA Test Date:
Test No. Date

1 14th,15th,16th March 2011

2 21st, 22nd,23rd April 2011

3 19th,20th,21st May 2011

Total Number of Teaching Hours:

Total Number of teaching hours as per VTU Schedule: 52

Total Number of teaching hours as per Lesson Plan : 54

Text Books:

1. Structured Computer Organization (5th Edition) Andrew S. Tanenbaum. ISBN-13: 978-0131485211

2. Computer System Architecture (3rd Edition) M. Morris Mano. ISBN-13: 978-0131755635

Reference Books:

1. Computer Architecture: A Quantitative Approach, 4th Edition by John L. Hennessy and David A. Patterson

2. The Essentials of Computer Organization And Architecture by Linda Null

3. Computer Organization and Architecture: Designing for Performance (8th Edition) by William Stallings
Signature of the faculty Signature of the HOD Signature of the Principal