Vous êtes sur la page 1sur 2

Vidyalankar

Time : 3 Hrs.]

S.E. Sem. III [CMPN]

Digital Logic Design and Application

Prelim Question Paper

[Marks : 100

Design and Application Prelim Question Paper [Marks : 100 N.B. : (1) Question no. 1 is

N.B. :

(1)

Question no. 1 is compulsory. Answer any four out of remaining six questions. Figures to the right indicate full marks.

 

(2)

(3)

1. Convert the following numbers to the given base:

(a)

(i)

(357.46) 8 = (?) H

 

(ii)

(656.25) 8 = (?) 6

(iii)

(123) 4 = (?) 2

(iv)

(11011.101) 2 = (?) 10

(b)

Implement the following Boolean function using 4: 1 MUX.

 

f (A, B, C, D) = m (0, 1, 2, 4, 6, 9, 12, 14)

(c)

Prove:

(i)

AB AB (A B) (AB)

 

(ii)

A(B C) AB BC A(B C) B(AC 1) C

(d)

Design full adder using half adders.

 

2. (i) A panel light in the control room at the launching of a satellite is to go ON if an only if the pressure in both fuel and oxidiser tanks is equal to or above a required minimum and there are 10 minutes or less to lift off or if the pressure in the oxidiser tank is equal to or above a required minimum and pressure in fuel tank is below a required minimum but there are more than 10 minutes to lift off or if the pressure in the oxidiser tank is below a required minimum but there are more than 10 minutes to lift off. Design a two level combinational circuit to control panel light.

(a)

(ii)

Explain the following terms :

 

(1)

Prime Implicant

 

(2)

Input variable

(3)

Min. term

(4) Max term

(b)

Simplify the function using Quine McClusky method,

f (A, B, C, D) = m (4, 5, 8, 9, 11, 12, 13, 15). Draw the logical diagram using NAND gates.

(a)

3. Given the logic expression: A BC ABD ABCD . (i) Express it in standard SOP form.

(ii)

Draw K-map and simplify.

 

(iii)

Draw logic diagram using NOR gates only.

 

(iv)

Draw logic diagram using NAND gates only.

(v)

Express it in standard POS form.

 

(b)

Design a clocked sequential R.S. Flip-flop. What is race around condition? Is it in R.S.

Flip-flop? How is it avoided in J-K Flip-Flop?

 

(c)

Draw truth table, function table and excitation table of J-K Flip-flop.

4. Explain the working of a Parallel In Serial Out Registers using D-flip-flops.

(a)

(b)

Differentiate between :

 

(i)

Synchronous and Asynchronous counters.

 

(ii)

Combinational and Logic Circuits.

 

(c)

Explain the lockout condition in counters with examples and how it can be avoided.

(d)

Simplify using K-map:

 

f (A, B, C) = m (0, 2, 5, 7)

[6]

[4]

[4]

[4]

[6]

[4]

[10]

[10]

[8]

[2]

[6]

[4]

[4]

[4]

[2]

(2) Vidyalankar : S.E. DLDA

5. Explain in brief with neat sketches:

(a)

[8]

(i)

Fan-out

(ii)

Current and voltage parameters w.r.t. to input and output of digital ICs.

 

(iii)

Propagation delays

(iv)

Noise Immunity

(b)

Write short notes on Interfacing of TTL and CMOS logic families.

[6]

(c)

Explain the Power ON RESET circuit for a counter.

[3]

(d)

Encode the data into even parity Hamming Code.

[3]

(i) (1101) 2

(ii) (1001) 2

6. What is race condition ? How it is overcome in Master-slave J-K flip flop ? Explain. [10]

(a)

(b)

State truth table of 3-bit gray to binary conversion and design using 3 : 8 decoder and additional gates.

[10]

7. Write short notes on :

 

[20]

(a)

Multiplexer and demultiplexer

(b)

ALU

(c)

Asynchronous vs synchronous counter

 

(d)

Octal to binary encoder

 

