SystemVerilog Q&A

1. What's difference between static and automatic task/program?

If you use static task for multiple places in your testbench, the local variables will
share the common, static storage. In this case, different threads will step on each other's
values.
By using atuotmic storage, it will make a copy of local variables and use them. Not a
common static storage any more.

e.g. program automatic initialization;

......
endprogram

2. What's the packed array and unpacked array?

unpacked array is an array with gap between variables.

e.g. bit[7:0] b_unpack[3]; // unpacked

Te system verilog simulators store each element on a 32-bit word boundary. In
other words, you are using only lower 8 bits, the other 24 bits per word space is wasted.

Packed array is an array without gap. Unpacked array is good for local individual
variable access.

e.g. bit[3:0] [7:0] bytes; // 4 bytes packed into 32 bits

In this case, all 32 bits word are packed with 4 bytes. A packed array is handy if you
need to convert to and from scalars.

3. What's different between logic and wire?

Logic and wire are almost the same except wire can be driven by multiple sources.
Logic can only driven by single source.

Systemverilog Assertion (SVA) 2

Working Assertion Examples:

Normal inline assertion example:

assertStateStartShortFalse:
assert property (@(posedge clk) disable iff(!reset_n)
(state==`START) |-> (short==FALSE))
 else $display("Error state START and short is true ");

Normal Assertion compile with VCS with +assert option

// Assertion example for parity checking
module check_par(clk, parity, data);
input clk, parity;
input [31:0] data;

property p_check_par;
@(posedge clk) (^(data^parity)) == 1’b0;
endproperty
a_check_par: assert property(p_check_par);
endmodule

binddata_bus check_par u1(clk, parity, data);

bindtop.mid.u1 check_par u2(clk, parity, data);

For OVL, use +define+OVL_ASSERT_ON for OVL.

ovl_even_parity

[#(severity_level, width, property_type, msg, coverage_level,

clock_edge, reset_polarity, gating_type)]

instance_name (clock, reset, enable, test_expr, fire);

ovl_even_parity top.u1(clk, reset, 1, (^(data^parity)));

Posted by Roy Chan at 8:01 AM 0 comments

Labels: SVA

SVA ( System verilog Assertion)

1. What are difference between SVA and other assertions?

Answer: Systemverilog Assertions (SVA) are temporal, Declarative and formal friendly.
Temporal : Design Variables relationship in time
Declarative: Orthogonal to procedural form in design (describe what instead of
how )
Synthesizable: Good for dynamic and formal verification.
SVA provides interoperability with RTL, testbench features and functional
coverage.
2. What are the benefits of using assertions?

Answer: 1) Improve error detection

2) Better observability
3) Shortens debug time

3. Who writes Assertions?

Answer: White box (Designers) , Black box (DV)

4. How many ways to connect assertion to RTL?

Answer: There are 3 ways to connect assertion to RTL: inline, Instantiation and Virtual
Instantiation (bind).

Inline Assertion: Assertion directly put into the RTL by designer. Use compile
option for synthesis.

For example:
// A synchronous D Flip-Flop
moduledff (input logic [7:0] D, input RST_, input CLK, output logic [7:0] Q);
always @(posedge CLK)
if (!RST_) Q<= 8'h0;
else Q <= D;

// assertions
propertyd_q_property_0 (clk, rst_, q);
@(posedge clk) !rst_ |->##1(q == 8'h0);
endproperty
assert_d_q_property_0 : assert property(d_q_property_0(CLK, RST_, Q));

endmodule

Assertion Instantiation: Put assertion into another module and use it again by RTL
designers.

For example:

moduledff (input logic [7:0] D, input RST_, input CLK, output logic [7:0] Q);
always @(posedge CLK)
if (!RST_) Q<= 8'h0;
else Q <= D;

// Use assertion module here

dffChecker #(8) Chk0(CLK, RST_, D, Q);

endmodule
moduledffChecker (clk, rst_, d, q);
parameter WIDTH = 8;
input clk, rst_;
input [WIDTH-1:0] d, q;
propertyd_q_property_0;
@(posedge clk) !rst_ |->##1 (q == 8'h0);
endproperty
assert_d_q_property_0 : assert property(d_q_property_0);
endmodule

Virtual Instantiation (bind): Use bind method to connection both modules together. It's a
saftest method for DV because it did not change RTLs. Plus we can use OVL for most of
common checkers.

For examples:
binddff dffChecker #(8) Chk0(CLK, RST_, D, Q);

SystemVerilog Interview Questions

1. How many array types in SystemVerilog? How do you use them?

array_name[ ] dynamic array

e.g . dyna_arr_1 = new[100] (dyna_arr_1);

dyna_arr_2 = new[4]('{4,5,6}); // elements are {4,5,6,0}

array [5] fixed array

e.g. register1 [6][7:0] = `1;

array[$] queue
e.g. int q[$] = { 2, 4, 8 };
q = {}; // clear the queue (delete all items)
e = q[0]; // read the first (leftmost) item
e = q[$]; // read the last (rightmost) item

array[string] or array[%] associate array

e.g. //associative array of 4-state integers indexed by strings, default is '1.
integer tab [string] = '{"Peter":20, "Paul":22, "Mary":23, default:-1 };

2) What is the Polymorphism?

Polymorphism allows an entity to take a variety of representations. Polymorphism

means the ability to request that the same Operations be performed by a wide range of
different types of things. Effectively, this means that you can ask many different objects
to perform the same action. Override polymorphism is an override of existing code.
Subclasses of existing classes are given a "replacement method" for methods in the
superclass. Superclass objects may also use the replacement methods when dealing with
objects of the subtype. The replacement method that a subclass provides has exactly the
same signature as the original method in the superclass.

EXAMPLE: with virtual

class A ;
virtual task disp ();
$display(" This is class A ");
endtask
endclass

class EA extends A ;
task disp ();
$display(" This is Extended class A ");
endtask
endclass

program main ;
EA my_ea;
A my_a;

initial
begin
my_a = new();
my_a.disp();

my_ea = new();
my_a = my_ea;
my_a.disp();
end
endprogram

RESULTS

This is class A
This is Extended class A

3) how the copy works?

Answers:
There are 2 types of copy. Show copy or deep copy
 For example:

class B;
int
endclass

program main;
initial
begin
B b1;
B b2;
b1 = new();
b1.i = 123;
b2 = b1; // b1 and b2 point to the same memory. The properties did
not get copied.
$display( b2.i );
end
endprogram
RESULTS:

123

A shallow copy of an object copies all of the member field values.

program main;
initial
begin
B b1;
B b2;
b1 = new();
b1.i = 123;
b2 = new b1; // shallow copy of b1
b2.i = 321;
$display( b1.i );
$display( b2.i );
end
endprogram

RESULTS:

123
321
If the value of b1 change, it will also change the value of b1. It's because it's pointing to
the same memory.

To avoid this, we need to use the deep copy.

Deep Copy

A deep copy copies all fields, and makes copies of dynamically allocated memory
pointed to by the fields. To make a deep copy, you must write a copy constructor and
overload the assignment operator, otherwise the copy will point to the original, with
disasterous consequences.

EXAMPLE:
class A;
int i;
endclass

class B;
A a;

task copy(A a);

this.a = new a;
endtask

endclass

program main;
initial
begin
B b1;
B b2;
b1 = new();
b1.a = new();
b1.a.i = 123;
b2 = new b1;
b2.copy(b1.a);
$display( b1.a.i );
$display( b2.a.i );
b1.a.i = 321;
$display( b1.a.i );
$display( b2.a.i );
 end
endprogram

RESULTS:

123
123
321
123

1) There is a waveform

in _____|====|________
out_____|=|___|=|______

The output is "high" when the input change the value.

Verilog code

always@(posedge clk or reset)

begin
if(!reset)
begin
in_reg <= 1'b0; // initial value
out <= 1'b0;
end
else
begin
if(in != in_reg)
begin
out <= 1'b1;
in_reg <= in;
end
else
out <= 1'b0;
end
end

After synthesis, what will it be look like?

It's like a D-FF and a XOR

in -----D_FF------in_reg---|XOR| ___ out

|__________________| |
2) How to write a C or C++ code for Strlen

Answer:

int strlen (char *s)

begin
for (int len =0; *s='\0'; s++)
len++;
return (len);
end

Use recurve way

int strlen_r (char *s)

begin
if(*s='\0') return 0;
else return (1 + strlen_r(s+1));
end

C++ basic interview questions

1) How do you swap two integers? Without another variable?

Answer:

example main.cpp

void main()
{
int a=2, b=3;
swap (a, b);
}

swap ( int &a, int &b) // pass by reference

{
int tmp = a;
a = b;
b = tmp;
}

Without a third variable

swap ( int &a, int &b)
{
a = a +b; // a = 2 +3 =5
b = a-b; // b = 5-3 =2
a = a -b; // a = 5 - 2 = 3, a and b swap
}

template < class T>

void swap ( T &a, T &b)
{
T tmp =a;
a = b;
b = tmp;
}
use swap (a, b ) to call the swap. It can swap any data type.