R F

2008 IEEE INTERNATIONAL RF AND MICROWAVE CONFERENCE December 2-

2-4, 2008, Kuala Lumpur, MALAYSIA
M 08

Characterisations of Electromagnetic Emission of a High-Speed Digital

Circuit

Saizalmursidi Md Mustam and Mohd Zarar Mohd Jenu

Center for Electromagnetic Compatibility,
Faculty of Electrical and Electronic Engineering,
Universiti Tun Hussein Onn Malaysia,
86400 Parit Raja, Batu Pahat, Johor, Malaysia.
saizal@uthm.edu.my, zarar@uthm.edu.my.

Abstract - Controlling electromagnetic emissions level
of high-speed digital circuit has become utmost
important to ensure a proper operation and
performance of electronic devices as well as
electromagnetic compatibility (EMC) compliance. The
increasing clock frequency of the digital circuits has
created more challenges to the circuit designers in
producing a system that is complying with regulation
since its harmonic frequencies can contribute
significant amount of electromagnetic emission. The
paper will highlight the most effective technique to
ensure proper mitigation approach to achieve EMC
requirement. The measurements were conducted in
Gigahertz Transverse Electromagnetic (GTEM) cell. It
is interesting to indicate that, different method of
emission reduction is only effective at certain range of
frequency.
Keywords: Electromagnetic Compatibility (EMC),
Electromagnetic Emission, High-Speed Digital Circuit,
Emission Reduction.
that the DM radiation is characterised by currents
flowing on closed loops (power or signal and return
path loop) that behave like transmitting antenna, while
CM radiation is caused by ground-noise voltage or
voltage drops which results in CM current flowing in
interfacing cable [1].
Basically, the maximum emission of radiated
fields, | Eˆ D , max | and | Eˆ C , max | that are broadside on the
wires and Printed-Circuit Board (PCB) lands due to
DM current and CM current respectively can be
estimated by using the formula as given below [1];
| Iˆ D | f 2 A
| Eˆ D , max |= 1.316 × 10 −14 [V/m] (1)
d
where
| IˆD | is DM current in Ampere,
f is frequency in Hertz,
A is the loop area in m2,
d is the distance of observation point in m
which is fixed by the related standard.

1. Introduction
Nowadays, the revolution of analogue to digital
signal processing for high speed operation purpose has
leads in controlling and operating an electrical and
electronic device digitally. Electrical and electronic
equipments on the market today’s use a printed circuit
board carrying high speed digital circuit driven by a
repetitive signal such as trapezoidal or square wave
shapes which have high number of harmonics
frequency. At the highest frequencies, harmonic
components of clock signal become the significant
source of Electromagnetic Interference (EMI)
problem. With the trend of frequency getting higher in
order to satisfy the need of higher performance and
high speed system, the EMI problem becomes a
challenge to the circuit designer to implement the
proper suppression techniques.
Many works have been done on the suppression
methods of electromagnetic emission of high speed
digital circuit due to differential-mode (DM) radiation
and common-mode (CM) radiation. It is well know
| Iˆ | fL
| Eˆ C , max |= 1.257 ×10 − 6 C [V/m] (2)
d
where
| IˆC | is CM current in Ampere,
f is frequency in Hertz,
L is the line length in m,
d is the distance of observation point in m
which is fixed by the related standard.
Based on equations (1) and (2), it can be observed that
by reducing the levels of DM current and the loop area
as well as the CM current and the line length, the
reduction of radiated emissions at a specific frequency
can be achieved.
Numerous approaches have been reported in the
literature [2]-[6] related to radiated emission from
PCB. In [2], it has been proven experimentally that the
poor PCB layout design is fail to meet EMC
compliance. Therefore, controlling both DM and CM
radiations from a digital circuit is the best way in

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minimizing electromagnetic emissions from the PCB. fabricated as shown in Figure 2 consisting of a single-
A digital circuit with high ground bounce indicates layer double-sided board with the power and signal
large circuit loop which lead to high DM radiation and traces dedicated at the top side and ground trace at the
also CM radiation through interfacing cable [3]. bottom side of the board. The power and signal traces
However, in [4] the authors reported that a lower load are kept fixed in order to examine the influence of
termination results on higher ground bounce. Reducing return current path layout on electromagnetic
the loop size is basically the option for the circuit emissions level. The circuit was fabricated on FR4
designer to reduce the level of emission. For example, board with relative permittivity 4.7, thickness 1.6mm
it can be done by applying decoupling capacitor [5]-[8] and the power/signal and ground traces width is set to
and the use of ground plane as return current path [7]-
be 0.08mm.
[9]. It is of utmost importance to ensure that a low
impedance path is provided with a lowest loop area.
Typically, for ground plane at low frequency, the
impedance of Printed-Circuit Board (PCB) trace is
dominated by resistance. While at high frequency, the
impedance is dominated by inductance [7].
In this paper, different designs of return path for Power Trace
high-speed digital circuit are studied. This includes a
ground trace closely following the power or signal
trace at the bottom side (layout-A), ground trace at the
opposite side of power or signal trace (layout-B) and
the use of perfect ground plane (layout-C). The Signal Trace
radiated emissions are examined by experimental
measurement using GTEM cell.

(a) Power and signal traces of layout-A.

2. PCB Layout and Experiment

In the effort to investigate the electromagnetic

emission of high speed digital circuit, a worst digital
circuit layout as shown in Figure 1 has been designed
and the GTEM cell 750 with EMI receiver model
SCR3012 have been utilized for radiated emission
measurement.

osc
inveter
JK-ff

(b) Ground trace of layout-A.

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Figure 1: High-speed digital circuit under Study.

In this paper, electromagnetic emission from high-

speed digital circuit proposed by See et al. [2], [3] with
three different return path layouts was investigated and (c) Power and signal traces of layout-B.
compared. A 9 V battery was used as a supply voltage
to operate the circuit driven by 25MHz clock square
wave signal. All these three PCB layouts were

330

(d) Ground trace of layout-B.
(e) Power and signal traces of layout-C.
(f) Ground plane of layout-C.
Figure 2: Three PCB layouts (A, B and C) of power and
signal traces with different return current paths.
Based on Figure 2, (a) and (b) illustrate the
layout-A’s PCB where its return path current at the
opposite sides of board and its follow all the power
and signal traces in order to reduce the loop areas.
Layout-B as can be seen in (c) and (d) has the return
current on opposite side of power and signal trace
which results in large power and signal loops. (d) and
(e) show the layout-C where return current is on a
ground plane.
Figure 3 (a), (b) and (c) show the position of the
high-speed digital circuit under study inside the GTEM
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cell which is represented in the x, y, and z orientations
respectively.
(a) High-speed digital circuit located at X orientation.
(b) High-speed digital circuit located at Y orientation.
(c) High-speed digital circuit located at Z orientation.
Figure 3: PCB orientations inside the GTEM cell.
3. Results and Discussions
In this section, the electromagnetic emission of
high-speed circuit board in the aspect of different
ground traces are presented and discussed. We are only
interested in investigating the emission due to signal to
ground trace. The power to ground trace is assumed
has no contribution in the emission level since the
circuit is powered by battery. The results of radiated
emission from the three different PCB layouts are
measured inside the GTEM cell at distance of 0.43m
from septum. The electric field strength of 25 MHz
clock signal and its harmonic frequencies radiated
compared with EN55022 standard limit line is shown
in Figure 4 – Figure 6.

Figure 4: Layout-A’s radiated emission level.
Figure 5: Layout-B’s radiated emission level.
Figure 6: Layout-C’s radiated emission level.
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Comparisons of these figures show that circuit
design with ground plane (layout-C as shown in Figure
6) provides the best practice on reduction of
electromagnetic emission. This means that a ground
plane can provides lower ground impedance.
Theoretically, the return current will follow the path of
least inductance during high frequency operation [7].
The existence of the ground plane provides smallest
loop area and hence it reduces the emission level of the
circuit. However in Figure 4 and Figure 5, it can be
seen clearly that, both measurement results are
exceeding the EN55022 limit line at some frequencies.
Thus, both Layout-A and Layout-B have failed the
radiated emission testing and do not comply with
EN55022 class B regulation.
Observation of Figure 4 and Figure 5 shows that
layout-B is better than layout-A in reducing the
emission level from the circuit. Based on the design in
layout-A, the ground tracks are traced parallel on the
opposite side of the board below the signal trace. This
greatly reduces the loop area of the return path
compared with layout-B. Basically, the parallel PCB
traces have radiated emission due to DM currents and
CM currents. We must provide lower impedance path
to ensure only DM currents exist so that emission level
can be reduced. Since the DM currents are oppositely
directed, the radiated electric field will be cancelled
out and this results a small level of radiation. However,
CM currents are directed in the same direction, so it
will contribute higher radiation than DM currents.
Based on Figure 4, there is higher emission in
between 275 MHz to 500 MHz and 600MHz to
850MHz. It is believed to be related with the
impedance of the return ground trace of both layouts.
Since layout A has smaller loop area compared with
layout-B, it produces lower resistance and higher
current distribution. Based on equation (2), as the
current distribution increases, the radiated emission
will also increases. This shows the reason why the
emission of layout-A is higher than layout-B.
4. Conclusion
In this paper, we presented the work related to the
electromagnetic emission of high-speed digital circuit
with different configurations of return current path.
According to the results obtained from experimental
measurement inside GTEM cell, it was found out that,
the use of ground plane has significant effect in
reduction of emission level because it offers the return
current path at any track above it.
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