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un 1
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Introduction ............................................................................................................ 11
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1.1 Supported d
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un
1.1.1ed Operating System Support ...................................................................... 13nd
1.2 f
Power e d
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13
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d 1.2.1 Processor Core Power Management........................................................... e d
n de
un 1.2.2 System Power Management ..................................................................... e fin 13 14
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1.2.3 Memory Controller PowerdManagement...................................................... u n d 14
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d ef 1.2.4 Processor Graphics Power
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n 1.2.4.1 Memory e
Power Savings Technologies i n
........................................... 14
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u 1.2.4.2 Display u d ef
ndPower Savings Technologies ............................................ 14
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Graphics Core Power Savings n
Technologies................................... 14
efi 1.3 Thermal Managementi n
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d f e
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1.5 n d e
ProcessoruTestability .......................................................................................... 15 f in
1.6 Terminology un
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1.7
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u
d f in e
2 un de
Interfaces................................................................................................................
n e fin 19
d u
e2.1 System Memory Interface .................................................................................. d 19
f in 2.1.1 System Memory Technology e un
d Supported ..................................................... 19
d e 2.1.1.1 DDR3L/-RS f in
Supported Memory Modules and Devices e d
..................... 20
un 2.1.1.2 DDR4 Supported d e Memory Modules and f in
Devices............................. 21
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unTiming Support...............................................................
ed 2.1.2 System Memory
d nd 21
if n e u
d e 2.1.3
2.1.4
System
System
Memory
f in
Memory
Organization Modes.........................................................
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Frequency......................................................................
22
23
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un e i n e d
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2.1.5 Technology
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d ef Access............................. 24 f in
2.1.6 Data un
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n de
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2.1.7in DDR I/O Interleaving .............................................................................. 25 u
d ef Data Swapping ......................................................................................
2.1.8 f in e d
26
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un2.1.9 DRAM Clock Generation...........................................................................
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e d 2.1.10 DRAM Reference Voltage u
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......................................................... 26
d
if n2.2 PCI Express* Graphics Interfacen(PEG).................................................................
e un 26
de fi d
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2.2.1 PCI Express* Supporte.............................................................................
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2.2.2 PCI Express* Architecture n .......................................................................
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..................................................... 29
f in e d u
2.2.4 PCI Express* Equalization Methodology ..................................................... 29
n de 2.3 Direct Media Interfacee n ed
fin (DMI)............................................................................... 30 d
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2.3.2 DMI
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2.4 in Graphics ............................................................................................
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n de API Support (Windows*)


2.4.1 fin
.........................................................................
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31
u2.4.2 Media Support (Intel QuickSync ®
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e d 2.4.2.1 Hardware Accelerated unVideo Decode ............................................ n de 31
e fin 2.4.2.2 Hardware Accelerated
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....................................... 33
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Transcoding .............................................. 33
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un .............................................................................. 33
f in 2.4.4 Switchable/Hybrid e d Graphics u
..................................................................... 34
d e f n d
i Analytics.............................................................................
e u
2.4.5 GEN 9 Videoe n 34 d
un d f i e
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2.4.6 GEN 9n(Generation 9) Block Diagram ........................................................
uGraphics Frequency..........................................................................
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35
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f in 2.5.3 Digital Video e un
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2.5.6 d
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Multiple Display Configurations (Dual Channel u nd DDR) ....................................42 def
e Display Configurations (Single d DDR) ..................................43un
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d 2.5.10 Display Bit Per Pixel (BPP) Support............................................................44 n de
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....................................................45
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2.6.1 PECI Bus Architecture..............................................................................46
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fin 3 Technologies............................................................................................................48
n e d nd
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VT) e
..........................................................48 u
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3.1.1 Intel®dVirtualization Technology (Intel® VT) foreIA-32, f in Intel® 64 and Intel® ed
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in d u
3.2 Security
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3.2.1 Intel Trusted Execution Technology
un3.2.2 Intel® Advanced Encryption Standard n de (Intel TXT) .......................................53
New Instructions (Intel® AES-NI) .........54 e fin
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3.2.4 Intel Secure Key ...................................................................................54
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d e 3.2.8 Intel Supervisor f in Mode Access Protection (SMAP) .........................................55
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3.2.9 Intel® Memory
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Protection Extensions (Intel® MPX)......................................55
..........................................56 f in
ed ® Virtualization Technology (Intel® VT)
3.2.11 nIntel
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ufor Directed I/O (Intel® VT-d).....56 n de
i d u
3.3 Power
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Technologies ...................................................................57
e d
u3.3.1
n Intel Hyper-Threading Technologye(Intel HT Technology) .........................57 in
d nd
3.3.2 Intel® Turbo Boost Technologyu2.0............................................................57 d ef
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fin ne d
d e 3.3.3 Intel ®
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d ® un
d
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if n 3.3.6 Intel® Transactional
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d TSX-NI) ..................59
d e 3.4 Intel® Image Signalfi Processor (Intel® ISP) ...........................................................60
e u
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3.4.1 Platform Imaging Infrastructure................................................................60
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un ...........................................................................................61 e fin
3.5.1 Intel ed® Processor Trace ............................................................................61
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Power-Down................................................................
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4.3.3 e d 4.3.2.4
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........................................................... 77nd
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e i n d 77
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4.4 nd PCI Express* Power Management ........................................................................
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..................................................
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n de ..................... 78
fi n 4.6.2 Display Power d u
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d e 4.6.2.1 f i nIntel (Seamless & Static) Display Refreshe d Rate Switching (DRRS) u
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de with ®eDP* Port ......................................................................... 78 n ed
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4.6.2.2 Intel Automatic Display Brightness d ............................................ 78 f i
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d4.6.2.3 Smooth Brightness.................................................................... 78 nd
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in 4.6.2.4 Intel® Display Power Saving edTechnology (Intel® DPST) 6.0 ............d78u
d 4.6.2.5 Low-Power Single Pipe (LPSP) f in .................................................... e
un 4.6.3 Processor Graphics Core Power d e
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d un Frequency ............................................ d e
e 4.6.3.1 Intel® Graphics Dynamic n 79
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in 4.6.3.2 Intel® Graphics edRender Standby Technology (Intel® GRST) u
d ............ 79
d 4.6.3.3 Dynamic FPS f in(DFPS) e
................................................................. 79
un 4.7 d e f in
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e d un n de
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n e 81 d
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f i ne
5.1.2 Intel Turbo Boost Technology 2.0 Power Monitoring
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....................................... 82 n
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82
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...................................................... 84
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d e 5.2 S-Processor Line Thermal fi e
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......................................................................................... 112
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119 n de
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un Revision History
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e in
nd ef
ed d
u
un
d
de
if n ne
de fi ed un
un de fin ed
Revision un de fin
Number
e d Description
un
Revision Date
n de
001
fi n
• Initial release e d August 2015 u
n
•deUpdated datasheet title
e f in n ed
002 u
• Addition of the i3, i5, i7 processor information d f i
e d • Addition of Intel Pentium processor information
® ®
un n de 2015
October

e fin • Updated Section 5.2 “S-Processor Line Thermal


n ed and Power Specifications” d
u
i e
un
d • Updated Table 1-1, Processor
ef Group DC Specifications
Lines
in
d
003 • Updated Table 7-10, DDR3L/-RSdSignal
• Updated Table 7-12, DDR4/-RS u n Signal Group DC Specifications d ef October 2015
e d clarity n
efin • Minor Edits throughout e
i n
for
d
u
u nd
d • Removed references f to GT3, GT4, Vcc , ECC, and On-Package Cache e
throughout
fin Description” ed
GTX
un • Removed references
n de to DDR_RCOMP[2:0] signals from Chapter 6, “Signal e i n
u
• Table 1-1, “Processor Lines”. Updated table d f
• Sectione1.5,d “Processor Testability”. Updated Note un nde
ef
in 2.1, “System Memory Interface”. Updated bulletnfor
• Section edTheoretical maximum memory d
u
dbandwidth.
f i e
un•• Table 2-4, “Supported DDR4 Non-ECC UDIMM Module
n de Configurations”. Updated table
e fin
d Table 2-5, “Supported DDR4 Non-ECC SODIMM
e • Section 2.5, “Display Interfaces” Added Table u Module Configurations ”. Updated table d
fin e d 2-18, “Display Resolutions and Link Bandwidth un
n de for Multi-Stream Transport calculations”n
e fi ned
u • Section 2.5.7, “Multiple Display Configurations
d (Single Channel DDR)”. Added section.
f i
d • Section 2.5.8, “High-Bandwidthn
u Digital Content Protection (HDCP)”. Added Table 2-24, e“HDCP
if n
e Display supported Implications”.
d und
• Section 3.3.2.1, “Intel Turbo e Boost Technology 2.0 Frequency”. Updated section,
®
d added un
d e bullet. f in n e d
un • Section 3.3.3, “Intel
e
d Advanced Vector Extensions 2 (Intel AVX2)”. Updated
® ® fi section. e
d un“Processor IA core C-State Rules”. Updated sectionntoderemove references to f in
de
• Section 4..2.4,
d above C8.
Package C-State
e u n
n
i5-2, “TDP Specifications (S-Processor Line)”. Updated d
etable u
ef 5-3, “Low Power and TTV Specifications (S-Processor
• Table
004 May 2016 d
d
• Table f in Line)”. Updated table. e
u• nTable 6-2, “DDR3L/-RS Memory Interface ”. Updated n detable e fin
e d • Table 6-3, “DDR4 Memory Interface”. Updated table u d
fin • Table 6-14, “Processor Power Rails Signals”. e dUpdated table. un
e i n e d
d ef
• Table 7-2, “Processor IA core (Vcc) Active and Idle Mode DC Voltage and Current
un Specifications”. Updated table
d f in
n e
ed • Table 7-3, “Processor Graphics (VccGT and VccGT-X) Supply DC Voltage and Current d
Specifications”. Updated table
u
d (VDDQ) Supply DC Voltage and Current Specifications”. un
if n n e d
d e • Table 7-4, “Memory Controller
f i e u
u n Updated table
d e f i n e d
deSpecifications”. fin
• Table 7-7, “Vcc Sustain (VccST) Supply DC Voltage and Current Specifications”. Updated table
n
ed • Table 7-8, “VccuSustain Gated (VccSTG) Supply DC Voltage and Current n e
ed
Updated table u
d Specifications”. Updated un
d
in “Processor PLL (VccPLL) Supply DC Voltage and nCurrent
• Table f7-9, e
de
table
e fi and Current Specifications”. n ed
•un i
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d Updated table u nd
Voltage
d ef
e n
e fin •• Table 7-12, “DDR4 Signal Group DC Specification”.
ned Updated table d
u
d Table 7-5, “embedded DisplayPort* (eDP*)
f i Group DC Specifications”. Updated table
e
un 005 • Table 7-18, “PECI DC Electrical Limits”.eUpdated table. in
d • Added Chapter 9, Processor Land
u n d
Information d ef January 2017
e • Updated Table 2-14, VGA anddembedded DisplayPort* (eDP*) Bifurcation Summary“ un
f in n e d
n de 06 • Updated Table 2-15,
e fi Management“
“embedded DisplayPort* (eDP*)/DDI Ports Availability“
i ne August 2017
d
u
u • Updated Chapter 5, “Thermal
d f e
ed un n de e fin
e d u d
fin e d un
n de e fin ned
u d f i
d 1 of 2
Datasheet, Volume
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e d • Removed Section 2.4.1 "Operatingun Systems Support" nde e
f in 007
e d
• Added Section 1.1.1 "Operating Systems Support" u May 2018
nd
e i n e d u
un
d 008 ef "Operating Systems Support"
• Updated Section 1.1.1
d f in August 2018
ed
009 • Updated Chapter n 7, Electrical Specifications Section 7.1.2 VCC e
Voltage Identification (VID) July 2020 i n
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Throughout this document, the 6th Generation Intel
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n de fin ed
un de if n
ed un n de
Introduction fin ed u
de if n ed
un de fin
ed un n de
if n e d u
de1.1 Supported Technologies f in e d
un n de e fin
e d ®
• Intel Virtualization u Technology (Intel VT) ®
nd e
f in ® e d ® d u nd
e • Intel Active i n Management Technology 11.0 (Intel eAMT 11.0) u
un
d ef
• Intel®dTrusted Execution Technology (Intel® TXT) fin ed
u®n d
®
e f i n
• Intel
e d ® Streaming SIMD Extensions 4.2 (Intel un SSE4.2) n de
e fin• Intel® Hyper-Threading Technology (Intel ned HT Technology)
®
d
u
d • Intel 64 Architecture f i e
un • Execute Disable Bit n de e fin
ed u
d 2.0 un
d
f in • Intel® Turbo Boost Technology e
n de • Intel® Advanced Vector e finExtensions 2 (Intel® AVX2) n ed
f i
d
u • Intel® AdvanceduEncryption nd Standard New Instructions (Intel de® AES-NI)
e d n
e fin • PCLMULQDQ e(Perform
i n Carry-Less Multiplication Quad word)
d
u Instruction
u nd
d • Intel® Secure f Key e
un de fin ® ed
n
®
• Intelu Transactional Synchronization Extensions d e(Intel TSX-NI) f in
•ne
d
PAIR – Power Aware Interrupt Routing d u
n
nde
i e u
d ef• SMEP – Supervisor Mode Execution Protection f in e d
un • Intel® Boot Guard n de e fin
e d u (Intel® SGX) nd
in • Intel® Software Guard Extensions d u
f e
n de • Intel® Memory Protection
e finExtensions (Intel® MPX) ned
u d f i
d • Intel® Image SignalnProcessor (Intel® ISP) e
if n
e ®
• Intel Processor d
u
Trace u nd
e d un
d e f in n e d
un e i e
d
Note: The availability
un
d of the features may vary between processor
d ef SKUs.
f in
Refereto d Chapter 3 for more information. un n de
i n e d u
d ef f in e d
1.1.1 un Operating System Supportde fin
d u n d e
e d n
fin Processor Windows* 10
n e
Windows* 8.1 Windows* 7 Linux*u Chrome*
d
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un
d Line 64-bit
d ef 64-bit 64- & 32-bit
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d S-Processor Yesun Yes Yes Yesde Yes No


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d u nd
fi ne e d u
1.2.1 Processor Core Power Management fin ed
n de e i n
u • Full support of ACPI C-states as implemented d f
e d un by the following processor C-states:
n de
fin — C0, C1, C1E, C3, C6, C7,eC8 d u
d e f®i n e d
un • Enhanced Intel SpeedStep
de Technology in
d u n d ef
e Refer to Section 4.2 for d more information. un
f in ne d
de ef
i
in
e d
u
un d f e
ed un n de e fin
e d u d
fin e d un
n de e fin ned
u d f i
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ef
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un n de e fin
ed u
un
d
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i e
def f in e d un
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un de if n
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u
de if n e
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un
d ef
ed un
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d1.2.2 System Power Management ef
i n ed
un d f in
e d • S0/S0ix, S3, S4, u
n
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d Refer to Chapter
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e f•inDisabling Unused System Memory Outputs ned d
u
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un • DRAM Power Management and Initialization n de e fin
ed • Initialization Role of CKE d
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un
d
f in e
n de • Conditional Self-Refresh fin
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u • Dynamic Power Downd f i
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fin d
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d e • DDR Electrical
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un de
• Power training
n e fin n ed
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1.2.4 un Processor Graphics Power dManagement e fin
d u n d e
e d un
fin
1.2.4.1 Memory Power Savings Technologies e
n de ® e finManagement (Intel® RMPM) ned
u • Intel Rapid Memory Power
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d un Technology (Intel® S2DDT) e
if n
e • Intel® Smart 2D Display
d u nd
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d e 1.2.4.2 Display Power f inSavings Technologies n e d
un e fi e
d • Intel® u
nd
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• Inteled® Automatic Display Brightness u n de
fi n e d u
d •e Smooth Brightness f in e d
un • Intel® Display Power Saving Technology n de (Intel® DPST 6) e fin
e d • Low Power Single Pipe (LPSP) d u
d
fin e un
e f i n e d
nd
u1.2.4.3 Graphics Core Power Savings de Technologies fin
n e
ed • Intel® Graphics Dynamic d
u Frequency nd
if n e u
n de • Intel® Graphics
e finRender Standby Technology (Intel® GRST)
ned d
u
u • Dynamic d
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d
Refer to eSection 4.6 for more information. u d
f in e d un
n de e fin n ed
1.3 i
d Thermal Management uSupport
u nd f
e n de
e fin • Digital Thermal Sensor ned d
u
d • Intel® Adaptive Thermal Monitor f i e
un de in
d • THERMTRIP# and PROCHOT# u n support d ef
e un
f in • On-Demand Modeed
de n
fi Closed Loop Throttling e d u
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• External d
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f in e d un
n de e fin ned
u d f i
14 d un Datasheet, Volumed 1e of 2
e d n
if n e u
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e f in ned
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if n
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de if n ed
un de fin
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d e • Render Thermal Throttling f in e d
un • Fan speed controlnd
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d ef 5, “Thermal Management” for morefiinformation.
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1.4 e
fPackage Support n
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u
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un 1.5 Processor de
Testability in
d un d ef
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fin An XDP on-board n e connector is a must to enable the processor
d nd
d e For the processor
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un lower C-staten de debug. e fin recommended to enable i n ed
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u
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e u d
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e i n e d
d
un1.6 d ef f in
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if n d u nd
e
n de e fin ned d
u
u Table 1-2. Terminology d (Sheet 1 of 3) f i e
ed un n de e fin
ed
Term
d
Description
u
un
d
UHDfin Ultra High Definition e
n
e
dAES e fin n ed
u Advanced Encryption Standard
d f i
e d AGC Adaptive Gain Control un n de
e fin BLT ned
Block Level Transfer d
u
i e
un
d ef in
d
BPP Bits perd
u n
pixel
d ef
e CDR Clock and Data Recovery
d un
f in ne d
de CTLE i Continuous Time Linear Equalizer
ef Digital Display Interface for DP or HDMI/DVI fine d
u
un DDI d e
ed DDR3 un Third-generation Double Data Rate SDRAM n
e
dmemory technology e fin
e d u d
fin e d un
n de e fin ned
u d f i
d 1 of 2
Datasheet, Volume
e un n de 15
ef
in ed d
u
d f in e
un n de e fin
ed u
un
d
fin ed
i e
def f in e d un
n de fin ed
un de if n
ed un n de
fin ed Introduction
d
u
de if n e
un e in
un
d ef
ed un
d
if n ed
e
dTable 1-2. in
Terminology (Sheet 2 off3) ed
un de in
n ef
ed Term u Description
un
d e
if n DDR3L/RS ed DDR3 Low Voltage Reduced Standby Power d nd
de fin e u
un DDR4/DDR4-RS
n de Fourth-Generation Double Data Rate SDRAM
e f inMemory Technology n ed
u RS - Reduced Standby Power d f i
DFE ed decision feedback equalizer un n de
e fi n
DMA Direct Memory Access n ed d
u
d f i e
un DMI Direct Media Interfacede
n e fin
ed DP DisplayPort*
d
u
un
d
f in e
n de DTS
fin Sensor
Digital Thermal
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u ECC Error dCorrection Code - used to fix DDR transactions errors f i
e d un DisplayPort* n de
fi n eDP* d embedded
e Execution Unit in the Processor Graphics u nd
d e EU f i n e d u
un GSA n de Graphics in System Agent e fin n ed
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HDCP d
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in d u
d ef
HDMI* High Definition Multimedia Interface
f i ne e d
un IMC Integrated Memory Controller
n de e fin
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Intel 64 Technology 64-bit memory extensionsu to the IA-32 architecture d
fin Intel DPST®
Intel Display Powere d Saving Technology un
n de e finTrust Technology n ed
u Intel PTT ® Intel Platform
d f i
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nd
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e Intel TSX-NI Intel
d
if n e u
un
®
d e Intel TXT
f in Intel Trusted Execution Technology e d
un e i n d
d Intel VT ®
un
d with Virtual Machine Monitor software, enables
d ef multiple, robust independent
Intel Virtualization Technology. Processor virtualization, when used in conjunction
f i ne
ed un
software environments inside a single platform.
n de
i n Intel Virtualization Technology d
(Intel VT) for Directed I/O. Intel VT-d is a hardware u
d ef VT-d
Intel ®
f ne Machine Manager or OS) control, for enablinged
assist, under system software i(Virtual

un
I/O device virtualization.
protection from errant DMAs
n de by using DMA remapping, a key feature of Intel VT-d.
Intel VT-d also brings robust security by providing
e fin
e d u d
fin IOV I/O Virtualization d
e un
e i n e d
un
d ISP Image
ef
Signal
d
Processor
fin
n
Low Frequency Mode. corresponding to the Enhanced Intel SpeedStep e ®

ed LFM u
Technology’s
d lowest voltage/frequency pair. It can be readnat d MSR CEh [47:40].
if n e u
n de LLC
e fin Last Level Cache n ed d
u
u d Low-Power Mode.The LPM Frequency is less f
than i or equal to the LFM Frequency. The e
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un LPM TDP is lower than the LFM TDP as the LPM
n de configuration limits the processor to e fin
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single thread operation
u d
LPSP fin Low-Power Single Pipe e d un
n de Lowest Supported Frequency.This e finfrequency is the lowest frequency where n ed
u LSF
manufacturing confirms logical d functionality under the set of operating conditions. f i
e d un MFM is the minimum ratio supported by the processor n de
e fin MFM
Minimum Frequency
and can be read from
n ed MSR CEh [55:48].
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d
u
d fi e
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Mid-Level Cache
n fin
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Non-Critical to Function. NCTF locations are typically redundant
n d or non-
f in NCTF e d reserved balls/lands, so the loss of the solder jointucontinuity
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u
u PAG d Platform Power Architecture Guide (formerly PDDG) f i e
ed un n de e fin
e d u d
f in e d un
n de e fin ned
u d f i
16 d un Datasheet, Volumed 1eof 2
e d n
if n e u
n d e
e fin n ed
u d f i
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if n
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i e
def f in e d un
n de fin ed
un de if n
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de if n ed
un de fin
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if n e d u
d eTable 1-2. Terminology (Sheet 3 of f in3) e d
un n de e fin
e d Term u Description d e
f in e d Platform Controller Hub. The chipset with centralized un platform capabilities including nd
e i n e d u
un
d PCH
d ef the main I/O interfaces along with display connectivity,
management, manageability, security, and f
audio features, power
instorage features. The PCH may also be ed
un referred as “chipset”. d e f i n
e
PECI d Platform Environment Control Interface un n de
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n
fiPEG PCI Express Graphics n ed d
u
d f i e
un PL1, PL2, PL3 Power Limit 1, Power
n
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d
u component (package)
un
d
f in e d multiple
The termin
n de Processor Core e
executionf “processor core” refers to Si die itself, which can contain
cores. Each execution core has an instruction cache, i n edata cache, and 256-
u KBn dL2 cache. All execution cores share the LLC. e f
ed u
d Intel Processor Graphics un
d
fin Processor Graphics
ne d nd
d e PSR f i Panel Self-Refresh e u
un n de fin
A unit of DRAM corresponding to four toeeight devices in parallel, ignoring ECC. n ed
Rank u d f i
e d These devices are usually, but not always,
un in the ACPI protocol.
mounted on a single side of a SODIMM.
nde
ef
in
SCI System Control Interrupt. SCI
edis used u
d Scenario Design Power. The f inPower consumed by a typical scenario. For more ned
un SDP information, refer to the
n deScenario Design Power (SDP) Implementation
ef
i
e d Considerations document
u (see Related Documents section). d
fin SGX Software Guard edExtension un
d e n
fi Algorithm e d
un
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f in
un Spectrum Clock e
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d
Spread
nd
if n u
e A non-operational state. The processor may be installed in a platform, in a tray, or
d e f in loose. Processors may be sealed in packagingnoredexposed to free air. Under these un
un e conditions, processor landings should not beficonnected to any supply voltages, have d
d un
d
Storage Conditions any I/Os biased, or receive any clocks. Upon
d e exposure to “free air” (that is, unsealed f i ne
ed
packaging or a device removed from n
handled in accordance with moisture u packaging material), the processor must be
sensitivity labeling (MSL) as indicated on the n de
i n e d u
d ef packaging material.
f in e d
un TAC
STR Suspend to RAM e in
d Thermal Averagingu nd
Constant d ef
e un
e fin TCC Thermal Control
n edCircuit d
d f i e
un TDP Thermale
n d Design Power e fin
ed TOB u Budget
Tolerance
d nd
if n e Thermal Test Vehicle TDP u
ed
TTV TDP
n de e fin Processor core power supply i n d
u
u V CC d f e
ed V CCGT un Processor Graphics Power Supply
n de e fin
ed d
u
un
d
V
fin
CCIO I/O Power Supply
e
n dVe CCSA System Agent Power Supplyfin
e n ed
f i
d V
u CCST Vcc Sustain Power Supply
u nd de
e n
e fin V DDQ DDR Power Supply
ned d
u
d VLD Variable f
Lengthi Decoding e
un de in
d VPID VirtualnProcessor ID
u d ef
e d un
f in V SS
neProcessor Ground
d
de ef
i
in
e d
u
un d f e
ed un n de e fin
e d u d
fin e d un
n de e fin ned
u d f i
d 1 of 2
Datasheet, Volume
e un n de 17
ef
in ed d
u
d f in e
un n de e fin
ed u
un
d
fin ed
i e
def f in e d un
n de fin ed
un de if n
ed un n de
fin ed Introduction
d
u
de if n e
un e in
un
d ef
ed un
d
if n ed
e
d1.7 Related Documents ef
i n ed
un d f in
e d un n de e
f in e d u nd
e Table 1-3. Related Documents n d u
i e
un
d
def Document f in Document Number/Location ed
u n d e f i n
®
6th Generation Intel Core
e d Processor Family Datasheet, Volume 2 of 2 un 332688
n de
6th Generation Intel
e finCore Processor Family Specification Update ined
®
332689
d
u
d f e
6th Generation
un Intel Processor Platform I/O Datasheet, Volumen1dofe 2
®
332690
e fin
ed Intel Processor Platform I/O Datasheet, Volume
6th Generation
n
®
d
u 2 of 2 332691
u nd
f i ® e 332692d
e Generation Intel Processor Platform I/O Specification fin
6th Update
dAdvanced e
u n Configuration and Power Interface 3.0 de f in
http://www.acpi.info/

ed DDR3 SDRAM Specification un n de


http://www.jedec.org
fi n e d uhttp://www.jedec.org nd
d e DDR4 Specification
f i n e d u
un High Definition Multimedia Interface
n despecification revision 1.4 e fin
http://www.hdmi.org/manufacturer/specifi-
n ed
u d cation.aspx
f i
e d
Embedded DisplayPort* Specification revision 1.4 un http://www.vesa.org/vesa.standards/
nde
in
ef revision 1.2
DisplayPort* Specification ed d
u
d f in http://www.vesa.org/vesa.standards/
e
http://www.pcisig.com/specifications in
un Specification Revision 3.0
PCI Express* Base
n de ef
®
Intel 64 e d
and IA-32 Architectures Software Developer's Manuals u d
http://www.intel.com/products/processor/
manuals/index.htm n
e fin n ed d
u
d f i e
un n de e fin
ed d
u
un
d
f in e
d e f in e d un
un e §§ i n e d
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e d n
if n e u
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u d f i
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if n
e d u nd
e
i e
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un de if n
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un de fin
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e d un n de
fin• Two channels of DDR3L/-RS and DDR4 d
ememory with a maximum of two DIMMs per u
d e channel. DDR technologies, number f i n
of DIMMs per channel, number of ranks e
perd
un channel are SKU dependent.
n de e fin
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d Down support (based on SKU) un
d
f in e
n de • Single-channel and dual-channel
e fin memory organization modes
n ed
u • Data burst length n ofdeight for all memory organization modesef i
e d u d
fin • DDR3L/-RS I/O
e d Voltage of 1.35V - based on Processor Line un nd
e • DDR4 I/O i n
Voltage of 1.2V e d u
un
d ef fin ed
• 64-bitnd wide channels e i n
u UDIMM and SODIMM DDR4/DDR3L/-RS d f
d
• Non-ECC
e un support (based on SKU) nde
in d u
d ef• Theoretical maximum memory bandwidth f i ne of: e d
un — 20.8 GB/s in dual-channel mode
— 25.0 GB/s in dual-channel u
e assuming 1333 MT/s
nd assuming 1600 MT/s
mode e fin
e d d
fin — 29.1 GB/s in dual-channel e d mode assuming 1866 MT/s un
n de — 33.3 GB/s in dual-channel
e fin mode assuming 2133 MT/s ned
u d f i
e d Note: Memory down of all technologies un (DDR3L/DDR4) should be implemented n de
if n homogeneously, which d
e means that all DRAM devices shoulddbe from the same vendor u
d e and have the same f in part number. Implementing a mix ofnDRAM e devices may cause un
un e i e d
d
serious signal
un
d integrity and functional issues.
d ef f in
Note: d
If theeS-Processor Line memory interface is configured un to one DIMM per Channel, the nde
i n e d u
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processor
CTRL[3:2].
can use either of the DIMMs, DIMM0
f in or DIMM1, signals CTRL[1:0] or ned
un nde e fi
e d u d
2.1.1 fin System Memory Technology e d Supported un
d e f i n e d
un The Integrated Memory Controller
n de (IMC) supports DDR3L/-RS and DDR4
e fin protocols with
ed two independent, 64-bit
d
u wide channels. nd
if n e u
n de Table 2-1. Processor DRAM
e finSupport Matrix ned d
u
u d f i e
ed un Line
Processor 1
DPC DDR3L/-RS
n de DDR4 LPDDR3
e fin
ed Line 1333/1600 d
u
un
d
f in
S-Processor 2
e 1866/2133 N/A

n
e
dNotes: e fin n ed
u 1. DPC = DIMM Per Channel. d f i
e d 2. Increasing the DDR4 rate to 2133 MT/s may
un lead to TDP power penalty up to 400mW, n de
fin ed
and 5-10% battery life impact.
u
d e f i n e d
un • DDR3L/-RS Data Transfer
de Rates: in
d — 1333 MT/s (PC3-10600) u n d ef
e d un
f in — 1600 MT/s (PC3-12800)
n e d
de • DDR4 Data e fi
Transfer Rates: in
e d
u
un d f e
ed — 1866 unMT/s (PC4-1866) n de e fin
d
— e2133 MT/s (PC4-2133) u d
f in e d un
n de e fin ned
u d f i
d 1 of 2
Datasheet, Volume
e un n de 19
ef
in ed d
u
d f in e
un n de e fin
ed u
un
d
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i e
def f in e d un
n de fin ed
un de if n
ed un n de
fin ed Interfaces
d
u
de if n e
un e in
un
d ef
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if n ed
de • SODIMM Modules: fin ed
un e in
d
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n Modules: ef
ed u
un for x8 and x16
d technology and addressing are supported
d
de
if n — Standard e4-Gb
de if n
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un de
DDR4 SODIMM/UDIMM
n Modules: fin e n ed
u d f i
e —d Standard 4-Gb and 8-Gb technologies and u naddressing are supported for x8 and
n de
e fin x16 devices. n ed d
u
d f i e
un There is no support for memory n de
modules with different technologies or capacities e fin
ed on opposite sides of the same memory u
d identical module. If one side of a memorynmodule d is
f in populated, the other side is
n e either or empty. d
u
e i
un
d
• DDR3L/-RS Memory Down: d ef Single and dual rank x8, x16 (basedfion neSKU)
ed • DDR4 Memory Down:
un Single rank x8, x16 (based on SKU) nde
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un 2.1.1.1 DDR3L/-RS
n deSupported Memory Modules andefDevices in n ed
u d f i
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Table 2-2. in
Supported
ef
DDR3L/-RS Non-ECC UDIMM Module ed Configurations (S-Processor
d
u
Line)
d f in e
un n de e fin
d
eCard
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finVersion DIMM
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d A 4GB 4Gb
un 512M x 8 8 1 16/10 e8 8K

if n
e B 8GB 4Gb ed 512M x 8 16 2 16/10u
nd 8 8K
d e f in e d un
un e i n e d
d un
d
d ef f in
Table 2-3. Supported ed DDR3L/-RS Non-ECC SODIMM Module un Configurations (S-Processor nde
i n e d u
d ef
Line)
f in e d
Rawu
n DRAM n d#eof # of # of
Page de
fin
e d
Card
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finVersion Capacity Density Organization e d Devices Bits DRAM u


d e f in e d
un A 4GB 4Gb de x 16
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d n
u 512M x 8 d e
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n de C 2GB 4Gbin
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un n de e fin
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f in Table 2-4. Supported DDR4 e d Non-ECC UDIMM Module Configurations un (S-Processor Line) nd
e i n e d u
un
d
d ef DRAM f in # of # of ed
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DIMMn
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n de B 16GB 8Gb
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i
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un 256M x 16 4 1
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fi n C 4GB 8GB
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nd
d e f i n e d u
un n de e fin n ed
Table 2-5. Supported u DDR4 Non-ECC SODIMM Module Configurations
d (S-Processor Line) f i
e d un nde
Raw finDIMM DRAM # of ed # of Row/Col Banks Page
# of # of
d
u
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f in
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deDevices fin
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un
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n Bits DRAM
e
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de A 8GB 8Gb fin x 8
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d 8K
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n de 16 8K

in B 16GB 8Gb d 1024M x 8 16 2 u


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d ef C 2GB f ne
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un
un d e n
fi 16/10 e d
d C 4GB
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un2.1.2 System Memory Timing
n de Support
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if n The IMC supports the following DDR Speed Bin,
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CAS Write u
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n de command signalfimode
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un Latency n de e fin
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d Command delay un
d
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n d•e tRP = PRECHARGE Command Period efin n ed
u • CWL = CAS Write Latency d f i
e d un n de
e fin • Command Signal modes:
ned d
u
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un n de
— 1N indicates a new DDR3L/DDR4 command may be issued every
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d
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un
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un Table 2-6. e in
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u
un
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Device
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fi
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un de fin Only)
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2.1.3 ef
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System Memory Organization Modes
n ed
n if n
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d memory organization modes, single-channel
fin e u d
de
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memory channel,
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un is used when either the Channel A or Channel n de B DIMM connectors are populated einfiany
e d order, but not both. u d
fin e d un
de Dual-Channel Mode – Intelf® inFlex Memory Technology Mode ned
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u
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Flex
ef into a
e d n
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d e each channel andfin is contiguous until the asymmetric zone begins e d or until the top un
un e i n d
d address of the
u ndchannel with the smaller capacity is reached. d ef In this mode, the system f i ne
runs with one zone of dual-channel mode and one zone
ed
simultaneously, across the whole memory array.d u
n of single-channel mode,
n de
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Note:
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versa. However, channel A size must u
de channel 0 and 1 respectively or viceefin
ben greater or equal to channel B size.
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un ef
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un
d
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un de Mode (Interleaved Mode)
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un mode, also known as interleaved mode, e
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if n e world applications. Addresses are ping-ponged u
d e performance onin
f real
e d between the un
un channels after e
d each cache line (64-byte boundary). Ifethere n
fi are two requests, and the e d
d un is to an address on the opposite channel
second request d from the first, that request can f in
be sentedbefore data from the first request has dreturned. un If two consecutive cache lines
n de
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d ef requested,
opposite
both may be retrieved simultaneously,
channels. Use Dual-Channel Symmetric f in mode when both Channel A and ne
d
n
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ethe
un ef
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channel to the other. u
u n d e f i n e d
ed 2.1.4 System unMemory Frequency n de e fin
d u d
f i ne e d un
is the lowest frequency of all memoryed
n
Ineall modes, the frequency of system memory
d
modules placed in the system, as e
determined
fin through the SPD registers on the fin
u d
ed memory modules. The system memory n
u controller supports up to two DIMM connectors n de
fi n per channel. If DIMMs with different
e d latency are populated across the u
channels, the
e i n e d
un
d BIOS will use the slower of
ef
the two latencies for both channels. For Dual-Channel
in
d
modes both channels mustdhave a DIMM connector populated. For Single-Channel
u n d ef
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d un
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d2.1.5 Technology Enhancements ef
i n of Intel® Fast Memory ed Access
un d f in
ed The following sections undescribe the Just-in-Time Scheduling, Command n de Overlap, and e
f in Out-of-Order Scheduling e d Intel FMA technology enhancements. u nd
e i n e d u
un
d
d ef f in ed
Just-in-Time
u n Command Scheduling
d e f i n
ed
Thenmemory controller has an advanced command un scheduler where all pending n de
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requests are examined simultaneously to idetermine n ed the most efficient request to be d
u
d f e
un issued next. The most efficient request e
d isoptimal
picked from all pending requests and issued in
fThus,
to system memory Just-in-Time to n
make use of Command Overlapping. e
ed u
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d
f in instead of having all memory access
e d
de mechanism forcing requests fto in be executed one at a time, they can benestarted without
u n interfering with the current
d erequest allowing for concurrent issuing of
f i requests. This
d allows for optimized un
bandwidth and reduced latency while d
maintaining
e appropriate
e un
fin command spacing e todmeet system memory protocol. nd
d e f i n e d u
un CommandnOverlap de e fin n ed
u d f i
Command e d Overlap allows the insertion of the DRAM un commands between the Activate, nde
in d u
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Pre-charge, and Read/Write commands normally
f i ne used, as long as the inserted e d
commands do not affect the currently executing command. Multiple commands caninbe
un issued in an overlapping manner, increasing n de the efficiency of system memory protocol. ef
e d u d
fin ed un
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un
d
While leveraging the Just-in-Time d ef Scheduling and Command Overlap fenhancements, in
un e
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if n e of latency. If there are multiple requests u
d e bandwidth and reduction
f in would e d to the same open un
un page, these e
requests be launched in a back to back i n manner to make optimum
e d
d use of the open
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n de
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2.1.6 ef Scrambling
Data
d f in e d
unThe system memory controller incorporates de a Data Scrambling feature to minimizeefthe in
d u n d
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d
d e 0s on the data bus. Past experience
f i has demonstrated that traffic on the data
e bus is not
un random and can have energy d econcentrated at specific spectral harmonics f in creating high
ed di/dt which is generally limited un by data patterns that excite resonance n de between the
in d
e on die capacitances. As a result the system u
d ef package inductance and
uses a data f
scramblingin feature to create pseudo-random patterns e d onmemory the
controller
system u
u n d e f i n e d
memory datanbus to reduce the impact of any excessiveedi/dt.
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un n de e fin
e d The processor supports u I/O interleaving, which has the abilityndto swap DDR bytes for e
f in routing considerations. e d BIOS configures the I/O interleaving u mode before DDR training. nd
d e f i n e d u
un There are n d2
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u d f i
d
• Interleave
e (IL) un n de
e fin• Non-Interleave (NIL) ned d
u
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un The following table and figure describe n dethe pin mapping between the IL and NIL e fimodes.
Table ed u
un
d
f in 2-7. Interleave (IL) and Non-Interleave e d (NIL) Modes Pin Mapping

n de IL
e fin NIL n ed
u d f i
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un Channel Byte
n de
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ned
Byte0 DDR0 Byte0
d
u
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fin ed
DDR0u
n Byte2 DDR0 Byte4 d e f in
e d un nde
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Byte3 DDR0 Byte5
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u
d Byte4 DDR1 f
Byte0in e
un n
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dByte1 e fin
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u d
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n de e fin ned
u DDR0 Byte7
d DDR1 Byte5
f i
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if n
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d
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u nd
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Byte1 DDR0 Byte3
n e d
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d ef f in
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DDR1 Byte3 DDR0 Byte7
un n de
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un DDR1 Byte5 DDR1
nde
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fin e d un
d e DDR1 Byte7 DDR1
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unFigure 2-2. Interleave (IL) and Non-Interleave n de e fin
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un
if n ne d
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f n e d
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d2.1.8 Data Swapping if n ed
un d e f in
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f in segments and DRAM
d
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e i n e d u
un
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un n de
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2.1.9 ndDRAM Clock Generation f in e
u n de e fin
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d DRAM. un
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n de e fin n ed
u d f i
e d 2.1.10 DRAM Reference un Voltage Generation n de
e fin n ed has the capability of generating the dDDR3L/-RS u
u nd
d The memory f i
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un de (VREF) internally for both read andewrite
Reference Voltage fin operations. The generated ed
n
VREF canube changed in small steps, and an optimum d VREF value is determined for f in
e d a cold boot through advanced trainingunprocedures in order to provide the nde
both during
in
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best ed d
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un n de e fin
2.2ine d PCI Express* Graphics u Interface (PEG) d
f e d un
n de
Note: The processor’s PCI Express* e
in
finterface is present only in 2-Chip platform nedprocessors.
u d f i
d unPCI Express* interface capabilities of the e
if n
e This section describes the
d u nd processor. See the
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PCI Express Base*nSpecification 3.0 for details on PCI Express*. d un
d f i n e d
un e i e
d 2.2.1 PCI Express* un
d
Support d ef f in
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The fprocessor’s PCI Express* interface is a 16-lane d
e (x16) port that can also be u
d e
configured as multiple ports at narrower widths f in (see Table 2-8, Table 2-9). e d
unThe processor supports the configurations n de e fin
e d u shown in the following table. d
fin e d un
d e f i n e d
un n de e fin
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u
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un Table 2-8. de and Lane Reversal Mapping
PCI Express* Bifurcation in
n ef
ed Link Width
d
uConfig. Signals
un
Lanes
d
de
if n e
de
Bifurcation
0:1:0 0:1:1 n
fi0:1:2 CFG CFG CFG 0 1 2 3 4 5 6ed7 8 9 10 11 12 13 14 15 un
un de [6] [5] [2]
fin ed
1x16
n
x16u N/A N/A 1 1 1 0 1 2 3 4
de5 6 7 8 9 10 11 12 13 14 15 fin
e d u11n de
1x16 Reversed
fi n x16 N/A N/A 1 1 0 15 14
e
13
d12 10 9 8 7 6 5 4 3 2 1
u0 n
2x8
nde x8 x8 N/A 1 0 1 0 n
1 i2
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3 4 5 6 7 0 1 2 3 4 5
n e6 d 7
u 1 0 0 7nd6 5 4 3 2 1 0 7 6 5 4 3 e2f
i 1 0
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u n d
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1x8+2x4 x8 x4 x4 0 0
n e1d 0 1 2 3 4 5 6 7 0 1 2 d3 u 0 1 2 3
i
d
un 1x8+2x4 Reversed x8 x4 x4
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d e0 f 0 3 2 1 0 3 2 1 0 7 6 fin5 e 4 3 2 1 0
ed Notes: un 6.4. n de
fi n 1. For CFG bus further details, refer to dSection
ewidth and use devices with lower number of lanes (that u is, usage on x4 configuration), nd
d e 2. Support is also provided for narrow
however further bifurcation is f
i n e d u
un 3.
enot supported.
In case that more than oneddevice is connected, the device with the highest lane fcount, in should always be connected to the ed
lower lanes, as follows:u n d e f in
— Connect lane 0dof 1st device to lane 0.
e un nde
— Connect lane
in 0 of 2nd device to lane
eflane 0 of 3rd device to lane 12.
8.
ed d
u
— Connect
For example:d f in e
n
a. u When using 1x8 + 2x4, the 8 lane device must use lanes
n de 0:7. e fin
e d
b. When using 1x4 + 1x2, the 4 lane device must use u lanes 0:3, and other 2 lanes device must use
ndlane device
lanes 8:9.

fin c. When using 1x4 + 1x2 + 1x1, 4 lane device must


e d use lanes 0:3, two lane device must use lanes 8:9,uone
fin ed
must use lane 12.
n d4.e For Reversal lanes, For example: e i n
u — When using 1x8, the 8 lane device
nduse lanes 12:15, so lane 15 will be connected to dlane
must use lanes 8:15, so lane 15 will be connected to lane f
e 0 ofthetheDevice.
0 of
e d — When using 1x4, the 4 lane device must u Device.
nlane 0 of the Device.
if n — When using 1x2, the 4 lane device
e d must use lanes 14:15, so lane 15 will be connected to
u
d e f in e d un
un e
The processor supports the following: i n e d
d • Hierarchical
d
un PCI-compliant configuration mechanism d ef for downstream devices f in
• n ed
Traditional PCI style traffic (asynchronous d un
snooped, PCI ordering) n de
i e u
d e•f PCI Express* extended configuration space. f in The first 256 bytes of configurationned
un space aliases directly to the PCI Compatibility
n de configuration space. The remaining
e fi
e d portion of the fixed 4-KB block of u memory-mapped space above that (starting d at
fin 100h) is known as extendedeconfiguration d space. un
de fin Mechanism. Accessing the device iconfiguration d
un • PCI Express* EnhancedeAccess
d f ne
e d space in a flat memory
un mapped fashion n de
in • Automatic discovery, d negotiation, and training of link out of u
d ef f i n e
e d reset. u
n • Peer segment e destination posted write traffic (no peer-to-peer i n read traffic) in d
u d f e
ed
Virtual Channel
un 0: DMI -> PCI Express* Port 0
n de e fin
• 64-bit d downstream address format, but the processor u never generates an address d
f ne 512 GB (Bits 63:39 will always be zeros)
iabove e d un
n d•e 64-bit upstream address format, but ethe finprocessor responds to upstream read ined
u transactions to addresses above 512 ndGB (addresses where any of Bits 63:39deare f
e d u n
nonzero) with an UnsupporteddRequest response. Upstream write transactions to
e fin addresses above 512 GB will i n ebe dropped. d
u
d ef that have been previously completed e
un • Re-issues Configurationdcycles
n e fin with the
ed Configuration Retry status u d
f in • PCI Express* e d
reference clock is 100-MHz differential clock
un
de i n e d u
un • Power Management d ef Event (PME) functions f in e d
ed • Dynamic unwidth capability n de e fin
e d u d
fin e d un
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fin ed Interfaces
d
u
de if n e
un e in
un
d ef
ed un
d
if n ed
de fin (MSI and MSI-X) messages
• Message Signaled Interrupt ed
un de in
• Lane reversal n ef
ed u
un
d e
if n ed Reporting (AER) and control capabilities
• Full Advance Error
d nd
de fin ne
u
un The following
n d etable summarizes the transfer rates andfitheoretical
e
bandwidth of PCI
n ed
Express*ulink. d f i
e d un n de
Table 2-9. finExpress* Maximum Transfer Ratesinand
PCI
e ed Theoretical Bandwidth d
u
d f e
un Express* PCI Maximum
n de Theoretical Bandwidth [GB/s]
e fin
ed Encoding Transfer Rate
d
u x8 un
d
f in Gen [GT/s]
n e x1 x2 x4
d
x16

d e i
f 2.5 e
de 5 fin 4.0
Gen 1 8b/10b 0.25 0.5 1.0 2.0 4.0
un n e
ed Gen 2 8b/10b
d
u 0.5 1.0 2.0
un
d 8.0

fin Gen 3
ne
128b/130b 8 1.0 2.0
d 3.9 7.9 15.8 nd
d e f i e u
un Note: The processor
n dehas limited support for Hot-Plug, for details e fin refer to Section 4.4. n ed
u d f i
e d un nde
2.2.2 PCI in Express* Architecture ed u
d ef f in e d
un Compatibility with the PCI addressing model
n de is maintained to ensure that all existing e fin
e d applications and drivers operate unchanged. u d
fin e d un
de The PCI Express* configuration finuses standard mechanisms as definedininethe d PCI Plug
u n and-Play specification. The d e
processor PCI Express* ports support Gen f 3.
d un results in twice as much bandwidth per e as compared to
if n
e At 8 GT/s, Gen 3 operation
Gen 2 operation. The d16 lanes port can operate at 2.5 GT/s, 5 u ndlane
GT/s, or 8 GT/s.
e d un
d e f in n e d
un Gen 3 PCI Express*d e uses a 128b/130b encoding which isfiabout 23% more efficient e
d un encoding used in Gen 1 and Gen 2.nde
than the 8b/10b f in
ed u n de
n
i Express* architecture is specified in three
The fPCI d
e layers – Transaction Layer, Data Link d u
d e and
Layer, Physical Layer. See the PCI Expressf in Base Specification 3.0 for details of PCI e
unExpress* architecture. n de e fin
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d e2.2.3 PCI Express* in
Configuration
f Mechanism e d
un n de e fin
e d The PCI Express* (external u graphics) link is mapped throughna d PCI-to-PCI bridge e
f in structure. e d u nd
e i n e d u
un
d
Figure 2-3. PCI Express* d ef Related Register Structures in thefinProcessor ed
un d e f i n
e d un n de
e fi n ned d
u
d f i e
un n de e fin
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PEG fin
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un
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e fin
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fin PCI Express* extends the e d
configuration space to 4096 bytes
un
per-device/function, as
d e f in by the conventional PCI specification.nePCI d
un compared to 256 bytes e
allowed i Express*
d configuration space is divided
u nd into a PCI-compatible region (thatdconsists ef of the first
e 256 bytes of a logical d device's configuration space) and an extended n PCI Express*
if n e u
d e region (that consistsf in of the remaining configuration space). e dThe PCI-compatible region un
un can be accessed e n
d using either the mechanisms definedefini the PCI specification or using e d
d the enhanced un PCI Express* configuration access mechanism d described in the PCI f in
Express* ed Enhanced Configuration Mechanism section. un n de
i n e d u
d ef PCI Express* Host Bridge is required ftointranslate
The the memory-mapped PCI e d
un Express* configuration space accesses e the host processor to PCI Express* fin
dfrom
e d configuration cycles. To maintain compatibility u n with PCI configuration addressing n de
i n d u
d ef mechanisms, it is recommended
f i nethat system software access the enhanced e d
configuration space using 32-bit operations (32-bit aligned) only. Seein
un Base Specification for details n de of both the PCI-compatible and PCI Express* e f the PCI Express
Enhanced
e d u and transaction rules. d
fin configuration mechanisms
e d un
d e f i n e d u
n e i n e d
u 2.2.4 PCI Express* d Equalization Methodology f
ed un n de e fin
n ed
The equalization of link requires equalization fordboth u TX and RX sides for the processor nd
u
and f ifor the End point device. n e d
d e f i e
unAdjusting transmitter and receiver of the n delanes is done to improve signal reception e fin
ed quality and for improving link robustness d
u and electrical margin.
un
d
f in e
n de The link timing margins and e fin margins are strongly dependent oninequalization
voltage ed of
u the link. n d e f
ed d
u nd
f in The processor supports e u
n de e fin the following: i ned d
u
u • Full TX Equalization:
d Three Taps Linear Equalization (Pre, f Current and Post e
ed cursors), unwith FS/LF (Full Swing /Low Frequency)nd24/8 e values respectively.
e fin
e d u d
fin e d un
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u d f i
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ef
in ed d
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un e in
un
d ef
ed un
d
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de • Full RX Equalization andin ed CDR (Clock
ef acquisition for: AGC (Adaptive Gain Control),
un and Data Recovery),dadaptive DFE (decision feedback equalizer) f inand adaptive CTLE
un time linear equalizer). e
ed peaking (continuous
d nd de
if n e u
de inphase 3 EQ compliant with PCI Express* dGen 3 specification
• Full adaptive
e un
un ef fin ed
ndExpress* Base Specification 3.0 for details
See the PCI
u e on PCI Express* equalization.
d fin
e d un n de
i n e d u
2.3 d ef
Direct Media Interface (DMI) f in ed
n
u Direct Media Interface (DMI) connects d e f i n
e d un the processor and the PCH. n de
e fin Main characteristics: n ed d
u
d f i e
un • 4 lanes Gen 3 DMI support de in
d • 8 GT/s point-to-point u n DMI interface to PCH d ef
e d unPCH
fin • DC coupling -n e
no capacitors between the processor and dthe nd
d e f i e u
un • PCH end-to-end
n de lane reversal across the link
e fin n ed
• Half-Swingu support (low-power/low-voltage) n d f i
e d u nde
in d u
Note: ef DMI x4 configuration is supported. fine
Only
d e d
n
Note: d u Polarity Inversion on DMI Link is not allowed n de on both sides of the processor and ethe fin
e u d
fin PCH.
e d un
n de e fin n ed
u 2.3.1 DMI Error Flow nd f i
e d u n de
if n DMI can only generate d
e SERR in response to errors; never SCI, u
d e GPE. Any DMI related f in SERR activity is associated with Device e d0.SMI, MSI, PCI INT, or un
un e i n e d
d un
d
def f in
2.3.2 DMI eLink d Down un n de
i n e d u
The
d efDMI link going down is a fatal, unrecoverable f in error. If the DMI data link goes to ned
undata link down, after the link was up, then n dethe DMI link hangs the system by not efi
d
e allowing the link to retrain to prevent u d by
if n the PCH. e d data corruption. This link behavior is controlled un
de fin ed
un Downstream transactions n de had been successfully transmitted across
that f inthe link prior
d u be processed as normal. No completions e
dfrom
e to the link going down may
d n downstream,
fin non-posted transactions e are returned upstream over the DMI u after a link
link down
n de event. e fin ned d
u
u d f i e
ed un n de e fin
2.4 Processor ed Graphics d
u
un
d
f in e
n
Thedeprocessor graphics is based on GEN 9 (generation e fin 9) graphics core architecture in
ed
u
d that enables substantial gains in performance
d
un and lower-power consumption over ef
dprior
e n
e fin generations. GEN 9 architecture supports
n ed up to 72 Execution Units (EUs), depending d
u on
d the processor SKU. fi e
un de in
d The new processor graphics u n architecture delivers high dynamic range d eoff scaling to
e d low power to high power, increased performance un
f in address segments spanning
n e d
per watt,
e support for next i
generation of APIs and extends heterogeneous e programmability with u
un
d ef
IA core/GPU anddShared Virtual memory (SVM). GEN 9 scalable f in architecture is e d
ed partitioned by unusage domains along Render/Geometry,ndMedia, e and Display. The
e fin
e d u d
f in e d un
n de e fin ned
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de if n ed
un de fin
ed un nde
if n e d u
d e architecture also delivers fvery in low-power video playback and next ngeneration e d analytics
un and filters for imaging d
e
related applications. The new Graphics Architecture f i includes 3D
ed n
compute elements, uMulti-format HW assisted decode/encodenpipeline, de and Mid-Level e
f in Cache (MLC) for
d
esuperior high definition playback, video d u and improved 3D
quality, nd
e i n e u
un
d performance
d efand media. f in ed
n
u Engine handles delivering the pixelsnto e
d the screen. GSA (Graphics in f i n
The Display
e
System
d Agent) is the primary channel interface
u for display memory accesses and “PCI- n de
e
in traffic in and out.
flike” ned d
u
d f i e
un The display engine supports the latest n dedisplay standards such as eDP* 1.3, DP* e fin1.2,
ed HDMI* 1.4, HW support for blend,
u
d scale, rotate, compress, high PPI support,
d
un and
f in e
n de advanced SRD2 display power
e fin management. n ed
u d f i
e d 2.4.1 API Support un
(Windows*) n de
e fin n ed d
u
u nd
d • Direct3D*
i
f 12, Direct3D* 11.3, Direct3D* 11.2, Direct3D e 11.1, Direct3D 9,
un n
Direct3D de10, Direct2D e fin n ed
u d f i
d
• OpenGL*
e 4.4 un nde
in
ef• OpenCL* 2.1, OpenCL* 2.0, OpenCL*fin1.2 ed d
u
d e
un Direct3D* 11.x extensions: n de e fin
e d u d
fin • PixelSync, InstantAccess. d
e un
n de Gen 9 architecture delivers e
in
fhardware acceleration of Direct X* 11 n
Render
ed pipeline
u d f i
d comprising of the following un stages: Vertex Fetch, Vertex Shader, e Shader,
Hull
if n
e Tesselation, Domain d Shader, Geometry Shader, Rasterizer, u ndShader, Pixel Output.
Pixel
e un
d e The Direct X* 12 f inAPI is supported at feature level 12_1.ned d
un e i e
d u nd ® d ef f in
2.4.2 Media d Support (Intel QuickSyncun& Clear Video de
e
Technology
n HD) d u n
i e
d ef f in e d
un GEN 9 implements multiple media video n decodecs in hardware as well as a rich setefofin
e d image processing algorithms. u d
if n e d un
de
Note: All supported media codecseoperate fin on 8 bpc, YCbCr 4:2:0 video profiles. ed
un d f in
e d 2.4.2.1 Hardware Accelerated un Video Decode n de
in e d u
d ef GEN 9 implements fin a high-performance and low-power HW e d
acceleration for video
u
u n d e f i n e d
ed
decoding operations
un for multiple video codecs.
n de e fin
The HW ed u
un
d
f in decode is exposed by the graphics driver e d using the following APIs:
n d•e Direct3D* 9 Video API (DXVA2) e fin n ed
i
d
u • Direct3D11 Video API
u nd d ef
e n
e fin • Intel Media SDK
n ed d
u
d • MFT (Media Foundation i
Transform)
f filters. e
un de in
d GEN 9 supports full HW u n
accelerated video decoding for d ef
AVC/VC1/MPEG2/HEVC/VP8/
e d un
f in JPEG.
ne d
de fi in
e d
u
un Note: de
HEVC – 8 bitnsupport. f e
ed u n de e fin
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d
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un
d ef
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d
if n ed
de if n ed
un Table 2-10. e in
ndVideo Decoding
Hardware Accelerated ef
ed d
u d
unMaximum Resolution de
if n Codec
ne
Profile Level
de fi ed un
un MPEG2 de Main
Main
fin 1080p ed
un High
de fin
ed Advanced uL3n de
fi n
VC1/WMV9 Main
e d High 3840x3840 un
de Simple
fin Simple ed
un High de fin
ed AVC/H264 Main un L5.1 2160p(4K)de
fin MVC & stereo
ed un
d e VP8 f0in Unified level ed
un d e if n1080p
un Baseline e
ed
JPEG/MJPEG Unified level 16k x16k
d
fin HEVC/H265 ed Main L5.1 un 2160(4K) d
de if n e d un
un VP9* de 0 (4:2:0 Chroma 8-bit) Unified level fin ULX, 1080p 30fps @ 10Mbps
ULT, 4k 24fps @15Mbps
ed
n de in
d
u
un d ef
ne performance:
Expected
fi d un
de• fi
More than 16 simultaneous decode streams @ 1080p. ne ed
u n d e f in
Note: ed Actual performance depends on the u
n
processor SKU, content bit rate, and memory n de
ef
in frequency. Hardware decode for ed u
d f in H264 SVC is not supported. e d
un2.4.2.2 Hardware Accelerated n deVideo Encode e fin
ed u
dhigh-performance and low-power HW acceleration un
d
fin e
d e GEN 9 implements
f
a
in for multiple video codecs. e d for video un
un decoding e
operations i n e d
d u nd d ef f in
The HW d
e
encode is exposed by the graphics driver using
un the following APIs: n de
n
i Media SDK
• fIntel e d u
d e f in e d
un • MFT (Media Foundation Transform)nfilters de e fin
d
e GEN 9 supports full HW accelerateddvideo u encoding for AVC/MPEG2/HEVC/VP8/JPEG. d
fin e un
e f i n e d
nd 2-11. Hardware Accelerated Video
uTable de Encode fin
n e
ed d
u Profile nd Resolution
if n Codec
e Level u
Maximum

nde MPEG2 e fin Main High ned 1080p d


u
u d f i e
ed AVC/H264
un Main
L5.1 nd
e 2160p(4K) e fin
ed High
u
d level un
d
VP8 fin Unified profile e
Unified —

n de e fin — n ed
u
JPEG Baseline
d 16Kx16K
f i
e d HEVC/H265 Main un L5.1 2160p(4K)
n de
e fin VP9 ed
Support 8 bits 4:2:0 BT2020
n d
u
d may be obtained f i the pre/ — — e
un de in
ef
post processing
d u n d
e d SVC is not supported. un
f in Note: Hardware decode for H264
n e d
de ef
i
in
e d
u
un d f e
ed un n de e fin
e d u d
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n de e fin ned
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if n e u
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if n
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if n e d u
d e2.4.2.3 Hardware Accelerated f inVideo Processing e d
un n de e fin
e d There is hardware u
support for image processing functions
nd De-interlacing,
such as Film e
if n cadence detection, e d Advanced Video Scaler (AVS), detail u
enhancement, image nd
d e i n
stabilization,fgamut compression, HD adaptive contrast e d u
un enhancement, de total color control, Chroma de-noise, fSFC in enhancement,
pipe (Scalar and
skin tone
Format n ed
u n d e f i
Conversion),
e d de-noise,
spatial
memory compression, Localized Adaptive
Out-Of-Loop De-blocking (from
Contrast Enhancement (LACE),
unAVC decoder), 16 bpc support for de- n de
e
in
fnoise/de-mosaic. ned d
u
d f i e
un There is support for Hardware assisted n de Motion Estimation engine for AVC/MPEG2 e fin
ed encode, True Motion, and Image
u
d stabilization applications. un
d
f in e d
n de fin
The HW video processingeis exposed by the graphics driver using the i n efollowing APIs:
d
u
u n d
d ef
e • Direct3D* 9 Video API (DXVA2).
d un
fin • Direct3D 11 ne
Video API. d nd
d e f i e u
un de SDK.
• Intel Media fin ed
n
• MFTu(Media Foundation Transform) filters. nd
e f in
•ne
d
Intel CUI SDK. u nde
ef
i ed d
u
d f in e
Note:
un Not all features are supported by all the
documentation for more details. n de above APIs. Refer to the relevant efin
e d u d
fin e d un
n
e
d2.4.2.4 Hardware AcceleratedfTranscoding
e
in n ed
u f
d of decode video processing (optional)e and encode. Using i
e d Transcoding is a combination un d
fin the above hardware e dcapabilities can accomplish a high-performance un transcode pipeline.
d e in
There is not a dedicated
f API for transcoding. e d un
un e i n e d
d The processor
d
un graphics supports the following transcoding d ef features: f in
• in ed
Low-power and low-latency AVC encoder for
n
uvideo conferencing and Wireless n de
e d u
d ef Display applications. f in e d
un • Lossless memory compression fornmedia de engine to reduce media power. efin
e d u d
if n • HW assisted Advanced Videoed Scaler. un
de • Low power Scaler and Format ef
in Converter. ed
un d f in
ed Expected performance: un n de
in e d u
d ef • S-Processor fLine: in 18x 1080p30 RT (same as previousngeneration). e d u
u n d e f i e d
ed Note: un
Actual performance depends on Processor Line, video n deprocessing algorithms used, e fin
content edbit rate, and memory frequency. d
u
un
d
fin e
de fin n ed
2.4.3 unCamera Pipe Support d e f i
e d un n de
e fin Camera pipe functions such as de-mosaic,
n ed LGCA, white balance, defect pixel correction,
d
u black
level correction, gamma i
correction, vignette control, Front end Color
e Space
un
d
Converter (CSC), Image Enhancement d ef Color Processing (IECP). f in
ed un n de
in e d u
d ef fin e d u
un d e f in e d
ed un n de e fin
e d u d
fin e d un
n de e fin ned
u d f i
d 1 of 2
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ef
in ed d
u
d fin e
un n de e fin
ed u
un
d
fin ed
i e
def f in e d un
n de fin ed
un de if n
ed un n de
fin ed Interfaces
d
u
de if n e
un e in
un
d ef
ed un
d
if n ed
e
d2.4.4 Switchable/Hybrid i n
ef Graphics ed
un d f in
e d The processor supports unSwitchable/Hybrid graphics. nde e
f in e d u nd
d e Switchable graphics:f i n The Switchable Graphics feature allows
d
e you to switch between u
un using the n de integrated graphics and a discrete graphics
Intel e fin card. The Intel Integrated n ed
Graphicsudriver will control the switching betweennthe d modes. In most cases it will f i
operate e d as follows: when connected to AC poweru - Discrete graphic card; when n de
fi n d
eGraphics u
d e
connected to DC (battery) - Intel integrated
f i n e d
un Hybrid graphics: Intel integrated graphics n de and a discrete graphics card work efin
ed cooperatively to achieve enhanced
u
d power and performance. un
d
f in e
n de e fin n ed
Table 2-12. Switchable/Hybrid Graphics Support i
d
u
und d ef
e n
fin ed
2

e
Operating System
i n
Hybrid Graphics
d
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u nd
d f7 e 1
fin ed
Windows* N/A Yes
un n de 8.1 1 e i n
Windows*
u Yes
d N/A f
e dWindows* 10 Yes1 un N/A
nde
in d u
ef Contact your graphics vendor to check for support.fine
Note:
d e d
deWin8.1 or Win10. fin
1.
un2. Intel does not validate any SG configurationsnon e
d u nd
fi ne e d u
2.4.5 GEN 9 Video Analytics fin ed
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e d There is HW assist for video
un analytics filters such as scaling, convolve
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if n 1P filter, erode, dilate,
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n de 2.4.7 GT2 Graphics e fin Frequency n ed d
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e d The processor supports unsingle eDP* interface and 2 or 3 DDI interfaces n de (depends on e
f in segment): e d u nd
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def can be configured as DisplayPort* orfinHDMI*. ed
u n d e f i n
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e d DDI can support dual mode (DP++). un nde
e f•inEach DDI can support DVI (DVI maximum nedresolution is 1920x1200 @ 60 Hz). d u
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un • The DisplayPort* can be configured d eto use 1, 2, or 4 lanes depending on the fine
f
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d ef • DDI ports notated as: DDInB,
f i C, D. ed
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u • S-Processor Line processors
u nd supports eDP and up to 3 DDI supporting
d ef DP/HDMI.
e • AUX/DDC signals n
e fin n ed are valid for each DDI Port. (Three fordS-Processor u Line)
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d • Total Five e f i
dedicated HPD (Hot-plug detect signals) are evalid for all processor SKUs.
un n d e fin n ed
u d f i
Note: SSC is supported
e d in eDP*/DP for all Processor Lines.
un n de
n
• iDigital Display InterfaceDDI ports (B, C, and
ef resistor on following PCH signals: DDPB_CTRLDATA, ed D) are disabled if No Connect Pull-Upd u
d f in DDPC_CTRLDATA and e
un DDPD_CTRLDATA accordingly. nde e fin
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un
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n de • SW strap can override HW e finstrap. ned
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d Note: nd
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if n e u
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d
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d ef — eDP bifurcation for S-Processor Linefican ne be used for: DP x2 upper lanes (DDIE)ed
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fin e d un
n de The technologies supported by the
e fin processor are listed in the following table. n ed
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un Table 2-15. e in
nd (eDP*)/DDI Ports Availability
embedded DisplayPort* ef
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de
Ports
fi
Port name in VBT
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un
un e - eDP
dDDI0 fin ed
n
u DDI1
Port A
de Yes
fin
ed Port B un Yes de
fi n DDI2 Port C e
d Yes un
de f i n ed
un DDI3 e D
dPort Yes
fin
ed DDI4 - eDP
n
u Port E Yes1 de
fin Notes: ed un
nd
e 1. fin ed
Port E is bifurcated from eDP. When VGA is used, need to use available AUX (if HDMI is in used).
u a. de if n
For example, DT can use eDP_AUX for VGA converter which is available as free Design but HPD
n e
ed 2.
must be used as DDPE_HPD3.
u
3xDDC (DDPB, DDPC, DDPD) are valid for all processor SKUs).
un
d
fin 3. ed
5xHPD (PCH) inputs (eDP_HPD, DDPB_HPD0, DDPC_HPD1, DDPD_HPD2, DDPE_HPD3) are valid for all
un
d
de if n
processor SKUs. ed
un 4.
de
DDI3_AUX are exists as reserved. if n ed
5. n de
VBT provides a configuration option to select the four AUX channels A/B/C/D for a given port, based on in
u n
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ed d
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un d f in
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Tablee2-16. Display Technologies Support un de
in ed un
d ef Technology
fin Standard
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un e f i n
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nd
VESA* Embedded DisplayPort* Standard 1.3 e
if n
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uDisplayPort* Standard 1.2 u nd
e DisplayPort* 1.2 nVESA e PHY Compliance Test Specificationd
un
d f i VESA DisplayPort* n e 1.2
d
un e DisplayPort* Link Layer Compliance Test Specification
i 1.2
e
d HDMI* 1.4 un
d High-Definition Multimedia Interface Specification
1
d ef Version 1.4 f in
Notes: ed un n de
i n d
e chip connected to the DP* port. The LS-Pcon d u
d e1.f HDMI* 2.0 support is possible using LS-Pcon converter
supports 2 modes: f in e
un a.
b.
de
Level shifter for HDMI 1.4 resolutions.
DP-HDMI 2.0 protocol converter n for HDMI 2.0 resolutions. e fin
ed d
u
un
d
if n e d
de e fin ne
un d
• The HDMI* interfacensupports HDMI with 3D, 4Kx2K @24 Hz, Deep f i Color, and
e d x.v.Color. u n de
in e d u
d ef • The processor finsupports High-bandwidth Digital Content e dProtection (HDCP) for high u
u n definition d e
content playback over digital interfaces, f i
HDCP
n is not supported for eDP. e d
ed un
• Thedprocessor supports eDP* display authentication: n de Alternate Scrambler Seed e fin
u d
f ne (ASSR).
iReset e d un
n d•e The processor supports Multi-Stream eTransport fin (MST), enabling multiple monitors n ed
u d f i
e d
The maximum MST DP supported
uresolution for S-Processor Line is shownnindethe
to be used via a single DisplayPortnconnector.

e fin following table. n ed d


u
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Datasheet, Volume
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def f in ed un
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un de if n
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fin ed Interfaces
d
u
de if n e
un e in
un
d ef
ed un
d
if n ed d
de if n ne
un Table 2-17. e i
Display Resolutions n
and ef
d Link Bandwidth for Multi-Stream Transport
ed Calculations u nd
de
if n ed u
dPixel Clock un
de fin Refresh e Link
un e per line
dPixels Lines
Rate [Hz] fin [MHz] Bandwidth
ed
un de [Gbps]
fin
ed 640 480 60un 25.2 0.76 de
fi n 800 600 d
e 60 40 1.20 un
de fin 60 ed
fin
1024 768 65 1.95
un
1280 720 n
de 60 74.25 e
2.23
ed u d
un 2.05
fin 1280
ed768 60 68.25

de 1360
fin 768 60 85.5 ed 2.57
un 1280 de 1024 60 108 if n 3.24
un e
ed 1400 1050 60 nd
101 3.03
fin ed u119
un
d
if n ed
1680 1050 60 3.57
de
un de 1920 1080 60 if n 148.5 4.46
ed
n de in
u 1920 1200 60
n
154 4.62
ef
ed 2048 1152
d
60 u 156.75 4.70
un
d
if n 2048 1280
ne60 174.25 5.23
d e
ef
i ed
un
2048 1536
d
60 209.25 6.28
f in
1440 n e
ed
2304 60 218.75
u n d6.56
if n 2560
e d
1440 60 241.5 u 7.25
nd
e 3840 fin 2160 30 262.75
ned 7.88
u 2560
n de 1600 60 268.5
e f i 8.06
ed 2880 u 1800 60 nd
337.5 10.13
fin ed u
un
de
3200
f in 2400 60
ed497.75 14.93

un d e3840 2160 60
fin 533.25 16.00 ed
d un 4096 2160 60 de 556.75 17.02 if n
un e
ed 4096 2304 60 605 18.15
un
d
if n Notes: ed
d e 1. All above is related to bit depth of 24. f in ed
un 2. de
The data rate for a given video mode can be calculated as: Data Rate = Pixel Frequency * Bit if n
ed Depth.
u n
n de
if n ed
3. The bandwidth requirements for a given video mode can be calculated as: Bandwidth = Data
Rate * 1.25 (for 8B/10B coding overhead). u
de 4. if n
The Table above is partial List of the common Display resolutions just for example. ed
un e in
nd
The Link Bandwidth depends if the standards is Reduced Blanking or not.
ef
ed d
If the Standard is Not reduced blanking - the expected Bandwidth will be higher.
u
un
ed
For more details refer to VESA and Industry Standards and Guidelines for Computer Display
if n Monitor Timing (DMT). Version 1.0, Rev. 13 February 8, 2013
d e if n ed
To calculate what are the resolutions that can be supported in MST configurations, follow the u
un nd
e
below guidelines: f in ed
ed u a. de
Identify what is the Link Bandwidth (column right) according the requested Display if n
ed
resolution.
un de
fin
b. Summarize the Bandwidth for Two of three Displays accordingly, and make sure the
ed
final result is below 21.6Gbps. (for HBR2, four lanes) un
d e c.
fin
For special cases when x2 lanes are used or HBR or RBR used , refer to the tables in ed
un 5.
Section 2.5.11 accordingly.
For examples: de fin
ed a. un
Docking Two displays: 3840x2160@60hz + 1920x1200@60hz = 16 + 4.62 = de
fin 20.62Gbps [Supported]
ed un
d e b.
if n
Docking Three Displays : 3840x2160@30hz + 3840x2160@30hz + 1920x1080@60hz =
7.88 + 7.88 + 4.16 = 19.92Gbps [Supported] ed
un 6. de
Consider also the supported resolutions as mentioned in Section 2.5.6 and Section 2.5.7. if n
ed un nde
f in ed u
de if n ed d
u
un • The processoresupports only 3 streaming independent and in simultaneous display ne
d
un of DisplayPort*/eDP*/HDMI*/DVI monitors.
combinations ef In the case where 4 i
ed n d
d are plugged in, the software policy will udetermine
monitors which 3 will be used. def
e un
fin ed
nd
e fin ed
e f in
u nd e
38
ed u d
Datasheet, Volume 1 of 2