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PFC Controller Design

iL
is  L 
d

vs vs Vd
 Cd
iL R
 
Voltage Control Loop iL
(measured)
sintt
sin Current Control Loop
Vd*  IˆL* iL*   vc
 
Voltage Current q( t )
Controller Controller

Vd (measured)  IˆL* sin(t ) vr

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DESIGNING INNER AVERAGE-CURRENT-CONTROL LOOP

iL* (t) vd
vc (t) d (t ) Power
Current PWM
Controller IC Stage
iL

(a)
Current PWM Power
Controller IC Stage
iL* (s) vc (s) 1 d(s) Vd iL (s)
 Gi (s)
Vˆr sLd

(b)

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Why?

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DESIGNING INNER AVERAGE-CURRENT-CONTROL LOOP
iL* (t ) vd
vc (t ) d (t ) Power
Current PWM
Controller IC Stage
iL

(a)
Current PWM Power
Controller IC Stage
vc ( s )  iL ( s )
iL* ( s )  1 d (s) Vd
 Gi ( s )
Vˆr sLd

(b)

d ( s ) 1 k c 1  s / z
PWM-IC:  Controller: Gi ( s ) 
vc ( s ) Vˆr s 1  s / p
 
iL ( s ) Vd  phase boost
Power-Stage:  K boost  tan(45o  boost )

d ( s ) sLd 2
f ci
fz  f p  K boost f ci k c   z GC ( s ) fc
K boost
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DESIGNING THE OUTER VOLTAGE LOOP
Vd*
IˆL* Closed IˆL vd
Voltage Power
Controller Current Stage
( a) Loop

Closed
Voltage Current Power
Controller Loop Stage
v *d (s )  0 iL* ( s ) iL (s ) vd (s )
1 Vˆs

R/ 2
( b) Gv ( s) 1 2 Vd 1  s( R /2)C
kv 
Gv ( s )  
1  s / cv

kv 1 Vˆs R/2
1
1  s / cv 2 Vd 1  s ( R / 2)C s  j (2  f cv )

kv IˆL 2 IˆL 2
  1.5%
1  s / cv s  j (2 120)
Vˆd 2 ˆI
L

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kv
Gv ( s ) 
1  s / cv
C1

R1 R2 R1
in 
R1

out

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PSpice Modeling:

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Simulation Results
250

200

150

100

50

0
0s 20ms 40ms 60ms 80ms 100ms 120ms 140ms 160ms 180ms 200ms
V(R2:2) I(L1)*50
Time

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PSpice Switching Circuit Modeling:

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Simulation Results

3.0A

2.0A

1.0A

0A
I(L1)
250V

225V

200V

175V
SEL>>
150V
0s 20ms 40ms 60ms 80ms 100ms 120ms 140ms 160ms 180ms 200ms
V(U3:1)
Time

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FEEDFORWARD OF THE INPUT VOLTAGE

sin  t
Current Loop
*
Vd
Voltage N IˆL* iL* (t )
vc (t ) vd
Controller Current q (t )
Controller Power
D Stage
Vˆs
vr iL
Vˆs ,nom

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Summary

• PFC Controller Design

© Copyright Ned Mohan 2010 12