UNIT 8 TTL AND CMOS COMPARISON

A TTL logic gate is configured with

b. bipolar transistors.
A CMOS logic gate is configured with
a. field-effect transistors (FETs).
If the circuit you are designing had to be compact and immune to noise, you woul
d use
b. CMOS logic gates.
The positive supply voltage and negative supply voltage for a CMOS gate are
b. VDD and VSS, respectively.
When the input to a TTL or CMOS gate is greater than VIH, the input is in a(n)
c. logic 1 state.
When a 7407 TTL buffer has an input voltage of 0.7 Vdc, the input is in a(n)
a. logic 0 state.
When the input voltage for a 4069UB CMOS gate with VDD at 15 Vdc is 10 Vdc, the
input is in
a(n)
b. uncertain logic state.
Does a TTL gate or a CMOS gate have high noise immunity and lower power consumpt
ion?
b. CMOS
Nominal Answer: 200.0
Nominal Answer: 5.0
Nominal Answer: 1.4
10. Is the measured value of the input voltage (# V1# Vdc) when the output switc
hed to high
greater than VIL (0.8 Vdc) and less than VIH (2.0 Vdc)?
a. yes
Nominal Answer: 5.0
Nominal Answer: 1.4
13. A
Nominal Answer: 2.5
20. Is the measured value of the input voltage (#V3# Vdc) when the output switch
ed to high
greater than VIL (1.0 Vdc) and less than VIH (4.0 Vdc)?
a. yes
Nominal Answer: 5.0
Nominal Answer: 2.5
23. A
Nominal Answer: 1.4
Nominal Answer: 15.0
Nominal Answer: 15.0
1. C
2. D
3. C
4. C
5. A
Exercise 2 TTL and CMOS Dynamic Characteristics
The tPLH of a gate is 20 ns. This means that the
a. rising output of a gate takes 20 billionths of a second to respond to an inpu
t change.
Transition time is between
b. 10% and 90% of the maximum output voltage.
What is the output high-to-low propagation delay of a CMOS (4069UB) with a suppl
y voltage
(VDD) of 15 Vdc?
c. 30 ns
4. b
Nominal Answer: 290.0
Nominal Answer: 130.0
Nominal Answer: 155.0
Nominal Answer: 130.0
1. b
2. a
3. d
4. c
5. c
UNIT TEST
A CMOS logic gate
c. is constructed of field-effect transistors.
Compared to a CMOS logic gate, a TTL logic gate
d. All of the above.
A TTL buffer has a VIL of 0.8 Vdc and a VIH of 2.0 Vdc.
a. The output will change state when the input voltage is between 0.8 Vdc and 2.
0 Vdc.
A CMOS gate has better noise immunity than a TTL gate does because in a CMOS gat
e,
b. the difference between VIL and VIH is greater.
When a TTL gate drives a CMOS gate,
d. the TTL gate must have an open collector output pulled up to the VDD of the C
MOS
gate.
The tTHL of a gate is 80 ns. On the above timing diagram, the 80 ns is between t
he signal points
represented by
c. C.
The tPLH of a gate is 30 ns. On the above timing diagram, the 30 ns is between t
he signal points
represented by
b. B.
A signal transition time (rise or fall time) is measured between the
d. 10% and 90% points of a low-to-high or a high-to-low signal.
The positive and negative power supplies of a CMOS gate are, respectively,
c. VDD and VSS.
A CMOS gate
d. is more sensitive to static electricity than a TTL gate is.