2.

2 BLOCK DIAGRAM OF 89C51

P 0 .0 to P 0 .7 P 2 .0 to P 2 .7

P o r to D r iv e r P o r to 2 D r iv e r

RAM ADDR P o rto Q u ic k

RAM L a tc h F la s h
R e g is te r

P ro g ra m
B r e g is te r ACC S ta c k a d d re s s
P o in te r r e g is te r

TM P2 TM P1
B u ffe r

PC
ALU
In c r e -
IN T , S e r ia l P o r t, m ent
PSW & T im e r B lo c k s
P ro g
PSEN C o u n te r
ALE / PROG T im in g IN S T
& Reg
EA /VPP DPTR
C o n tro l
RST
P o r t1 P o rt3
L a tc h L a tc h

O SC P o r t1 D riv e r P o r t3 D r iv e r

P 1 .0 to P 1 .7 P 3 .0 to P 3 .7
 2.3 FEATURES

1. Compatible with MCS-51TM Products.

2. 8K byte of in system re-programmable flash memory.

3. Endurance: 1000 write / Erase cycle.

4. Fully static operation.

5. 3 Level program memorial clocks.

6. 256 X 8 bit internal RAM.

7. 32 programmable I/O Line.

8. 3-16 bit timer/Counter.

9. 8-Interupt Source.

10. Programmable serial channel.

11. Low power, Ideal and Power down modes.

12. Four register Banks each containing 8 registers

 2.4 PIN CONFIGARATION OF 89C51 :

(T 2) P 1 .0 . 1 40 VCC

T 2 (E x ) P 1 .1 2 39 P 0 .0 (A D 0)
P 1 .2 3 A 38 P 0 .1 (A D 1)

T
P 1 .3 4 37 P 0 .2 (A D 2)

P 1 .4 5 36 P 0 .3 (A D 3)

P 1 .5 6
M 35 P 0 .4 (A D 4)

P 1 .6 7 34 P 0 .5 (A D 5)

P 1 .7 8 E 33 P 0 .6 (A D 6)

L
RST 9 32 P 0 .7 (A D 7)

(R XD ) P 3 .0 31 EA /VPP

(T XD ) P 3 .1 11
8 ALE / PRO G

(IN T O ) P 3 .2 12 29 PSEN

(IN T 1 ) P 3 .3 . 13 9 28 P 2 .1 (A 15)

C
(T 0) P 3 .4 14 27 P 2 .6 (A 14)

(T 1) P 3 .5 15 26 P 2 .5 (A 13)

(W R ) P 3 .6 16
5 25 P 2 .4 (A 12)

(R D ) P 3 .7 17 24 P 2 .3 (A 11)

X TA L 2 18 2 23 P 2 .2 (A 10)

X TA L 1 19 22 P 2 .1 (A 9)

G ND 20 21 P 2 .0 (A 8)
 2.5 PIN DESCRIPTION OF 89C51

PORT O: Port O is an 8 bit open drain bi-directional I/O port. Each pin
can sink 8 TTL I/P’s. It can be configured to be multiplexed low order
Address / Data bus during access to external program and data memory.
When a pin is to be used as an I/P, a 1 must be written to a
corresponding port O latch by the program, thus turning both of the
transistor OFF, which in turn causes the pin to float in high impedance
state, and the pin is connected to I/P buffer. When used as an O/P the
pin latches that are programmed to a 0 will turn ON the lower FET
grounding the pin. All latches that are programmed to a 1 still float; thus,
external pull-up resistors will be needed to supply a logic high when using
port O as an O/p.

Port O also receives the code bytes during flash programming and
O/P’s the code bytes during program verification.

Port 1 : Port 1 is an 8-bit bi-directional I/O port with internal pull-ups.

The port 1 O/P buffers can sink/source four TTL I/P’s. When 1’s are
written to port 1 pin, they are pulled high by internal pull-ups and can be
used as I/P’s. Port 1 pins that are externally being pulled low will source
current in because of the internal pull-ups.

In addition port 1.0 and port 1.1 can be configured to be the

timer/counter 2 external count I/P’s (P1.0/t2) and the timer counter 2
trigger I/P (P1.1/T2(Ex)) respectively.

Port 2 : Port 2 may be used as an input/output similar in operation to

port 1. Port 2 emits the high order address byte during fetches from
external program memory and during accesses to external data memory
that use 16 bit addresses. In this application, Port 2 uses strong internal
pull-ups. When emitting 1’s. During excesses to external data memory
that 8 bit address, Port 2 emits the contents of the P2 Special function
Register.

Port 2 also receiveres the high order address bits and some control
signals during flash programming and verification.

Port 3 : Port 3 is an input/output port similar to port 1. The input and

output functions can be programmed under the control of the P3 latches
or under the control of various other special function registers. The port 3
alternate uses are shown in the following table.

Port Pin Alternate Function

P3.0 - RXD - Serial data input
P3.1 - TXD - Serial data output
P3.2 - INTO - External Inter Pt O
P3.3 - INT1 - External Inter Pt 1
P3.4 - TO - External Timer O I/P
P3.5 - T1 - External Timer 1 I/P
P3.6 - WR - External Data Memory write pulse
P3.7 - RD - External data Memory Read pulse

Unlike port O and 2, which can have external addressing functions

and change all eight port bit when in alternate use, each pin of Port 3 may
be individually programmed to be used either as I/O or as one of the
alternate functions.

Reset: A Reset can be considered to be the ultimate interrupt because the

program may not block the action of the voltage on the RST pin. This type
of interrupt is often called non-maskable because no combination of bits
in any register can stop or mask, the reset action.

A reset is an absolute command to jump to program address 0000h

and commence running from there. When ever a high level is applied to
the RST pin the 89C52 enters a reset condition.

ALE /PROG: Address latch enable is an O/p pulse for latching the low
byte of the addressing during accesses to external memory. This pin is
also the program pulse I/p (PROG) during flash programming.

In normal operation, ALE is emitted at a constant rate of 1/6 the

oscillator frequency and may be used for external timing or clocking
purposes. However that one ALE pulse is skipped during each access to
external data memory.

PSEN : Program store enable is the read strobe to external program

memory. When the 89C52 is executing code from external program
memory. PSEN is activated twice each machine cycle, except that two
PSEN activation’s are skipped during each access to external data
memory.

EA/VPP : External access enable. EA must be strapped to ground in order

to enable the device to fetch code from external program memory location
starting at 0000H up to FFFFH. However that if lock bit 1 is programmed.
EA will be internally latched on Reset. EA should be strapped to Vcc for
internal program executions. Bit EA is a master or global bit that can
enable or disable all of the interrupts.

This pin also receives the 12 volt programming enable voltage VPP
during flash programming when 12 volt programming is selected.

T0 and T1 : Counters and Timers : Timers 0 and 1 :

Many Microcontroller applications require the counting of external event,
such as the frequency of pulse train, or the generation of precise internal
time delays between computer action. Both of these task on be
accomplished using software techniques, but software loops for counting
or timing keep the processor occupied so that other, perhaps more
important, functions are not done. To relive the processor of this burden,
two 16 bit up counters, named T0 and T1 are provided for general use of
the programmer. Each counter may be programmed to count internal
clock pulses, acting as timer or programmed to count external pulse as a
counter.

The counters are divided into two 8 bit registers called the timer low
TL0 , TL1 and high TH0, TH1 bytes. All counter action is controlled by bit
states in the timer mod control register TMOD, the timer/counter control
register TCON and certain program instructions.

Timer 2: Timer 2 is a 16 bit timer/counter that can operate as either a

timer or an event counter. The type of operation is selected by bit CT12 in
the SFR’s T2CON.

TIMER 2 HAS 3 OPERATING MODES:

1) Capture mode 2) Auto reload mode 3) Baud rate generator mode.

The modes are selected by bits in T2CON Timer 2 Consists of two 8 bit
registers TH 2 and TL2. In the timer function, the TL2 register is
incremented every machine cycle. Since a machine cycle consists of 12
oscillator’s period, the count rate is 1/12 of the oscillator frequency.

XTALI and XTAL2:

The heart of the 89C52 is the circuitary that generates the clock pulses by
which all internal operations are synchronized. Pins XTALI and XTAL2 are
provided for connecting a resonant network to form an Oscillator. The
Crystal frequency is the basic internal clock frequency of the
microcontroller. The manufacturers make available 89C52 designs that
can run at specified maximum and minimum frequencies. Typically 1MHz
to16 MHz . Minimum frequency imply that some internal memories are
dynamic must always operate above a minimum frequency or data will be
lost.

C = 82 P F
18 X TA L 2

C ry s ta l
1 1 .0 5 9 2

19 X TA L 1
C = 82 P F

Typically, a Quartz Crystal of frequency 11.059MHz and capacitors are

employed as shown in figure. Here 1 machine cycle consists of 6 T-states
and each T-state is of 2 pulses.

To calculate the time for any particular instruction is

Given by: Tints = Cx12d

crystal frequency

Where C-Machine cycle of the instruction.

Consider a 1 byte instruction. If the crystal frequency is 11.0592 MHz

then the time to execute one byte instruction is 1.0850  sec.
 2.6 SFR & INTERRUPTS

We have seen earlier that many times, processor has to respond to

event happening in the real time world. The event may take place at any
time. Interrupt handling logic is incorporated inside the chip, for this
purpose. In such a case, processor will suspend current execution of the
program, and branch to interrupt service routine. After finishing, he will
resume the suspended work. The situation can be seen
very frequently, in our every day life. Suppose a person is busy in doing
some work, say writing a letter and call of a sudden telephone bell rings.
Then the person will stop writing the book, answer the telephone, and
resume the writing the book. Some time there are 4, 5 telephone lines are
available. In that case he may have to decide about the priority, in
answering the phones. Some time he himself is very busy in important
meeting, and does not want to get disturbed by the phone calls. All these
types of situation exist in microprocessor world also.
 Those of you who are familiar with 8085 will recall that 8085 can
handle 5 different interrupts. 89C52 can also respond to 5 different
interrupting lines, equivalent of having 5 telephone lines. Two are external
interrupts they are called INT0, INT1 at Port pin P3.2 and P3.3
respectively. If these interrupts are activated and enable in software the
program will branch to location 0003 and 0013Hex of program memory
(ROM).

89C52 have two Timers/Counter modules. These counters are UP

counters only. When counting starts, during the course of counting
whenever they overflow from FFFF to 0000, Timer overflow flag TF0 or TF1
is set and interrupts are generate. If the interrupts are enabled in software
then the program will branch to location 000B and 001B Hex respectively.

89C52 has built in serial interface. Whenever serial data is received,

Receipt Interrupt (RI) bit is set. Whenever data is fully shifted out Transmit
Interrupt (TI) bit is set. The RI and TI together generates one interrupt called
Serial Interrupt. If this interrupt is enabled in software then the program will
branch to location 0023 Hex in ROM memory. The interrupt handling logic of
89C52 can be explained with the help of next figure.
 The external interrupt INT0 and INT1 can be defined as either Negative
Edge Triggered or Level Triggered. This means, if interrupt is defined as
Negative Edge Triggered, interrupt will be generated whenever negative
edge is detected on INT0 or INT1 line, or if interrupt is defined as Level
Triggered, then interrupt is active as long as INT0 or INT1 is held low. The
bits IT0 (Interrupt Type Zero) and IT1 (Interrupt Type One) will decide
whether the interrupt is defined as edge triggered or level triggered. If the
bit is 0 then corresponding interrupt is level triggered and if the bit is 1
then it is edge triggered. These bits are found in TCON register, in the SFR
area of the internal RAM and it’s address is 88 Hex.

• Interrupt Enable Register (IE)

The bits in the register IE will decide, which interrupts are active or
enabled. The MS Bit of the IE register is the global enable bit, labeled as
EA. If this bit is 1 means interrupts are enabled, otherwise all interrupts
are disabled. Other bits in the IE register will enable, if they are 1 or
disable if they are 0, the individual interrupts. The IE has a place in SFR
area and its address is A8 Hex. It is a Bit Addressable Register. The next
fig. gives idea of IE.

IE : Interrupt Enable Register

EA : Global interrupt enable.

--- : Reserved.

ES : Serial interface.

ET1 : Timer 1.
EX1 : External Interrupt 1.

ET0 : Timer 0.

EX0 : External interrupt0.

0=Disabled.
1= Enabled
 There is a provision to decide the priority of the interrupt, either High
or Low. If lower priority interrupt work is in progress, and higher priority
interrupt arrives. Then lower priority interrupt work will be suspended,
processor will branch to higher priority service routine. After finishing
higher priority work, it will resume the execution of lower priority
interrupt. After finishing execution of lower priority interrupt, the
processor will go back to start the execution of main program. If higher
priority interrupt is in progress and lower priority interrupt arrives then
lower priority interrupt will be kept pending till the execution of higher
priority interrupt ends. After finishing higher priority interrupt processor
will start the execution of lower priority interrupt. After finishing the same,
processor will go back to main program. The address of the register is B8
Hex in the SFR area. It is a Bit Addressable Register. The next fig. gives
idea of IP.

• Interrupt Priority Register (IP)

 As was mentioned earlier INT0 or INT1 pins will activate the interrupt
in two ways. Interrupt can be defined as edge triggered or level triggered.
IE0 or IE1 are the two bits, which actually causes the interrupts. If
interrupts are defined as level triggered then bits IE0 or IE1 will remain
set as long as pins INT0 or INT1 are low. If they are defined as level
triggered and activated then program will branch to the respective vector
address in ROM and will start the execution of the service routine. It is
then hardware’s and / or programs responsibility to see that pin, INT0 or
INT1, who has caused the interrupt, goes high so that bit IE0 or IE1 will
be cleared. If INT0 or INT1 is not cleared then program will again enter
into the same service routine. Mostly these interrupts are defined as edge
triggered mode only. If they are defined as edge triggered, then the bit IE0
or IE1 will be set whenever negative edge is detected, and the bits will
automatically get cleared, when program branches to respective interrupt
service vector.

Timer overflow bit TF0 or TF1 will set, whenever counter overflows
from FFFF Hex to 0000 Hex. They will automatically get cleared, when
program branches to respective interrupt service routine.

The bits RI and TI in the serial interface logic will be ORed and will
generate one common interrupt. If these interrupts are enabled, then
program will start execution at ROM address 0023 Hex. These bits will not
get cleared automatically. Program will find who has caused the interrupt.
Then will take the appropriate action and program will clear the bit. The bits
TI and RI are found in Serial Control Register (SCON). The register SCON is
found at address 98 Hex in the SFR area.