FPGA Implementation of QRD-RLS Algorithm with Embedded Nios Soft Processor
Deepak Boppana Kully Dhanoa
Altera Corporation Altera Corporation
101 Innovation Dr Holmers Farm Way
San Jose, USA High Wycombe, UK
408-544-7887 1494-602-000
dboppana@altera.com kdhanoa@altera.com
I. INTRODUCTION
Adaptive signal processing algorithms such as
least mean squares (LMSs), normalized LMSs
(NLMSs), and recursive least squares (RLSs)
have been historically used in numerous wireless
applications such as equalization, beamforming,
and adaptive filtering (Figures 1 and 2). With the
advent of wideband 3G wireless systems,
adaptive weight calculation algorithms are also
being considered for new applications, such as
polynomial-based digital predistortion and multi-
in/multi-out (MIMO) antenna solutions (Figure
3). These applications generally involve solving
for an over-specified set of equations, as shown
below where m > N.
x1 (1) c 0 + x 2 (1) c1 + ....... x N (1) c N = y (1) + e (1 )
x1 ( 2 ) c 0 + x 2 ( 2 ) c1 + ....... x N ( 2 ) c N = y ( 2 ) + e ( 2 )
M fabric. Figure 1 gives an outline of the proposed
x1 ( m ) c 0 + x 2 ( m ) c1 + ....... x N ( m ) c N = y ( m ) + e ( m )
Among the different algorithms, the recursive
least squares algorithm is generally preferred for
its fast convergence property. The least squares
approach attempts to find the set of coefficients
c n that minimizes the sum of squares of the
errors, i.e., {min ∑ e ( m) 2 }. Representing the
m Multiply CI
above set of equations in the matrix form, we
have:
Xc = y + e (1)
where X is a matrix (mxN, with m>N) of noisy
observations, y is a known training sequence,
and c is the coefficient vector to be computed
such that the error vector e is minimized.
Direct computation of the coefficient vector c
involves matrix inversion, which is generally
undesirable for hardware implementation. Matrix
decomposition, based least squares schemes,
such as Cholesky, LU, SVD and QR-
decompositions, avoid explicit matrix inversions
and are more robust and well-suited for hardware
implementation (Figure 1). Such schemes are
CF-QRD031505-1.0
Jesse Kempa
Altera Corporation
101 Innovation Dr
San Jose, USA
408-544-8520
jkempa@altera.com
increasingly being considered for high sample
rate applications, such as digital predistortion,
beamforming and MIMO signal processing.
FPGAs are the preferred hardware platform for
such applications because of their capability to
deliver enormous signal processing bandwidth.
In recent years, FPGAs have become available
with increasingly powerful embedded soft
processor cores that give designers the flexibility
and portability of high-level software design,
while maintaining the performance benefits of
parallel hardware operations in FPGAs (Figure
4).
The rest of this paper describes the proposed
implementation of the QR-decomposition-based
RLS algorithm (QRD-RLS) on Altera’s
Stratix® FPGA with embedded Nios® soft
processor technology and the Avalon™ switch
implementation of the QRD-RLS algorithm
using the concept of custom peripherals and
custom instructions.
Avalon
CORDIC
Accelerator
N i os Program
& Data
Divide CI Memory
Figure 1. Nios processor-based QRD-RLS
implementation
II. OVERVIEW OF QRD-RLS ALGORITHM
As described earlier, the least squares
algorithm attempts to solve for the coefficient
vector c from X and y. To realize this, the QR-
decomposition algorithm is first used to
transform the matrix X into an upper triangular
matrix R (NxN matrix) and the vector y into
another vector u such that Rc=u. The
coefficients vector c is then computed using a
procedure called back substitution, which
involves solving the equations shown below. x1(2) x2(2) x3(2) x4(2) xN(2) y(2)
uN x1(1) x2(1) x3(1) x4(1) xN(1) y(1)
cN = (2)
R NN

f
o
r
i
N
-
1
,
.
.
.
1
1 ⎛ N ⎞ R11 R12 R13 R14 R1N u1
ci = ⎜ui − ∑ R ij c j ⎟ = (3)
R ii ⎜ ⎟
⎝ j = i +1 ⎠
R22 R23 R24 R2N u2
The QRD-RLS algorithm flow is depicted
below in Figure 2. R33 R34 R3N u3
Vectoring mode
X R
QR Back c R44 R4N u4
y Decomposition u Substitution
Rotating mode
RNN UN
Figure 2. QR decomposition based least squares

III. CORDIC-BASED QR-DECOMPOSITION

The QR-decomposition of the input matrix X Fig. 3. Systolic array architecture for QR Decomposition
can be performed, as illustrated in Figure 3,
using the well-known systolic array architecture results obtained were achieved using Altera’s
[5]. The rows of matrix X are fed as inputs to the Quartus® II push-button flow on its Stratix
array from the top along with the corresponding devices. As the input-bit width increases, the
element of the vector y. The R and u values held resource consumption also increases, whereas
in each of the cells once all the inputs have been the fMAX decreases.
passed through the matrix, are the outputs from Table 1. Altera Cordic Resource Consumption
QR-decomposition. These values are Input Number of Logic fMAX (MHz)
subsequently used to derive the coefficients Width Iterations Elements
using the back-substitution technique. (bits) (LEs)
8 8 380 264
Each of the cells in the array can be 16 16 1,300 219
implemented as a coordinate-rotation digital 24 24 2,670 198
computer (CORDIC) block. CORDIC describes 32 32 4,600 189
a method to perform a number of functions, 40 40 7,010 163
including trigonometric, hyperbolic and
logarithmic functions [6]. The algorithm is Direct mapping of the CORDIC blocks onto
iterative, and uses only additions, subtractions the systolic array shown in Figure 3 consumes a
and shift operations. This makes it very significant number of LEs and yields enormous
attractive for hardware implementations. The throughput that is generally not required for
number of iterations depends on the precision many applications. The resources required to
required, which correlates directly with the implement the array can be reduced by trading
amount of bits needed. throughput for resource consumption via mixed
Altera’s CORDIC blocks have a deeply and discrete mapping schemes.
pipelined parallel architecture enabling speeds Mixed mapping: In mixed mapping schemes,
over 250 MHz on Stratix FPGAs in both the bottom rows in the systolic array are moved
vectoring and rotating modes. For real inputs, to the end of the top rows, to ensure the same
only one CORDIC block is required per cell. number of cells in each row. A single CORDIC
Many applications involve complex inputs and block can then be used to perform the operations
outputs to the algorithm, for which three of all the cells in a row, with the total number of
CORDIC blocks are required per cell. In such CORDIC blocks required being equal to the total
cases, a single CORDIC block can be efficiently number of rows. Because each CORDIC block
timeshared to perform the complex operations. has to operate in both vectorise and rotating
Table 1 illustrates the resource consumption modes, the scheme is called mixed mapping [7]
for the CORDIC algorithm in terms of logic Discrete mapping: In this scheme, at least two
elements (LEs) for different input bit widths. The CORDIC blocks are required. One block is used
purely for vectorise operations, while the other is
used for rotate operations [8]. This single
functionality of the processors allows any gains
from hardware optimisation to be realized.
Further information on the different mapping
schemes can be found in references [7], [8], and
[9]. An example resource estimation of direct,
mixed, and discrete mapping schemes is
presented in Section V.
IV. BACK SUBSTITUTION ON NIOS SOFT PROCESSOR
As outlined in Section II, the final coefficient
weight vector is derived from the outputs of the
QR-decomposition algorithm using a procedure
called back substitution. The back substitution
procedure, as seen in Figures 2 and 3, primarily
involves multiplication and division operations.
The Nios embedded soft processor, with its
custom multiply and divide instructions, is an
ideal fit to implement this function.
The Nios processor is based on the
revolutionary concept of embedding soft RISC
processors within FPGAs and can operate at over
100 MHz on Stratix FPGAs [10]. Embedded
designers can create custom processor-based
systems using Altera’s SOPC Builder system
development tool. SOPC Builder can be used to
integrate one or more configurable Nios
processor with any number of standard
peripherals, gluing the system together with the
automatically generated Avalon switch fabric.
Figure 4 outlines the procedure involved in
computing the coefficients via back substitution.
Nios CPU
I D
Avalon Bus
Program I/ Rr ur
O
& Data
Memory
Ri ui
CORDIC
Figure 4. Nios processor for back substitution
The CORDIC block performs the QR-
decomposition and stores the R and u values
(real and imaginary) in memory accessible to the
Nios processor, which then calculates the real
and imaginary coefficient values and stores the
results back into memory.
A 32-bit Nios CPU can optionally be
configured to include a hardware 16x16 –> 32
integer multiplier implemented using the digital
signal processing (DSP) blocks on Stratix
FPGAs. The MUL instruction can then be used to
complete the multiply operation in a single clock
cycle. The divide operation can be implemented
as a custom logic block that becomes a part of
the Nios processor’s arithmetic logic unit (ALU)
as shown below in Figure 5. The 32-bit division
can then be completed in approximately 35 clock
cycles by the Nios processor operating at
100 MHz. The Nios configuration wizard creates
software macros in C/C++ and assembly,
providing software access to the custom logic
block. The back substitution operation can thus
be efficiently implemented using hardware
accelerated code on the Nios processor, as
observed in the simulation results in the next
section.
cr Figure 5. Adding custom logic to the Nios ALU
V. RESOURCE ESTIMATES & SIMULATION RESULTS
ci
Table 2 gives an overview of the resource
estimates for performing the CORDIC-based
QR-decomposition using the three different
mapping schemes described in Section III. An
example scenario of m=64 and N=9 with 16-bit
complex inputs to the CORDIC is considered.
The system clock is assumed to be at 150MHz
with a single CORDIC block timesharing the
three operations required for complex inputs.
The estimates do not include the resources
required for scheduling operations between
the different CORDIC blocks.
1000000
Table 2. Resource Estimates Example for Different CORDIC Blocks

Some new terms are defined as follows.

Update Delay: Time required before all cells in
systolic array are updated with their R and z
values
Throughput: Number of input matrices (each m
Implementation CORDIC Throughput Cost
Technique Usage
No. of No. of Update Updates LE/Upd
Blocks LEs Delay per ate
(us) Second
Direct Mapping 54 70200 5.1 196078 1.497
Mixed Mapping 4 5200 250.85 3986 1.305
Discrete Mapping 2 2600 198.11 5047 0.515

x N) that are processed per second = 1/update

delay.
Cost: Number of LEs consumed per update
As seen in Table 2, direct mapping offers the
highest throughput (update/s) but at the expense
of fifty-four CORDIC blocks, which requires a
huge number of LEs. In almost all applications,
the cost of these logic resources would make this
implementation unviable. Mixed mapping
reduces the resource consumption by employing
only four CORDIC blocks with a corresponding
drop in throughput. In comparison, although the
discrete mapping scheme needs five CORDIC
blocks, it can be implemented using only two
blocks. Because Altera’s CORDIC block is
iterative and pipelined, the number of blocks can
be reduced from five to two with only a three-
clock cycle delay penalty (i.e., one extra clock
cycle for each timeshared CORDIC operation).
This not only further reduces the resource
consumption, but also provides higher
throughput than mixed mapping scheme.
The discrete mapping scheme, therefore, best
exploits the pipelining ability of Altera’s
CORDIC block and offers the optimum tradeoff
between resource consumption and throughput.
Figure 6 illustrates the number of clock cycles
required for the Nios processor, operating at
100 MHz, to calculate different numbers of
complex coefficients. The back-substitution
subroutine written in C code calculates the
coefficient array and stores it into memory. The
subroutine assumes that all complex arrays are
stored as short (signed 16-bit precision) and all
complex numbers are stored in complex
conjugate form. The plot also shows the
corresponding time taken when a multiply-
accumulate loop is involved in the back
Fig. 6. Back substitution results: Nios Processor vs. hardware
only approach
substitution is accelerated in hardware and
accessed as a custom peripheral by the processor.
For an example of N=9, the Nios processor
takes approximately 12,000 clock cycles or
120 s (software-only approach), which is
acceptable for many applications. For faster
updates, the Nios processor with hardware-
acceleration approach can be used, and requires
only 300 clock cycles or 3 s, but at the expense
of additional hardware resources. Moreover, the
Nios processor can be used to implement other
data and control functions on the FPGA during
the time it is waiting for the outputs from the
CORDIC block. This facilitates a complete
system-on-a-programmable-chip (SOPC)
solution without the need for an external
processor.
VI. SUMMARY
A novel implementation of the QRD-RLS
algorithm using Altera’s Stratix FPGAs with
embedded Nios soft processor technology was
proposed. The ability to exploit the deeply
pipelined parallel architecture of Altera’s
CORDIC block to implement the QR-
decomposition using the discrete mapping
scheme was described, and resource estimates
were presented. The back-substitution algorithm
was implemented on the configurable Nios soft
processor with custom instructions for hardware
acceleration. Simulation results were also
presented, illustrating the efficiency of the Nios
processor to facilitate an integrated SOPC
solution.

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http://www.altera.com/literature/lit-nio.jsp