Astro 2004 7

Cell-Based IC Physical
Design and Verification with

Astro
陳麒旭
cschen@cic.org.tw
Astro
Design Setup
General Astro Flow
Design
Design Setup
Setup Unit1
Unit1
Gate-level
Gate-level Floorplanning
Floorplanning Unit2
Unit2
Netlist
Netlist
Timing
Timing Setup
Setup Unit3
Unit3
Placement
Placement Unit4
Unit4
GDSII CTS
CTS Unit5
Unit5
GDSII
Layout
Layout Routing Unit6
Routing Unit6
Design
Design for
for Manufacturing
Manufacturing Unit7
Unit7
Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen 1-2
Cell-Based IC Physical Design and Verification with Astro
What does Design Setup entail?
z Library Data
z Technology File
z Reference Libraries
z Design Data
z Gate-level Netlist
z Timing Constraints
z Starting Cell
Design Setup
z Create Design Library
z Library > Create
z Attach Reference Libraries
z Read Netlist
z Expand Netlist
z Open Design Library & Create Starting Cell
z Bind Netlist to Cell
z Preserve the Hierarchy
z Save Starting Cell
Create Design Library
z A design library is a container that holds or points to all
of the logical and physical data
z A technology file must be specified when creating a
design library; it contains:
z Layer definitions
z Via definitions
z Process design rules (example: min width/spacing)
z TLU parasitic capacitance models
z Preferred routing directions
z GUI display info (example: color and fill of layers)
z Units, example: time, capacitance, distance
z Astro’s design library utilizes Milkyway database
Unix Structure of Design Library
Library Name LM
LM views
NETL EXP CEL FRAM TIM lib

CHIP.NETL CHIP.EXP CHIP.CEL CHIP.FRAM CHIP.TIM lib_1
lib_bck
CHIP CHIP CHIP CHIP CHIP Design Cell
CODEC CHIP_cts
inv CHIP_route
Net Expanded Cell Frame views Timing views

views netlist views views
Design Setup
z Library > Add Ref
z Read Netlist
z Expand Netlist
Design Library & Reference Library
StdLib DAC
Physical Hierarchy
inv DAC
nand2 Recorder
nor2 ADC DAC IOLib
IO1
CODEC
inv
IO2
IO1
xor3 MEM
Reference CHIP IO99

Memory
IO99
MEM Top Cell Name
Design Setup
z Read Netlist
z Netlist In > Verilog In
z Expand Netlist
Power Connection
Original netlist Implicit Power/Ground
representation connections
1’b1 VDD
VDD
GND
GND
1’b0
Explicit input
NETL/ connections to global
representation Power/Ground
VDD
GND
Naming Convention
module
module CHIP(x,
CHIP(x, y);
y);
.....
.....
mm inst_m(
inst_m( .i(a),
.i(a), .j(b),
.j(b), .k(c)
.k(c) );
);
.....
.....
endmodule
endmodule
module
module m(i,
m(i, j,
j, k);
k);
.....
.....
wire
wire t;
t;
nn inst_n(
inst_n( .p(d),
.p(d), .q(e)
.q(e) );
);
.....
.....
endmodule
endmodule
module
module n(p,
n(p, q);
q);
.....
.....
wire
wire tmp;
tmp;
buf
buf buffer( .in(in),
buffer( .in(in), .out(out)
.out(out) );
);
.....
.....
endmodule
endmodule
inst_m.inst_n.tmp inst_m.inst_n.buf
Library After Reading Netlist
Recorder
NETL EXP CEL FRAM LM lib

lib_bck
CHIP
CODEC Top
Top Cell
Cell and
and Sub
Sub Blocks
Blocks of
of All
All
inv Hierarchy
Hierarchy
Net
views
Design Setup
z Read Netlist
z Expand Netlist
z Netlist In > Expand
Flat Layout vs. Hierarchical Netlist
z The physical layout is a flat representation of all leaf
cells from all logical hierarchy levels. Logical sub-blocks
“disappear” and are ignored.
Hierarchical Netlist Flat Layout
Top Top
A2 C1 C3
A B
A4
RAM A3 C2
A1 A2 A3 A4 C RAM
= leaf cell A1
(std or macro cell) C1 C2 C3
Global Power/Ground “Association” to Cells
z During expansion, P/G ports in std and macro cells must
be “associated” with corresponding Global Power/Ground
signals
z Use the “Global Nets Option” dialog to specify, which
ports are associated with which global nets
P/G ports “associated”
with global
NETL/ EXP/ Power/Ground
representation VDD representation
VDD
VDD
VDD
GND
GND
GND GND
Library After Expanding Netlist
Library Name

lib_bck
CHIP CHIP
CODEC
Top
Top Cell
Cell Only
Only
inv
Net Expanded
views netlist views
Design Setup
z Read Netlist
z Expand Netlist
z Library > Open & Cell > Create
Library After Creating Starting Cell
Library Name

lib_bck
CHIP CHIP CHIP
CODEC
CHIP
CHIP
inv (Empty
(Empty Layout)
Layout)
Net Expanded Cell

views netlist views views
Design Setup
z Read Netlist Expanded Netlist
z Expand Netlist
z Design Setup > Bind Netlist
CHIP
CHIP
z Preserve the Hierarchy (Empty
(Empty Layout)
Layout)
Design Setup
z Read Netlist
z Expand Netlist
z Cell > Initialize Hierarchy Information
z Cell > Mark Module Instances Preserved
Post-layout Gate-level Simulation
z Astro operates on a flat design
z By default, output netlist is flat:
z Test “probe” points on sub-block boundaries may have moved or
disappeared – cannot reuse test bench
z Problem: How do you reuse existing test benches and
stimulus files?
z Solution: “Preserve the Hierarchy” during P&R
Hierarchy Preservation
z Hierarchy preservation is done in two steps:
z Initialize Hierarchy
z Maintains the sub-block hierarchy of selected blocks
z A necessary first step if you want to “mark as preserved” or do

an HVO (Hierarchical Verilog Out) at project end
z Allows decode of hierarchical names in the SDC file
z Mark as Preserved
z Tells Astro that pin name, number and functionality must
remain the same
z Usually the entire hierarchy is marked
z Depending on the verification technology, it may be

unnecessary to mark as preserved to the lowest level
Design Setup
z Read Netlist
z Expand Netlist
z Preserve the Hierarchy CHIP
CHIP
CHIP_designsetup
CHIP_designsetup
z Save Starting Cell CHIP_floorplan CHIP_floorplan
z Cell > Save! & Cell > Save As CHIP_place
CHIP_place
…
…
Lab 1-1
Astro
Floorplanning
General Astro Flow
Design
Design Setup
Setup Unit1
Unit1
Gate-level
Floorplanning Unit2
Unit2
Netlist
Netlist
Timing
Timing Setup
Setup Unit3
Unit3
Placement
Placement Unit4
Unit4
GDSII CTS
CTS Unit5
Unit5
GDSII
Layout
Routing Unit6
Design
Design for
for Manufacturing
Manufacturing Unit7
Unit7
Floorplan Areas
Pad Area
Core Area
Floorplanning
z Create power and corner pads
z Specify IO Constraint
z Define the core and pad area
z Place the macros
z Implement P/G grid
z Defining placement and routing blockages
Creating Power and Corner Pads
;; Create
Create P/G
P/G pads
pads for
for core
core power
power supply
supply
dbCreateCellInst
dbCreateCellInst (geGetEditCell)
(geGetEditCell) ""
"" “PVSSC.FRAM"
“PVSSC.FRAM" “vss_core_1"
“vss_core_1" "0"
"0" "NO"
"NO" '(0.0
'(0.0 0.0)
0.0)
dbCreateCellInst (geGetEditCell) "" “PVDDC.FRAM"
"" “PVDDC.FRAM" “vdd_core_1"
“vdd_core_1" "NO" '(0.0 0.0)
"NO" '(0.0 0.0)
;; Create
Create corner
corner cells
cells
dbCreateCellInst
(geGetEditCell) ""
"" “PCORNER.FRAM"
“PCORNER.FRAM" "CornerLL"
"CornerLL" "270"
"270" "NO"
"NO" '(10
'(10 10)
10)
dbCreateCellInst (geGetEditCell) "" “PVSSC.FRAM" “vss_core_1" "0" "NO" '(0.0 0.0)
0o
Cell ID Reference Reference Instance Rotation Mirror Origin (X,Y)

270o Library Cell name
90o
Return current cell

Return current library
180o Rotation
Floorplanning
z Define the core and pad area
z Place the macros
IO Constraints
z By default pads are evenly distributed on each side
pad padName padSide Cul T1 T2 Cur

[padOrder] [padOffset] [“reflect”]
padOrder constraint
pad “Cul＂ “left＂ 4 L3 overrides
pad “Cur＂ “top＂ 3 padOffset constraint
pad “Clr＂ “right＂ 1
pad “Cll＂ “bottom＂ 1 L2
pad “L1＂ “left＂ 1 400
pad “L2＂ “left＂ 2 400
pad “L3＂ “left＂ 3 200 L1
200
pad “T1＂ “top＂ 1
pad “T2＂ “top＂ 2 Cll Clr
Floorplanning
z Create the core and pad area
z Design Setup > Set Up Floorplan
z Place the macros
Create Core Area (1/2)
Core To Left
Width
Distance Control
Control Parameters
Parameters
Aspect
Aspect Ratio
Ratio
-- Utilization
Utilization
-- Aspect
Aspect ratio
ratio (H/W)
(H/W)
Core Area
Height -- Row/core
Row/core ratio
ratio
Width
Width && Height
Height
-- Width
Width
-- Height
Height
Bottom of row key -- Row/core
Row/core ratio
ratio
……….
……….
horizontal
Core To Bottom no double back
Distance
no-flip first row
Create Core Area (2/2)
Row
(Area：1600 µm2)
Channel
(Area：400 µm2) 13µm
50µm
Standard Cell
(Area：800 µm2) 10µm 11µm
Aspect ratio: 40/50 = 0.8
40µm
Core Utilization: 800/2000 = 0.4
Row/Core Ratio: 1600/2000 = 0.8
Core to Left: 10
Core To Right: 11 12µm
Core To Bottom: 12
Core To Top: 13
Create Pad Area
z Signal pads
z Instantiated in netlist
CornerUR
z Power and corner pads
z Created with dbCreateCellInst
Reset
command in the tdf file Filler
z Filler pads
z Inserted later with PostPlace > Add Pad VDD
Fillers command VSS
z P/G rings:
z Added later with PreRoute > Pad Rings
command
z Pad area is created by loading the tdf
file
Chip Package Requirements
z Bond wire requirements
z No crossing
z Min spacing
z Max angle
z Max length
z More … Wire crossing
over bond
Core Area
finger violation
Pads moved to
clear violation
Specify IO Pad Location
;; Variable
Variable definition
definition for
for aa shorter
shorter name
name used
used below
below
define
define _cell
_cell (geGetEditCell)
(geGetEditCell)
;; Place
Place IO using Cartesian
IO using Cartesian Coordinate
Coordinate
dbCreateCellInstPlacement
dbCreateCellInstPlacement _cell
_cell “D0"
“D0" "270"
"270" "no"
"no" "origin"
"origin" '(0
'(0 400.00)
400.00)
dbCreateCellInstPlacement
dbCreateCellInstPlacement _cell
_cell “D1"
“D1" "270"
"270" "no"
"no" "origin"
"origin" '(0
'(0 480.00)
480.00)
dbCreateCellInstPlacement _cell "VDD1"
dbCreateCellInstPlacement _cell "VDD1" "270"
"270" "no" "origin" '(0 560.00)
"no" "origin" '(0 560.00)
dbCreateCellInstPlacement _cell “D0" "270" "no" "origin" '(0 400.00)
VSS1
Filler
VDD1 Cell ID Pad Rotation Mirror Reference Location
D1 name Point of Cell (X,Y)
D0
z Unspecified pads are placed automatically

CornerLL CK
Cell After Creating Core and Pad Areas
Unplaced
Unplaced Macro
Macro
Flip
Flip First
First Row
Row
Double
Double Back
Back
Unplaced
Unplaced
Standard
Standard
Cell
Cell
Floorplanning
z Place the macros
z Modify > Move & Modify > Transform
Floorplanning
z Place the macros
z Connect Ports to P/G (PreRoute > Connect Ports to P/G)
z Create Ring (PreRoute > Rectangular Rings)
z Create Strap (PreRoute > Straps)
z Connect Macro & IO P/G ports to Ring (PreRoute >
Macros/Pads)
P/G Grid and Blockages
core macro
macro ring
ring
core ring
ring
strap
strap
soft
soft
blockage
blockage hard
hard
blockage
blockage
Connect Ports to P/G
module
module CHIP(…);
CHIP(…);
INV
INV i1(...);
i1(...); VDD
AND
AND a1(...);
a1(...); VDD VDD VDD1
Macro m1(...
Macro m1( ...);
); O B
PPAD(...);
PPAD(...); INV AND X Macro Y
GPAD(...);
GPAD(...); I A O
GND
…..
….. VSS VSS
endmodule
endmodule VSS
1. Connect power to standard cells

2. Connect power to macros VDDP Core Power VSSP Core Ground
3. Connect power to IO cells PPAD Pad GPAD Pad
4. Connect ground to standard cells
5. Connect ground to macros
6. Connect ground to IO cells
Create Ring
LH RH
TL TH
BL BH
LL RL
Create Strap
At First Targets Extend to High Boundaries
and Generate Pins
At Core Bdry
VSS
VDD
750 1250
Step
Group2
Group1
Pitch
(0,0)
2 Ring + 1 Strap
ring macro macro macro ring
strap
3 Straps
macro macro macro
strap strap
strap
Connect Macro & IO P/G ports to Ring
Connections are made to

the closest P/G grid
on each side of the instance
Floorplanning
z Place the macros
z Defining placement blockages
z Create hard blockage (PrePlace > Create Hard Blockage)
z Create soft blockage (PrePlace > Create Soft Blockage)
Hard Blockage vs. Soft Blockage
Hard blockage
prevents standard cells
from being placed
Macro 1 Macro 2 in this region
Soft blockage
allows new
buffers/inverters
to be inserted
Hard placement blockage
Soft placement blockage during optimization
Lab 1-2
Astro
Timing Setup
General Astro Flow
Design
Design Setup
Setup Unit1
Unit1
Gate-level
Floorplanning Unit2
Unit2
Netlist
Netlist
Timing
Timing Setup
Setup Unit3
Unit3
Placement
Placement Unit4
Unit4
GDSII CTS
CTS Unit5
Unit5
GDSII
Layout
Routing Unit6
Design
Design for
for Manufacturing
Manufacturing Unit7
Unit7
Timing Driven P&R
z Astro optimizes the logic gates, places and routes them
to fit in the smallest possible area while meeting all
timing constraints
z In addition to P&R, Astro has the capability of
z static timing analysis (STA) for the given timing constraints
z interconnect parasitic extraction estimation and calculation
z logic gates optimization based on the physical design information
Static Timing Analysis (STA)
z Main steps of STA
z Break the design into sets of timing paths
z Calculate the delay of each path
z Check all path delays to see if the given timing constraints are
met
z Four types of paths
PI
Combinational Logic
Start Point End Point
PO
Block-based vs. Path-based STA
AT=2
2
1
9 Path-based:
2+2+3 = 7
2+3+1+3 = 9
(OK)
(OK)
3 RAT=10 2+3+3+2 = 10 (OK)
3
1 2 5+1+1+3 = 10 (OK)
AT=5 3 5+1+3+2 = 11 (Fail)
1 5+1+2 = 8 (OK)
AT=2 AT=7
AT=2 RAT=5 RAT=7 Block-based:
2
1 Critical path is determined
3 RAT=10 as collection of gates with
AT=6 3
1 RAT=5 2 the same, negative slack:
AT=5 3 In our case, we see one
AT=11
AT=5
1 AT=9 RAT=10 critical path with slack = -1
RAT=4 RAT=8
Data Preparation for STA
Gate-level Netlist Back-annotated Parasitic

Design Data Interconnect Data
Block Models Estimated Wire Load Models
STA
Descriptions of Clocks
Timing Constraints
Cell Library
Library Data Boundary Conditions
Operating Conditions
Timing Exceptions
Library Data
z Cell Delay model
z Linear model
z Non-linear model
z Operating conditions
Linear Cell Delay Model
delay time (ns)
Cell Delay = T0 + Ac * Cload

T0
output capacitance load (pf)
T0 : cell pin to pin intrinsic delay

(delay without any loading)
Ac : drive impedance
Non-linear Cell Delay Model
z Delay values are stored in the delay tables
z Delay tables
z Cell delay Vin 50% 50%
z Transition delay
Vout
20% 80%
Dc Dtransition(I2)
I1
I2
Dtransition(I1) I3
Req
Dcell(I2) Ceq
Delay Tables
Cell Delay Dcell(I2) = f(Dtransition(I1), Ceq)
Transition Delay Dtransistion(I2) = g(Dtransition(I1), Ceq)
Output Input Transition

Capacitance 0 0.5 1 index1: input transition
0.1 0.123 0.234 0.456
Index2: output capacitance
0.2 0.222 0.432 0.801
Vin Dc Vout Dtransition(I2)

I1
I2
Dtransition(I1) I3
Req
Dcell(I2) Ceq
Select the Correct Delay Table
z According to output transition direction
z rise table
z fall table R F
z Output transition direction depends on unateness

z invert (positive_unate)
z noninvert (negative_unate)
z nonunate R or F
z The worst case delay is selected R
z Consider the clock edge for sequential cells
z edge_rising
z edge_falling
z The process, voltage, and temperature (PVT) ranges a
design encounters
z Specified in the technology library
z Cell and interconnect delays are scaled
Dscale = D (1 + ∆ P K P )(1 + ∆V KV )(1 + ∆ T K T )
∆ P = Pr ocess − nom _ process / ∆V = Voltage − nom _ voltage
∆ T = Temperature − nom _ temperature
delay delay delay

Worst
Worst Typical Worst

Best
Typical Typical
Best Best
Process Voltage Temperature

STA
Timing Constraints
Cell Library
Timing Exceptions
Define Timing Constraints
z Design rule constraints
z Set fan-out constraints
z Set capacitance constraints
z Set transition time constraints
z Design optimization constraints
z Define clock specification
z Specify boundary conditions (I/O timing requirements)
z Specify combinational path delay requirements
z Specify timing exceptions
Define Clock Specification
z We need to accurately specify the clock including the
clock routing details in the early design stage in order to
achieve timing convergence
z What should be defined?
z Period
z Waveform
z Latency
z Source latency
z Network latency
z Uncertainty
z Jitter
z Skew
z All register-to-register path are constrained now

Clock Period & Waveform
z Period: Clock cycle time
z Waveform: Clock rise and fall time
z Example:
z Period: 10ns
z Rise time: 0ns
z Fall time: 5ns
clock
0 5 10
Clock Latency
z A very important part of the clock is the routing effects:
z Off Chip cause:
z Source latency (delay): the timing a clock signal takes to
propagate from its ideal waveform original point to the clock
definition point
z On Chip cause:
z Budgeted network latency (delay) : the time the clock signal
takes to propagate from the clock definition point to the
clock pin of the sequential cells
z Actual insertion delay
D Q
QN
network latency
source latency
(min_rise : max_rise : min_fall : max_fall)
Clock Uncertainty Definition
z The maximum difference between the arrival of clock
signals at sequential cells in one clock domain or
between domains
P1
FF Arrival(P1) = 0.5ns
Arrival(P2) = 1ns
Arrival(P3) = 1.2ns
P2 FF Arrival(P4) = 1.3ns
P3
P4
uncertainty = 1.3 – 0.5
= 0.8ns
FF FF
Clock Uncertainty
z A very important part of the clock is the routing
z Off Chip impact:
z Jitter: typically a small value
z On Chip impact:
z Budgeted skew
z Actual skew
Ideal and Computed Clocks
z Off chip clock effects are fixed throughout flow:
z Source Latency
z Jitter
z On chip routing is estimated till clock tree routing
z Budgeted network latency
z Budgeted skew
z On chip routing is calculated after clock tree routing
z Actual insertion delay (network latency)
z Actual skew
I/O Constraints
z After constraining clock, we still need to constrain the
I/O
z Only comboin needs a "budgeted" arrival time
z Only combout needs a "budgeted" required time
Boundary Conditions
z Input driving cell
z Input transition time
z Output capacitance load
z Input delay
z Output delay
D Q b
Driving Cell INV01 5pf
QN
Output Capacitance Load

Input Transition Time
Input & Output Delay
z An input delay is the specification of an arrival time at an
input port relative to a clock edge
z An output delay represents an external timing path from
am output or inout port to a register
Input delay = Delayclk-Q + a
Q a Q b c
Input Block My Design Output Block

Output delay = c
Constraint Combinational Path Delay
z Set a target maximum delay for output ports
z Override the default single-cycle timing for paths
z Set a target minimum delay for output ports
z Override the default hold relation in a sequential path
IN Logic Out
z False Path
z Multi-cycle path
False Path
z Why are there false path constraints in a design?
z A path may exist in the circuit but never be used in its normal
functional operation
z A functional path may exist but the timing is very slow or
irrelevant
z A block may be reused and certain signal functions are no longer
required
z A path may exist in the circuit but no combination of input
vectors may ever exercise it
z A combinational loop exists in the design that needs to be
broken
Unexercised Path
z A path may exist in the circuit but never be used in its
normal functional operation
z A test register PROBE is inserted in the circuit to enable chip
debugging in the field. Data can be read through the probe
register. Data can be written from the probe register. Probing
would not occur at speed. (An alternative to scan)
False Path
irrelevant
required
broken
Irrelevant Path
z A functional path may exist but the timing is so slow or
irrelevant
z The chip uses a synchronized synchronous reset. The reset cycle
has a huge number of cycles before it needs to settle.
Asynchronous Path
z A functional path may exist but the timing is so slow or
irrelevant
z I have metastabilization registers between those two
asynchronous clock zones
False Path
irrelevant
required
broken
IP Reuse
z A block may be reused and certain signal functions are
no longer required
z This piece of logic is a custom adder. With design re-use, often
the blocks contain all of the potentially useful functions. When
the design is implemented in a chip, often particular signals are
not implemented
False Path
irrelevant
required
broken
Logically Impossible Path
z A path may exist in the circuit but no combination of
input vectors may ever exercise it
z A signal cannot travel from the Q output of a_reg through the
two muxes to b_reg
z PrimeTime attempts to automatically detect "logically impossible
false paths“ (requires many CPU cycles)
z These situations are quite rare
False Path
irrelevant
required
broken
Combinational Loops
z A combinational loop exists in the design that needs to
be broken
z Most STA’s can’t leave combinational loops in the design, as a
race condition will occur
z PrimeTime dynamically
breaks combinational
loops.
Break Combinational Loops
z Break any reset arc (unusually specified)
z Break a three-state enable arc
z Break at the first loop re-entry point
z Break arcs in the library
z False Path
z Multi-cycle path
Multicycle Paths
z Multicycle paths occur because the designer knows that
the particular logic function will not be used till a later
cycle

STA
Timing Constraints
Cell Library
Timing Exceptions
Interconnect Data
z Estimated delay information for nets based on a wire
load model is used before P&R
z Back-annotated (Actual) delay information based on the
P&R result is often described in the form of
z SDF (timing information) – Standard Delay Format
z SDF triplet: (min:typ:max)
z RSPF – Reduced Standard Parasitic Format

z DSPF – Detailed Standard Parasitic Format
z SPEF – Standard Parasitic Exchange Format
z SPEF also has syntax that allows the modeling of capacitance
between different nets, so it is used by the crosstalk analysis
tool
Wireload Model
z Very inaccurate!
wire_load (“500”) (
resistance : 3.0 /* R per unit length*/
capacitance: 1.3 /* C per unit length */
area: 0.04 /* area per unit length */
slop: 0.15 /* extrapolation slope*/
500um x 500um
1000um x 1000um fanout_length ( 1 , 2.1 ) /* fanout-length pairs */
fanout_length ( 2 , 2.5)
Cwire = (fanout=3, length =2.8) x capacitance coefficient (1.3) =

3.64 load units
Rwire = (fanout=3, length =2.8) x resistance coefficient (3.0) = 8.4
resistance units
AreaNet = (fanout=3, length =2.8) x area coefficient (0.04) = 0.112
net area units
Wireload Modes
Parasitic Model During P&R
z Compute wire length
z Ideal Manhattan Model
z Computed Manhattan Model
z Global Routing Model
z Compute parasitic value
z Linear parasitic model
z Table lookup parasitic model
z Calculate wire delay
z Elmore Model
z Final Layout Model
Ideal Manhattan Model
Computed Manhattan Model
Global Routing Model
Table Lookup Parasitic Model
z Table-Look-Up (TLU) Capacitance model
z CapTable
z cap_value = f(configuration, width, spacing)
z CapModel
z Assign CapTable to the reference layer according to the
configuration
z Capacitances are categorized into bottom, top and lateral
group
M2 air top
M1 lateral
Poly substrate
bottom
configuration1 configuration2 configuration3
Elmore Model
Final Layout Model
z AWE (Extraction Based) Model
z p1 , p2 – Poles
z r1 , r2 - Residues
Perform Static Timing Analysis

Specify
design data
Cell Library
& libraries
Specify
interconnect
Constraint Path
Descriptions of Clocks Violation Timing
Specify Reports Reports
Boundary Conditions timing constraints
Timing Exceptions
Check
Timing
STA Example 1 (Assumptions)
z Check setup time violations
z Assume all gates have 3ns max rise delay and 2ns min
rise delay
z Assume all gates have 2ns max fall delay and 1ns min
fall delay
z Assume all nets have 2ns max delay and 1ns min delay
z 3ns CLK-Q delay
z 1ns setup time (Ts)
z 1ns hold time (Th)
STA Example 1 (Timing Constraints)
z Clock definition
z Clock period: 14ns (Dclkp)
z Clock source latency: 2ns (Dclks)
z Clock network latency: 3ns (Dclkn)
z Clock uncertainty: 1ns (Dclku)
z IO constraints
z Input delay of A, B, C: 1ns (Da , Db , Dc)
z Output delay of Y: 3ns (DY)
STA Example 1 (Timing Paths)
Timing Path 1
Timing Path 2
Timing Path 3
STA Example 1 (AT of Path1 - Rise)
z Timing path 1: PI to clock data input
z Arrival time at end point: Da+2+3+2+3+2 = 13ns
launch edge source clock (ideal)

0 13 14
capture edge target clock (ideal)
AT
R 2 Why are the

AT = 13
delay values
R chosen?
3 2
2 R
3
STA Example 1 (AT of Path1 - Fall)
z Arrival time at end point: Da+2+2+2+3+2 = 12ns

0 12 14
capture edge target clock (ideal)
AT
F 2 Why are the

AT = 12
delay values
F chosen?
2 2
2 R
3
STA Example 1 (RT of Path1 - R/F)
z Required time at end point: Dclkp + Dclks + Dclkn - Dclku - Ts =
14+2+3-1-1 = 17ns

0 14
target clock (ideal)
16 target clock (source)
capture edge 19 target clock (source+network)
18 target clock (source+network

RT +uncertainty)
setup time
17
STA Example 1 (Slack of Path1 - Rise)
z Slack at end point: RT - AT = 17-13 = 4ns
z Timing is met since slack is greater than 0
R 2
AT = 13
RT = 17
R
3 2
2 R
3
STA Example 1 (Slack of Path1 - Fall)
z Slack at end point: RT - AT = 17-12 = 5ns
AT = 12
F 2
RT = 17
F
2 2
2 R
3
z Timing path 2: clock to clock data input
z Arrival time at end point: Dclks + Dclkn +3+2+3+2+3+2 = 20ns
source clock (ideal)

0 5 14 19 20
launch edge source clock (source
AT +network)
AT = 20 Why are the

delay values
R chosen?
3 3
R2 2 2
3 R

0 5 14 19
+network)
AT
AT = 19 Why are the

delay values
F chosen?
3 2
F2 2 2
3 R
z Required time at end point: Dclkp + Dclks + Dclkn - Dclku - Ts =
14+2+3-1-1 = 17ns
launch edge source clock (source+

5 14 network)
0
16 target clock (source)
capture edge 19 target clock (source+network)
18 target clock (source+network

RT +uncertainty)
setup time
17
z Slack at end point: RT - AT = 17-20 = -3ns
z Timing is not met since slack value is negative
AT = 20
RT = 17
R
3 3
R2 2 2
3 R
AT = 19
RT = 17
F
3 2
F2 2 2
3 R
z Timing path 3: clock to PO
z Arrival time at end point: Dclks + Dclkn +3+2+3+2= 15ns

0 5 14 15
+network)
AT
3
R
2 AT = 15
R
3
2

0 5 14
+network)
AT
3
F
2 AT = 14
F
2
2
z Required time at end point: Dclkp - DY = 14-3 = 11ns

5 11 14 network)
0
RT
output delay
3
F D Q
2 RT = 11
3
F QN
2
2
z This is the critical path
3 AT = 15
R D Q
RT = 11
2 3
R QN
3
2
3 AT = 14
F D Q
RT = 11
2
3
F QN
2
2
STA Example 2 (Assumptions)
z Check hold time violations
z Assume all gates have 3ns max rise delay and 2ns min
rise delay
z Assume all gates have 2ns max fall delay and 1ns min
fall delay
z Assume all nets have 2ns max delay and 1ns min delay
z 3ns CLK-Q delay
z 1ns setup time (Ts)
z 1ns hold time (Th)
STA Example 2 (Timing Constraints)
z Clock definition
z Clock period: 14ns (Dclkp)
z Clock source latency: 2ns (Dclks)
z Clock network latency: 3ns (Dclkn)
z Clock uncertainty: 1ns (Dclku)
z IO constraints
z Input delay of A, B, C: 1ns (Da , Db , Dc)
z Output delay of Y: 3ns (DY)
STA Example 2 (Timing Paths)
Timing Path 1
Timing Path 2
Timing Path 3
STA Example 2 (AT of Path1 – R/F)
z Arrival time at end point: Da+1 = 2ns

0 2 14 target clock (ideal)
capture edge
Why are the
AT delay values
Next Data chosen?
AT = 2
R/F
D Q
1 1
QN
z Required time at end point: Dclks + Dclkn + Dclku + Th = 2+3+1+1
= 7ns

0 7
target clock (source)
target clock (source+network)
capture edge target clock (source+network
+uncertainty)
RT
hold time
STA Example 2 (Slack of Path1 – R/F)
z Slack at end point: AT - RT = 2-7 = -5ns
z This is the critical path
R/F
D Q
1 1
AT = 2
QN RT = 7

0 5 14 19 20
+network)
AT
Next Data
AT = 15 Why are the

delay values
R chosen?
3 2
R1 1 1
2 R

0 5 14
+network)
AT
Next Data
AT = 14 Why are the

delay values
F chosen?
3 1
F1 1 1
2 R
z Required time at end point: Dclks + Dclkn + Dclku + Th = 2+3+1+1
= 7ns

0 7
target clock (source)
target clock (source+network)
capture edge target clock (source+network
+uncertainty)
RT
hold time
z Slack at end point: AT - RT = 15-7 = 8ns
AT = 15
RT = 7
R
3 2
R1 1 1
2 R
z Slack at end point: AT - RT = 14-7 = 7ns
AT = 14
RT = 7
F
3 1
F1 1 1
2 R

0 5 12
+network)
AT
Next Data
3
R
1 AT = 12
R
2
1
z Arrival time at end point: Dclks + Dclkn +1+1+1= 11ns

0 5 11
+network)
AT
Next Data
3
F
1 AT = 11
F
1
1
z Required time at end point: - DY = -3ns

-3 0 network)
RT
output delay
F D Q
1 RT = -3 3
F QN
1
1
z Slack at end point: AT - RT = 12-(-3) = 15ns
AT = 12
R RT = -3 D Q
1 3
1
R QN
2
1
z Slack at end point: AT - RT = 11-(-3) = 14ns
AT = 11
F D Q
1 RT = -3 3
1
F QN
1
1
Astro Timing Setup
z Define and Load Timing Constraints
z Timing > Load SDC
z Check Timing Data
z Attach Parasitic Model
z Set Appropriate Parameters in Timing Setup Panel
z Timing Sanity Check
z Net Delay Model Selection
z Before CTS
z After CTS
SDC Timing Constraints (1/2)
z Define clock waveform
create_clock -name “SYS_CLK" -period 10 -waveform {0 5} [get_ports {clk}]
create_generated_clock -name MY_CLK -source [get_ports {clk}]

-multiply_by 1 [get_pins {ipad_clk/Y}]
z Define clock latency

set_clock_latency 2 [get_clocks {MY_CLK}]
z Define clock uncertainty

set_clock_uncertainty 0.5 [get_clocks {MY_CLK}]
z Set Propagated Clock

set_propagated_clock [get_clocks {MY_CLK}]
SDC Timing Constraints (2/2)
z Set input delay
set_input_delay 1 -clock "MY_CLK" [get_ports {datain[0]}]
z Set output delay

set_output_delay 2 -clock "MY_CLK" [get_ports {dataout[0]}]
z Set output load

set_load -pin_load 10 [get_ports {dataout[0]}]
z Set false path

set_false_path -setup -from [get_ports {TEST_SI}]
z Set Operating Condition (Necessary when LM view is

used instead of timing view)
set_operating_conditions -min fast -max slow
Astro Timing Setup
z Check Timing Data
z Timing > Timing Data Check
z Before CTS
z After CTS
Check Timing Data
z After reading SDC constraints, you must ensure that
they completely constrain the design.
z Completeness does not imply correctness!
Number of unconstrained endpoints
in the design: 30
Unconstrained Endpoints:
------------------------
h264_d1
h264_d2
...
Number of input ports with no delay: 4
Ports With No Input Delay:
--------------------------
din[0]
reset
...
Astro Timing Setup
z Check Timing Data
z Tech File > ITF to TLU+
z Before CTS
z After CTS
Attach Parasitic Model
The Mapping File translates

.tf (Astro technology file)
layer/via names into StarRCXT
.itf layer/via names.
018.itf
DIELECTRIC IMD1B { THICKNESS=1.28 ...}
DIELECTRIC IMD1A { THICKNESS=0.6 ...}
CONDUCTOR ME1 { THICKNESS=0.48 WMIN= ...}
Layer “met1" { conducting_layers

layerNumber = 46 poly POLY
Verify that star_rcxt data is 018.tf maskName = "metal1" metal1 ME1
consistent with the main metal2 ME2
...
…
library’s technology data! 018.map
Select TLU+ Capacitance Model
z Choice is made in “Timing Setup Panel”
z Timing > Timing Setup
Make
Make sure
sure you
you click
click Apply
Apply
after
after making
making changes
changes
Astro Timing Setup
z Check Timing Data
z Before CTS
z After CTS
Timing Sanity Check
z Verify that the constrained netlist has a good chance of
meeting timing after P&R
z Timing Analysis is performed while ignoring net C
Set
Set “Ignore
“Ignore Interconnect”
Interconnect”
option
option for
for zero
zero CC
Net Delay Model Selection (1/2)
z After placement, but prior to routing, net geometry is
estimated based on a Virtual Route
z Since Virtual Routing is only an estimate use Elmore for
all steps up to and including routing
z After routing, detailed net is available and extraction will
be more accurate
z Use AWE or Arnoldi for post-route optimizations
z Arnoldi preferred when comparing to PrimeTime™
Net Delay Model Selection (2/2)
Before CTS
9
9
9
After CTS
9
9
9
Lab 1-3
Astro
Placement
General Astro Flow
Design
Design Setup
Setup Unit1
Unit1
Gate-level
Floorplanning Unit2
Unit2
Netlist
Netlist
Timing
Timing Setup
Setup Unit3
Unit3
Placement
Placement Unit4
Unit4
GDSII CTS
CTS Unit5
Unit5
GDSII
Layout
Routing Unit6
Design
Design for
for Manufacturing
Manufacturing Unit7
Unit7
Astro Placement and CTS Flow
z Detach Scan Chains
z Set Placement Common Options
z Pre-Placement Optimization
z Standard Cell Placement
z Post-Placement Optimization Phase 1 (PPO1)
z Clock Tree Synthesis
z Connect Scan Chains
z Clock Tree Optimization
Placement
z PrePlace > Trace Scan Chain
z PrePlace > Optimize/Delete Scan Chain
Scan Chains
z Scan chains are designed to load/unload test data:
z FFs are serially connected (alphanumeric ordering)
z Requires a lot of routing resources if serially connected FFs are
not placed in their ordering
z Routing can be reduced by placing serially connected FFs
based on their ordering:
z Requires long runtime to optimize FFs placement
z May hurt critical paths d[0] dout_1
FF FF
z A better solution... s_in1 FF s_out1
d[1] dout_2
s_in2 FF FF FF s_out2
d[2] dout_3
s_in3 FF FF FF s_out3
scan_en
Solution for Scan Chains
z Disconnecting the scan chains prior to placement allows
the tool to focus on better for the functional critical
paths
z Scan chains are re-connected after CTS using
placement-based scan chain reordering
FF Reorder Scan Chains
FF FF
d[0] dout_1
FF FF FF FF FF s_out1
s_in1 FF
d[1] dout_2
FF FF FF s_in2 FF FF s_out2
FF
d[2] dout_3
Detach Scan Chains s_in3 FF FF FF s_out3
scan_en
Placement
z InPlace > Placement Common Options
Set Placement Common Options
z Options must be set prior to any placement and
optimization steps.
Use at least Congestion and Timing
optimization mode.
Better run time Better chip

and congestion area
Placement
z PrePlace > Pre-Placement Optimization
Pre-Placement Optimization
z PrePlace optimization removes all WLM effects to create
a minimal "seed" netlist (clean slate) prior to actual cell
placement:
z Performs zero WLM (RC=0) optimization (Ideal Optimization) &
logic re-mapping
z Reduces total cell area by gate down sizing (area recovery) and
buffer removal
z Buffers high fanout nets based on a "reasonable" throw-away
placement (quick placement)
z If timing violations are more than 5%, go back to the
synthesis stage.
Estimating Timing During Placement
z Placement uses RC parameters from Virtual Route (VR)
to calculate timing
z VR = shortest Manhattan-distance between two pins
z VR RCs are much more accurate than WLM RCs
The Virtual Route in Astro

will look out for
blockages/obstructions.
If there are blockages,
the virtual route will
route around them
Buffer High Fanout Nets
z High fanout buffers are first collapsed then synthesized
based on VR RCs from a "quick" placement
z This creates a better “seed” netlist for actual placement
Collapse
HFNs
HFNs from
from Synthesis
Synthesis Netlist
Netlist HFNs
HFNs in
in “seed”
“seed” Netlist
Netlist
(based
(based on
on quick
quick placement)
placement)
Placement
z Connect Standard Cell Power/Ground
z PreRoute > Standard Cells
z Cell Placement
z Congestion Analysis and Fixing
Connect Standard Cell Power/Ground
z P/G rails for Std Cells uses routing resources. This
affects congestion!
z Create P/G rails early so they are accounted for during
placement
z Connect ports to P/G before this step for multiple PG
design
P/G Rail
VSS
VSS
VDD
VDD
Placement
z Cell Placement
z InPlace > Design Placement
Placement
HFN Re-Synthesis
In-Placement Opt.
The above 3 steps occur concurrently
Cell Placement
z Timing driven placement
z Tries to place critical path cells close together to reduce net RCs
and meet timing
z Is based on Virtual Route (VR)
z In-Placement Optimization (IPO) performs:
z Cell-sizing, cell-moving, cell-bypassing, net splitting, gate
duplication, buffer/inverter insertion, area recovery
Select In-Placement Optimization
for logic optimization and
HFN Collapse/Re-synthesis
Previous HFNS was based on "throw away“

placement. This HFNS build buffer trees for
the real placement. So HFN is re-synthesized.
Placement
z Cell Placement
z InPlace > Display Congestion Map
z InPlace > Search and Refine
Congestion
z There is a limit to the number of nets that can be routed
through the small area (enclosed by the red circle)
z When you approach or exceed this limit, the area is said
to be congested
z If placement remains unchanged, only solution is for the
actual route to detour
z Worse, if nets cannot be
detoured then the design
cannot be routed!
2D Congestion Map
6/5 7/5
Horizontal demand = 14
14/12
GRcell Horizontal supply = 12
Overflow = 2
6/5 8/5
1D Congestion Map
4/3
5/4
6/5
9/8
∑demand 24/20
∑ supply 1.20
0.99
0.81 0.76
0.43
Be Proactive with Congestion
z Actual detoured net will have worse RC / timing
compared to the VR estimate
z In highly congested areas, VR is therefore optimistic
congestion area
detoured net
Fix
Fix congestion
congestion problems
problems
prior
prior to
to routing
routing
Fix Congestion During Placement
z During placement, the congestion is fixed by spreading
cells apart
z Timing will get worse
z If the cells that are spread apart are in a timing critical path, this
path may violate timing
z These timing violations can be resolved by performing logic
optimization
z S&R works on localized areas
and spreads cells apart in
congested areas, even
at the expense of timing.
Placement
z PostPlace > Post-Place Optimization Phase 1
PPO1
z Performs setup fixing and max tran/cap fixing
z First time max tran/cap fixing is performed.
z Slack may get worse with Tran/Cap fixing. Violations will be
addressed during PPO2.
Enable
Enable Global
Global Routing
Routing (GR)
(GR)
for
for improved
improved accuracy
accuracy
Global Routing (GR)
z Assigns nets to specific
GRC
GRC (next
(next slide)
slide) global route
metal layers and global
routing cells (GRCs) to
more accurately predict
the final routing paths
and delays
z Also accounts for:
z P/G (rings/straps/rails)
z Routing blockages
z Placement blockages Y
z Congestion area virtual route

X congestion area
Global Routing Cells (GRCs)
z GR determines if each assigned GRC along a path has
enough wire tracks for the assigned nets through the
edges of that GRC M3
z If not enough wire tracks, M2
GR re-assigns metal layers M1

or GRCs accordingly
Z
Y GRC
X wire tracks
global route
GR
GR delay
delay calculations
calculations and
and placement
placement decisions
decisions are
are based
based on
on
more
more accurate
accurate estimated
estimated wire
wire routes
routes and
and parasitics
parasitics compared
compared to
to VR
VR
Additional GR Benefits in PPO1
z PPO1 uses global route to
Routing
foresee routing detours blockage
based on congestion and Detoured route
routing blockages
z Buffers are added to
account for long detoured
nets while observing
placement blockages
z More effort spent here
will speed up post-place
flow Placement
blockage
Lab 1-4
Astro
CTS
General Astro Flow
Design
Design Setup
Setup Unit1
Unit1
Gate-level
Floorplanning Unit2
Unit2
Netlist
Netlist
Timing
Timing Setup
Setup Unit3
Unit3
Placement
Placement Unit4
Unit4
GDSII CTS
CTS Unit5
Unit5
GDSII
Layout
Routing Unit6
Design
Design for
for Manufacturing
Manufacturing Unit7
Unit7
CTS
z Clock > Clock Common Options
z Clock > Clock Tree Synthesis
Effect of Clock Skew on Timing
The budget for

combinational
delay is 9ns only
-1ns
-1ns capature time = 10 – 1 = 9
Decrease the timing performance if there are critical paths

in the combinational logic cloud.
The budget for

combinational
delay is 11ns.
1ns
1ns capature time = 10 + 1 = 11
Increase the timing performance if there are critical paths Useful

Useful
in the combinational logic cloud. Skew
Skew
Why Clock Tree Synthesis?
z Normally, we do CTS for zero skew.
z Logical synthesis tool doesn't have good knowledge on
building good clock tree to buffer loads on the clock. Do
not add clock tree during synthesis.
z HFN synthesis is used to balance the load but it's not
good at balance the skew.
DQ
DQ DQ
Clock
CTS
DQ
CTS DQ
DQ
Clock
HFN
HFN synthesis
DQ
DQ synthesis
DQ
DQ
&
&
Skew
Skew optimization
optimization LPM D Q DQ
LPM D Q DQ
G G
How Clock Tree Synthesis?
z Add multi-level buffer trees according to your clock
specification (model/estimation) for the previous stages
z skew & insertion delay
z A good clock tree should have the same features as
described in the clock estimation
z CTS result will be always bad if the clock estimation is
not realistic. In this case, make realist clock estimation
according to the CTS result and then go back to the
Timing Setup stage.
Effects of Clock Tree Synthesis
z More buffers added
z Other cells may move
z Congestion may increase
z Can introduce new timing and max cap/trans violations
Clock Tree Synthesis Setup
z Settings for CTS and CTO
Include all clocks from the

SDC file if this field is empty
This skew value overrides

set_clock_uncertainty from the SDC
set_clock_latency from SDC

overrides this insertion delay value
Options will be used during CTO
Clock Tree Synthesis and Optimization
z Input to CTS should be
z placed design w/o clock tree
z tran/Cap fixed
z HFN synthesized
z minimized timing violations
z acceptable congestion
z SDC clock constraints
z Create clock tree to meet SDC targets

CTO can run automatically
right after CTS
When does CTS and CTO Stop?
CTS
CTS
No CTO
Skew < Target? CTO
Reduces
Reduces Skew
Skew
Yes
No CTO
CTO
Insertion Delay
> Target? Adds
Adds Delay Cells
Delay Cells
Yes
Default values are zeros which means to minimize

Stop
the targets as much as possible
After CTS
z Adjust the following in the timing setup panel to tell
optimizations to use the actual clock tree delays
z Set “Ignore Clock Uncertainty”, unless this is used to gain
additional margin
z Unset “Ignore Propagated Clock”
z Unset “Enable Ideal Network Delay “
z Reconnect scan chains so the next optimization steps
take them into account for hold time fixing
z After CTS, the design may have:
z Timing (setup/hold) violations
z Max transition and max capacitance violations
CTS
CTS
z PostPlace > Post Placement Optimization
PPO2
z Fixes violations due to CTS perturbations and addresses
hold for the 1st time
Enable to reduce
CTS
CTS
routing congestion
Setup
Setup and
and Hold
Hold Fixing
Fixing
Max
Max Tran/Cap
Tran/Cap Fixing
Fixing
Area
Area Recovery
Recovery
Setup/hold,
Setup/hold, no Vary
Vary PPO
PPO 22
max
max tran/cap
tran/cap
ok? Parameters
Parameters
ok?
yes For large design, target only one optimization

CTO
at a time, e.g. only max transition fixing
CTO
CTS
z Clock > Clock Tree Optimization
z Clock > Skew Analysis
Clock Tree Optimization
z Improve the clock tree after PPO 2
PPO2
PPO2
Clock
Clock Skew
Skew Analysis
Analysis
(next
(next slide)
slide)
no Optimize
Optimize
Skew
Skew OK?
OK?
Clock
Clock
yes
Routing
Routing
Clock Skew Analysis
z Global Clock Skew:
z Reports skew for all clocks
z Local Clock Skew:
z Arrival time difference between
two flops that are adjacent
through combinational logic
z Inter Clock Skew:
z The difference between clock
with smallest skew and clock
with largest skew
Lab 1-5
Astro
Routing
General Astro Flow
Design
Design Setup
Setup Unit1
Unit1
Gate-level
Floorplanning Unit2
Unit2
Netlist
Netlist
Timing
Timing Setup
Setup Unit3
Unit3
Placement
Placement Unit4
Unit4
GDSII CTS
CTS Unit5
Unit5
GDSII
Layout
Routing Unit6
Design
Design for
for Manufacturing
Manufacturing Unit7
Unit7
Design Status, Start of Routing Phase
z Standard cells are placed
z Clock tree and HFN buffers placed
z Virtual route (or optionally a Global route) was
completed:
z Estimated congestion - acceptable
z Estimated timing - acceptable (~0ns slack)
z Estimated net caps – no violations
z Estimated signal transition times – no violations
z Any “routes” done to gather information for a timing-
driven placement will be discarded
Grid-based Routing (1/2)
z What is Routing?
z Draw DRC-correct metal shapes for all interconnect wire while
maintaining circuit timing, clock skew, signal net transition and
capacitance limits
z Astro is a grid-based router
z Each metal layer has its own, possibly unique, grid and preferred
routing direction
z Metal shapes implementing wires will be centered on the grid
points
z A series of grid points in a line is called a metal “track” while
unoccupied, a trace when occupied
z Track spacing values are set in the technology file
Grid-based Routing (2/2)
track
trace
prBoundary row unitTile pitch channel
Design Rule Check or DRC
z Physical domain – mask design rules
z Wire spacing & width area check
z Via considerations
z Many other rules related to device (transistor) formation
z Built-in DRC is used for simple verification only, you
should use other tools for sign-off.
width check enclosure spacing check

outside spacing check inside spacing check
Wire Parasitic RC Extraction
z Astro contains an LPE (Layout Parasitic Extraction)
engine
z LPE automatically calculates wire parasitic RCs from wire
shape data
z Parasitic RC values are used to calculate the wire delays
for timing analysis
z After detailed routing, all wire RCs are re-calculated
using the actual metal shapes for the nets
z TLU or TLU+ models are used by LPE for wire delay
calculations
Route Operations in Astro
z There are 4 routing operations that Astro performs:
z Global Route Route Operations, relative run time
z Track Assignment 20
Detailed Route
18
z 16
14
z Search and Repair 12
10
8
6
4
2
0
Clk global Track Detail Route S&R
Route route Assign Route Opt
z Each clock and signal net is global routed, track assigned

and detailed routed
z Each clock and signal net may be rerouted during search
& repair
Global Route (1/2)
z During global route (Groute), Astro assigns nets to the
global routing cells (Gcell or GRcell) through which they
will pass. Groute avoids obstacles and makes routes
that do not create congested areas.
z The metal layer used for net routing in each Gcell is also
assigned during Groute.
z For each Gcell, routing capacity is calculated according
to the blockages, pins, and routing tracks inside the cell.
z Astro calculates the demand for wire tracks in each
global routing cell. This is the basis for congestion
analysis.
Global Route (2/2)
z Astro may reduce overloaded Gcells by detouring nets
around congested areas
z Detours increase wire length, hence increase wire delay
z Pre-routed wires are considered, block-ages to new
signal routes
z A new congestion map is available after Groute
Track Assignment
z Track assignment selects tracks within Gcells to be used
for routing each net
z Track assignment operates on the entire design at once
attempting to:
z Make long, straight routes
z Reduce the number of vias
z Net connection is complete, but many DRC violations are
expected (shorts)
Detail Route (1/2)
z Detailed route works to clear all the DRC violations left
by the track assignment stage
Track
Assignment
Global Route Detail Route
Detail Route (2/2)
z The detail router divides the chip area into switch boxes
z A switch box aligns SBox Boundary GCell Grid
to Gcell boundaries
z Each switch box is
overlapped with its
neighbor by 1 Gcell
z Detail router generates
the detailed routing one
switch box at a time
Search & Repair
z During S&R, Astro searches for design rule violations and
reroutes wires in an effort to fix them
z Multiple passes with different sized SBoxes are
conducted
z If DRC violations cannot be cleared in ~50 S&R loops:
z Check the GR congestion map
z If only a handful of errors remain, try cleaning them up
interactively with the axgQuickSignalRoute command
z Check layouts for unreachable pins
z Create or free up routing resources
z Floorplan changes
z Removing routing obstructions
General Flow for Routing
Placement & CTS
P/G Route Optimize Routing
Set Routing Options

Post-route CTO
ECO Route
Route Clock Nets
Global Route
Post-route Opt.
Global Route Opt.
In-route Opt.
Track Assign
Detail Route Design for

manufacturability
Search & Repair =
Routing
z P/G Route
z Set Routing Options
z Route Clock Nets
z Route Signal Nets
z Optimize Routing
z Post-route CTO
z Post-route Optimization
z In-route Optimization
Routing
z P/G Route
z Route Setup > Route Common Options
z Route Clock Nets
z Route Signal Nets
z Optimize Routing
z Post-route CTO
z ECO Route
Set Routing Options
z Select options to match the design requirements before
each routing command
To minimize clock skew,

Set Clock Routing option
to “balanced”.
Routing
z P/G Route
z Route Clock Nets
z Route > Route Net Group
z Route Signal Nets
z Optimize Routing
z Post-route CTO
z ECO Route
Route Clock Nets
z Skew control and insertion delay targets easier to meet if
these nets are routed first
z Command can also be used to route critical signals or
busses separately
Route all clock nets at once!
Routing
z P/G Route
z Route Clock Nets
z Route Signal Nets
z Route > Global Route & Route > Auto Route & Route >
Search and Repair
z Optimize Routing
z Post-route CTO
z ECO Route
Route Signal Nets
z Determine if GRoute optimization should be performed
z Auto-Route does not offer an option to run GRoute
optimization Global
z Auto-Route complete Route
GRoute, Track Assignment,
Detail Route in a slack < no GRoute
single step PPO 2 optimization
yes
Track
Auto- Assignment
Route
Detail Route
Global Route Optimization
z Perform setup time, hold time, max transition, max
capacitance fixing by cell sizing and buffer insertion.
Must either select “ECO Route”

option or re-run global route
after this optimization is completed
Routing
z P/G Route
z Route Clock Nets
z Route Signal Nets
z Optimize Routing
z Route > Post Route Optimization
z Post-route CTO
z ECO Route
Optimize Routing
z Optimize the routing by reducing wire length, the
number of vias, and removing unnecessary jogs
z If the process is new or unproven, the reduction in via
counts and increase in long straight routes may improve
yield
z Skip this step if timing is already met and the process is
mature
Routing
z P/G Route
z Route Clock Nets
z Route Signal Nets
z Optimize Routing
z Post-route CTO
z Clocks > Post Route CTO
z ECO Route
Post-route CTO
z Clock skew may have been disturbed by previous routing
and route optimization activity
z Do CTO only if preceding route or optimization activity
has perturbed the clock skew. You may consider it also
if timing is marginally negative and tightening the clock
skew might close timing.
z Can specify specific Clock Nets for optimization with
astClockOptions command
Routing
z P/G Route
z Route Clock Nets
z Route Signal Nets
z Optimize Routing
z Post-route CTO
z ECO Route
z ECO > ECO Route – Design ECO
Post-CTO ECO Route
z First, select CTS nets Æ “minor change only” in the
Route Common Option form
z No Track Assignment or GRoute is necessary, so
deselect them on the form
z To minimize disruption to existing routes:
z Select “utilize” for dangling wires
z Reroute “modified nets first”
Routing
z P/G Route
z Route Clock Nets
z Route Signal Nets
z Optimize Routing
z Post-route CTO
z ECO Route
z Route > Post Route Optimization
Post-route Optimization
z Do it if timing is not met or any trans/cap violations
z Performs cell sizing, buffer and inverter insertion
z Strong hold time fixing
z Topology based optimization
Routing
z P/G Route
z Route Clock Nets
z Route Signal Nets
z Optimize Routing
z Post-route CTO
z ECO Route
z Route > In Route Optimization
In-route Optimization
z Does “in-route” extraction:
z Fast incremental mode
z Runs/updates as routes change
z ~5% more pessimistic than normal post-route extraction
z Most useful for cross-talk fixes
z Used when a very small increase in timing performance
is required and other optimizations have stalled
z Can have a long runtime
Lab 1-6
Astro
DFM
General Astro Flow
Design
Design Setup
Setup Unit1
Unit1
Gate-level
Floorplanning Unit2
Unit2
Netlist
Netlist
Timing
Timing Setup
Setup Unit3
Unit3
Placement
Placement Unit4
Unit4
GDSII CTS
CTS Unit5
Unit5
GDSII
Layout
Routing Unit6
Design
Design for
for Manufacturing
Manufacturing Unit7
Unit7
Design state at the start of DFM
z Standard cells are placed
z Clock tree and HFN buffers placed
z All clock, signal and P/G nets have been completely
routed
z All route related optimizations are completed:
z Setup and Hold time: met
z Maximum capacitance limits - met
z Maximum signal transition times – met
z Design is DRC clean
Manufacturability Issues
z Astro can address several issues to increase
manufacturing yield:
z Gate Oxide integrity Æ antenna fixing
z Via resistance and reliability Æ extra contacts
z Metal erosion Æ metal slotting
z Metal liftoff Æ metal slotting
z Metal Over-Etching Æ metal fill
Problem: Gate Oxide Integrity
z Metal wires (antennae) placed in an EM field can
generate voltage gradients
z During the metal etch stage, strong EM fields are used
to stimulate the plasma etchant
z Resultant voltage gradients at MOSFET gates can
damage the thin oxide
• Oscillating charges in
Plasma Etch
Damaged Gate Oxide
Antenna Rules
z As length of wire increases during processing, the
voltage stressing the gate oxide increases
z Antenna rules define acceptable length of wires
Antenna Ratios:
Area of Metal Connected to Gate

Combined Area of Gate
Or
Area of Metal Connected to Gate
Combined Perimeter of Gate
gate
poly
diffusion
Solution 1: Splitting Metal or Layer Jumping
Before metal splitting
unacceptable antenna length
gate
driver
After metal splitting to meet Antenna rules
gate
driver
acceptable antenna length
Solution 2: Inserting Diodes
Before inserting diodes
• Diode Inhibits charge oscillation

in metal tracks
During etch phase, the diode clamps the voltage swings
Antenna Fixing Flow
Routing
Routing&&related
related
Routing & related
optimizations
Routing &&related
optimizations
Routing related
optimizations
optimizations
optimizations
Search & Repair

Route DRC Yes
violations?
No
Set antenna rules
Remaining Design
for
Search & Repair Manufacturability
Insert Antenna
Diodes for all
remaining violations
Via Resistance and Reliability
z Replacing one contact with multiple contacts can
improve yield & timing (series R reduction)
z Inserts multiple contacts without rerouting
extra
vias
added
Problem: Metal Erosion
z The wafer is made flat (planarized) by a process called
Chemical Mechanical Polishing (CMP)
z Metals are mechanically softer than dielectrics:
z CMP leaves metal tops with a concave shape - dishing
z The wider the metal the more pronounced the dishing
z Wide traces with little intervening dielectric and can become
quite thin – dishing this severe is called erosion
z Process rules specify maximum metal density per layer
to minimize erosion
Problem: Metal Liftoff
z Conductors and Dielectrics have different coefficients of
thermal expansion:
z Stress builds up with temperature cycling
z Metals can delaminate (lift off) with time
z Wide metal traces are more vulnerable than narrow ones
z Maximum metal density rules also address this issue
Metal thermal expansion
Metal
Dielectric
Dielectric thermal expansion
Solution: Metal Slotting
z Slotting wide wires reduces the metal density
z Slots minimize stress buildup, reducing liftoff tendency
z Primarily used on Power and Ground traces:
z Can apply to any other net if wide enough
z Slotting parameters can be set layer by layer
SideClearance OpenSlot SideSpace
Width EndSpace Length
Problem: Metal Over-Etching
z A narrow metal wire separated from other metal receives
a higher density of etchant than closely spaced wires
z The narrow metal can over-etch
z Minimum metal density rules are used to control this
Plasma Etchant
Less
etchant
per wire More
etchant
per wire
Solution: Metal Fill
z Fills empty tracks with metal shapes to meet the
minimum metal density rules
z Uses up most of the remaining routing resource:
z No further routing or antenna fixes can be done
Final Validation
From antenna and
DFM steps
Generate a Output GDS2 Generate Write .spef file

PARA view output netlist
Astro Calibre LEC PrimeTime
Validate Astro’s
Prove logical timing results
timing Detailed equivalence after
engine DRC & LVS. Astro optimizations
Final Validation: wire parasitics (PARA)
z Generate a PARA view using:
z Astro LPE or
z Star-RCXT called from Astro
z PARA contains extracted, parasitic RC values for nets
z PARA view is used inside Astro for:
z Timing, skew or crosstalk analysis
z Speeds up processing since no net RC re-extration is required
Final Validation: wire parasitics (spef)
z Wire parasitics for external STA are provided
via a .spef file
z The .spef file can be generated from the PARA view or
from the internal LPE of Astro:
z In the Timing Setup: Parasitic Tab select “LPE” or “DB”
Final Validation: Netlist Output
z Netlists for STA (Static Timing Analysis) do not require
output of “Physical only cells” like:
z Corner Pad Cells
z Pad/ Core Filler Cells
z Unconnected Cell instances
z Exception: Physical only cells are needed for LVS when
there are unconnected cell instances (spare cells)
z The top-level netlist generated from the EXP view is flat
Final Validation: Hierarchical Netlist Output
z Write out a hierarchical Verilog netlist
z Hierarchy must have been preserved before any:
z Netlist change
z HFN re-synthesis step
z CTS
z Logic or buffering optimization
z Hierarchical netlists allow re-use of existing test benches
for logic verification
Lab 1-7
Astro
CIC Specific Items

Outline
z Cell-based Design Kit provided by CIC
z Taped-out via CIC
z What should be prepared?
z Post-layout Physical Verification
z Design Rule Check (DRC), Electrical Rule Check (ERC)
z Layout Versus Schematic (LVS)
z Post-layout Function and Timing Verification

z Gate level
z Transistor level
z Post-layout Power Analysis

z Transistor level
CIC Provides
z 0.35um Cell-Based Design Kit (TSMC/TSMC)
z TSMC core and IO library for TSMC 0.35um process
z Apply memory blocks on CIC’s web site
z 0.18um Cell-Based Design Kit (UMC/Artisan)
z Artisan core and IO library for UMC 0.18um process
z Memory generator included
z 0.18um Cell-Based Design Kit (TSMC/Artisan)
z Artisan core and IO library for TSMC 0.18um process
z Memory generator included
0.35um CBDK (TSMC/TSMC)
z Location of Astro Library Data
z your_path/CBDK035_TSMC_TSMC/CIC/Apollo/
z File Descriptions
z PDS-030612-00-001.pdf Æ Application Notes
z stout.map Æ Layer Mapping File
z tsmc35_4lm.tf Æ Technology File
z tcb773p Æ Core Library
z tpz773pn Æ Digital IO Library
z tpz773pn_analog Æ Analog IO Library
z itfplus/t035p2p4mm.itf Æ Tech File
itfplus/t035p2p4mm.tluplus Æ TLU+ RC Model
itfplus/t035p2p4mm.map Æ Mapping File
z Location of Cell’s Documents
z your_path/CBDK035_TSMC_TSMC/CIC/doc/
0.35 TSMC/TSMC CBDK (P/G IO)
Power Pads PVDD1Z PVDD2Z PVDD3Z

Core VDD 9 9
IO VDD 9 9
Ground Pads PVSS1Z PVSS2Z PVSS3Z

Core VSS 9 9
IO VSS 9 9
0.35 TSMC/TSMC CBDK (Special Cells)
z Core Fillers
z FEED1, FEED2
z IO Fillers
z PFEED20Z, PFEED10Z, PFEED8Z, PFEED5Z, PFEED4Z, PFEED2Z,
PFEED1Z
z Overlapped IO Fillers
z PFEED1Z
z Buffers for CTS
z BUF6, BUF5, BUF4, BUF3, BUF2, BUF1
z Delay elements for CTS
z DEL5, DEL3, DEL2
z Corner Pad
z PCORNERZ
0.18um CBDK (UMC/Artisan)
z Location of Astro Library Data
z your_path/CBDK018_UMC_Artisan/CIC/Astro/
z File Descriptions
z PDS-030328-00-002.pdf Æ Application Notes
z stout.map Æ Layer Mapping File
z umc18_CIC.tf Æ Technology File
z umc18_fram Æ Core Library
z umc18io3v5v_5lm Æ IO Library
z itfplus/mixed18.itf Æ Tech File
itfplus/mixed18.tluplus Æ TLU+ RC Model
itfplus/mixed18.map Æ Mapping File
z Location of Cell Documents
z your_path/CBDK018_UMC_artisan/CIC/doc/
0.18 UMC/Artisan CBDK (P/G IO)
Power Pads PVDDC PVDDR

Core VDD 9
IO VDD 9
Ground Pads PVSSC PVSSR

Core VSS 9
IO VSS 9
0.18 UMC/Artisan CBDK (Special Cells)
z Core Fillers
z FILL64, FILL32, FILL16, FILL8, FILL4, FILL2, FILL1
z IO Fillers
z PFILL, PFILL_9, PFILL_1, PFILL_01
z Overlapped IO Fillers
z PFILL_01
z Buffers for CTS
z CLKBUFXL, CLKBUFX1, CLKBUFX2, CLKBUFX3, CLKBUFX4,
CLKBUFX8, CLKBUFX12, CLKBUFX16, CLKBUFX20
z Delay elements for CTS
z DLY1X1, DLY2X1, DLY3X1, DLY4X1
z Corner Pad
z PCORNER
Taped-out via CIC
z Before taped-out, make sure that
z your design is DRC clean.
z your design passes the black-box LVS check.
z your design meet the timing/power specification.
z When taped-out via CIC, prepare the following:
z GDSII layout of your design
z Calibre DRC report file
z Calibre LVS report file
z Post-layout timing/power verification result
z Specification files of used memories
z For 0.18 UMC/Artisan CBDK, 0.18 TSMC/Artisan CBDK
Post-layout Physical Verification (0.35 TSMC)
z DRC/ERC
z Calibre –drc –hier Calibre-drc-cur
modify the
LAYOUT PATH "./CHIP.gds" header
LAYOUT PRIMARY "CHIP“
SOURCE PRIMARY "CHIP"
SOURCE PATH "./CHIP.spi"
z LVS
z Add Texts for LVS in Astro
z dbAllowToAddPGIOText #t
z dbAddIOText (geGetEditCell) "pad" "netName" 40 20
z Select “Pin/Net Options Æ Output Net As Text” when streaming out.

z v2lvs –v CHIP_pr_lvs.vg –l tsmc35_lvs.v –o CHIP.spi –
s tsmc35_lvs.spi –c cic_ –n
z calibre –lvs –spice layout.spi –hier –auto Calibre-
lvs-cur
Post-layout Physical Verification (0.18 UMC)
z DRC/ERC
z Calibre –drc –hier Calibre-drc-cur
modify the
LAYOUT PATH "./CHIP.gds" header
LAYOUT PRIMARY "CHIP“
z LVS
z Add Texts for LVS in Astro
z dbAllowToAddPGIOText #t
z dbAddIOText (geGetEditCell) "pad" "netName" 103 20
z Select “Pin/Net Options Æ Output Net As Text” when streaming out.

z v2lvs –v CHIP_pr_lvs.vg –l umc18_lvs.v –o CHIP.spi
–s umc18_lvs.spi –c cic_ –n
z calibre –lvs –spice layout.spi –hier –auto
Calibre-lvs-cur
Post-layout Timing Verification
z Gate Level
z Output hierarchical Verilog netlist in Astro.
z Output SDF timing information in Astro.
z Proceed gate-level simulation as you did after synthesis.
z Transistor Level
z Must be done in CIC’s post-layout verification system (PVS)
z Apply for the PVS account in
z http://www2.cic.org.tw/WSAccount/index.html
z Portal
z telnet://queue.cic.org.tw
z Refer to the application note (PDS-031218-00-002.pdf) for
the detail
Replace Layout / LPE
z Qentry
–M {LPE}
–tech {UMC18|TSMC25|TSMC35}
–f GDSII
–T Top_cell_name
–s Ram_spce_filename
–t {ra1sd|ra1sh|ra2sd|ra2sh|rf2sh|18ra1sh_1|18ra1sh_2|18ra2sh}
–c {UMC18|TSMC25|TSMC35}
–i {UMC18|TSMC25|TSMC35}
–o Netlist_file_name
z Example:
z Qentry –M LPE –tech UMC18 –f CHIP.gds –T CHIP
–s RAM1.spec –t 18ra2sh –s RAM2.spec –t 18ra1sh_1
–s RAM3.spec –t 18ra1sh_2 –c UMC18 –i UMC18 –o
CHIP.netlist
z Use Qstat to check the status of your job.
z The result is stored in “result_#” directory.
Edit Files for Running Nanosim (1/2)
z Stimulus File
z (is=vec)(en=input.dat)(ot=CLOCK,START,IN[7:0]);
z Input Pattern File
z ; time CLOCK START IN[7:0]
radix 1 1 44
io i i ii
high 3.3
low 0.0
25 0 0 xx
50 1 0 xx
75 0 0 xx
100 1 1 ff
. . . . .
Edit Files for Running Nanosim (2/2)
z Spice Header File Æ Modify PVT
z .lib 'l18u18v.012' L18U_BJD
z .lib 'l18u18v.012' L18U18V_TT
z .lib 'l18u33v_g2.011' l18u33v_tt
z *epic tech="voltage 3.3“
z *epic tech="temperature 100"
z Configuration File
z bus_notation [ : ]
z set_node_v DVDD 3.3
z set_node_gnd DGND
z set_node_v VDD 1.8
z set_node_gnd GND
z print_node_logic CLOCK
z Refer to Nanosim Training course for the detail
Tricks to Get the Input Pattern File
z Add the following descriptions in your Verilog test bench:
z integer outf;
initial begin
outf = $fopen("input.dat");
. . . . .
$fclose(outf);
$finish;
end
always @(clock or start or in)

$fdisplay(outf,"%t %b %b
%h",$time,clock,start,in);
Running Nanosim
z Qentry
–M {NANOSIM}
–n {CHIP.io}
–nspice CHIP.netlist spice.header
–m Top_cell_name
–c {CHIP.cfg}
–z {CHIP.tech.z}
–o Output_file_name
–t Total_simulation_time
z Example:
z Qentry –M NANOSIM –n CHIP.io –nspice CHIP.netlist
spice.header –m CHIP –c CHIP.cfg –z CHIP.tech.z –o
UMC18 -t 100
z Use Qstat to check the status of your job.
z The result is stored in “result_#” directory.
View Simulation Result
z NOVAS nWave
z A waveform viewer which supports Nanosim output waveform
format.
z Environment setup
z unix% set path=($path /usr/debussy/bin)
z unix% setenv LM_LICENSE_FILE
5219@license_server_name
z Starting nWave
z unix% nWave &
z Refer to Debussy training course for the detail.
Power Analysis using Nanosim
z Add the following statement in the configuration file :
z report_node_powr <node_name>
z example : report_node_powr VDD
z Check nanosim.log
Current information calculated over the intervals:
0.00000e+00 - 1.00010e+03 ns
Node: VDD
Average current : -3.53355e+05 uA
RMS current : 3.53388e+05 uA
Current peak #1 : -4.54061e+05 uA at 6.78400e+02 ns

Current peak #2 : -4.34973e+05 uA at 4.00000e-01 ns
. . . . . .
Lab 1-8
Lab 2
Astro Laboratory Exercise
Design Preparation
unix% cp /**********/astro_lab_2004_07.tar.gz ~/ Æ ask the instructor

unix% gzip –dc astro_lab_2004_07.tar.gz | tar xvf -
Table I Lab1
DESIGN DATA FILE OR DIRECTORY
Gate Level Netlist ~/astro/Lab1/design_data/CHIP.vg
IO Constraint File ~/astro/Lab1/design_data/io.tdf
Timing Constraint File ~/astro/Lab1/design_data/CHIP.sdc
Technology File ~/astro/Lab1/tech/umc18_CIC.tf
(Add it by yourself)
Layer Mapping File ~/astro/Lab1/tech/stout.map
Antenna Rules ~/astro/Lab1/tech/antenna_rules.cmd
Reference Library (Memory) ~/astro/Lab1/ref_lib/hdsramsp512x32
Reference Library (Core) ~/astro/Lab1/ref_lib/umc18_fram
Reference Library (IO) ~/astro/Lab1/ref_lib/umc18io3v5v_5lm
TLU+ Data ~/astro/Lab1/star_rcxt/
Script Files ~/astro/Lab1/scripts/
Table II Lab2
DESIGN DATA FILE OR DIRECTORY
Gate Level Netlist ~/astro/Lab2/design_data/pmult32_syn.vg
IO Constraint File ~/astro/Lab2/design_data/iopin.tdf
Timing Constraint File ~/astro/Lab2/design_data/pmult32_pr.sdc
Running Directory ~/astro/Lab2/run/
Running Scripts ~/astro/Lab2/scripts/
Directory for Physical Verification ~/astro/Lab2/verify/
Environment Setup
unix% source ****************************** Æ ask the instructor
Chip Implementation Center – Design Service Department – Digital Technology Section 1

Lab1-1 Design Setup
1. Change directory to lab1_1

unix% cd ~/astro/Lab1/lab1_1
unix% Astro –cmdd logs/CHIP –logd logs/CHIP&
2. 建立新的 Library。
“ Library > Create ”
Library Name sparc
Technology File Name ../tech/umc18_CIC.tf
Hierarchy Separator .
Set Case Sensitive Enable
按 OK。
3. 加入 Reference Library，包括 umc18 的 standard cell、io pad、sram 的 library。

“ Library > Add Ref ”
Library Name sparc
Ref Library Name ../ref_lib/umc18_fram
按 Apply。
Library Name sparc

Ref Library Name ../ref_lib/umc18io3v5v_5lm
按 Apply。
Library Name sparc

Ref Library Name ../ref_lib/hdsramsp512x32
按 OK。
檢查 library 是否加入正確。
“ Library > Show Refs ”
Library Name sparc
按 OK。

4. “ Tools > Data Prep ”
“ Netlist In > Verilog In ”
Verilog File Name ../design_data/CHIP.vg
Verilog List File Name
Library Name sparc
Tech File Name
HDL To GDSII Map File
Bus Naming Style [%d]
Verilog Model Directory
Model File Extension .v, .V
Net Name for 1’b0 GND
Net Name for 1’b1 VDD
Hierarchy Seperator .
Bus Name Append
Multiple PG Nets Disable
No Backslash Insertion to avoid Hier Name Collisions Disable
Remove First Backslash Of All Escaped Identifiers Disable
Create Bus for Undefined Cells From Connect
按 OK。
檢查 sparc library 裡是否多了 NETL 的資料夾。
5. Expand the Netlist

“ Netlist In > Expand ”
Library Name sparc
Unexpanded Cell Name CHIP.NETL
Expanded Cell Name CHIP.EXP
Precede hierarchical names with “/” Disable
Expand netlist cell with no instance Enable
Stop at FRAM view cells only Disable
Print out net has a pin but no connections Disable
按 Global Net Options。
Mode Add
Net Name VDD
Port Pattern VDD
按 Apply，分別加入 VDD、GND，每加入一個，Number Defined 會加 1。加完最後一個之後，
按 Hide，再按 OK 。
Expand 結束後 sparc 裡會多出一個 EXP 的資料夾。

6. 開啟 Library 並建立新的 Cell
“ Tools > Astro ”
“ Library > Open ”
Library Name sparc
Library Path
按 OK。
“ Cell > Create ”

Cell Name CHIP
按 OK。
此時會開啟一個新的 CELL window。
7. 將 CHIP.EXP bind 到 CHIP.CEL 中

“ Design Setup > Bind Netlist ”
Net Cell CHIP.EXP
按 OK。
在 CELL window 上按 “ f ”，看看 design 是否有 bind 進來。
8. 保留 Hierarchy 名稱，以便 post-layout simulation 時不需再改 test bench。

“ Cell > Initialize Hierarchy Information ”
Flattened Cell Name (.EXP .CEL) CHIP.CEL
Hierarchical Top Cell Name (.NETL) CHIP.NETL
按 OK。
“ Cell > Mark Module Instances Preserved ”

Preserve Hierarchical Boundary for: All Module Instances
按 OK。
“ Cell > Save! ”

“ Cell > Save As ”
Cell Name CHIP_design_setup
overwrite Enable
按 OK。

Lab1-2 Floorplanning

2. “ Library > Open ”

Library Name sparc
Library Path
按 OK。
“ Cell > Open ”

Cell Name CHIP
按 OK。
3. 規劃 IO Pad 腳位擺放方向及位置，並編輯 io.tdf 檔供 floorplan 用(已編輯完畢)。

1 5 10 15 20 25 30 32
ipad_WATCH_RAM
ipad_WATCH_PC
ipad_DATAIN23
ipad_DATAIN24
ipad_DATAIN25
ipad_DATAIN26
ipad_DATAIN27
ipad_DATAIN28
ipad_DATAIN29
ipad_DATAIN30
ipad_DATAIN31
ipad_ADDRIN0
ipad_ADDRIN1
ipad_ADDRIN2
ipad_ADDRIN3
ipad_ADDRIN4
ipad_ADDRIN5
ipad_ADDRIN6
ipad_ADDRIN7
ipad_ADDRIN8
ipad_ADDRIN9
ipad_RESET
core_vdd1
core_vss1
ipad_TM
io_vdd1
io_vdd2
io_vdd3
io_vss1
io_vss2
io_vss3
33 cornerUL cornerUR
io_vss12
ipad_DATAIN22 io_vdd4 32
30 ipad_DATAIN21 opad_BYPASS_OUT
ipad_DATAIN20 opad_TEST_SO 30
ipad_DATAIN19 opad_Finish
io_vdd12 opad_DATAOUT31
ipad_DATAIN18 io_vss4
25 ipad_DATAIN17 opad_DATAOUT30
ipad_DATAIN16 opad_DATAOUT29 25
ipad_DATAIN15 opad_DATAOUT28
io_vss11 opad_DATAOUT27
ipad_DATAIN14 io_vdd5
core_vss4 Core opad_DATAOUT23
core_vdd4 core_vdd2
15 ipad_CLOCK core_vss2
io_vdd11 io_vss5
io_vss10 io_vdd6
1 io_vdd10 io_vss6
ipad_WATCH_REG
ipad_LOAD_INSTR
opad_DATAOUT10
opad_DATAOUT11
ipad_LOAD_RAM
opad_DATAOUT0
opad_DATAOUT1
opad_DATAOUT2
opad_DATAOUT3
opad_DATAOUT4
opad_DATAOUT5
opad_DATAOUT6
opad_DATAOUT7
opad_DATAOUT8
opad_DATAOUT9
ipad_BYPASS_IN
ipad_TEST_SE
ipad_BistMode
opad_BistFail0
opad_BistFail1
opad_ErrMap0
opad_ErrMap1
ipad_TEST_SI
core_vdd3
core_vss3
io_vdd9
io_vdd8
io_vdd7
io_vss9
io_vss8
io_vss7
1
cornerLL cornerLR
1 5 10 15 20 25 30 32

umc018 使用的 P/G Pad、I/O Pad 和 Corner 名稱
core pad PVDDC, PVSSC
io pad PVDDR, PVSSR
corner PCORNER
input P2A
output P8A
由於 gate level netlist 並未加入 P/G Pad 和 Corner 的 Cell，所以必須在 tdf 中建立這些 cell，其
範例如下，其中 core_vdd1、core_vdd2、ipad_DATAIN0 等為 Instance Name，"left" 1 為其擺放
位置及順序。
io.tdf 檔(已編輯完畢)
define _cell (geGetEditCell)
dbCreateCellInst _cell "" "PVDDC.FRAM" "core_vdd1" "0" "NO" '(0.0 0.0)
dbCreateCellInst _cell "" "PVDDC.FRAM" "core_vdd2" "0" "NO" '(0.0 0.0)
…….
dbCreateCellInst _cell "" "PVSSC.FRAM" "core_vss1" "0" "NO" '(0.0 0.0)
…….
dbCreateCellInst _cell "" "PVDDR.FRAM" "io_vdd1" "0" "NO" '(0.0 0.0)
…….
dbCreateCellInst _cell "" "PVSSR.FRAM" "io_vss1" "0" "NO" '(0.0 0.0)
…….
;;left
pad "io_vdd10" "left" 1
pad "ipad_DATAIN0" "left" 2
pad "io_vss10" "left" 5
…….
pad "cornerUL" "left" 33
;;right
pad "cornerLR" "right" 1
…….
;;top
pad "io_vdd1" "top" 1
…….
pad "cornerUR" "top" 32
;;bottom
pad "cornerLL" "bottom" 1
…….
pad "io_vdd7" "bottom" 32

4. 讀取 IO Constraints
“ Design Setup > Load TDF ”
Cell Name
TDF File Name ../design_data/io.tdf
Overwrite Enable
按 OK。
5. Floorplan 設定
“ Design Setup > Set Up Floorplan ”
Control Param aspect ratio
Core Utilization 0.8
Row/Core Ratio 1
Core Aspect Ratio(H/W) 1
Horizontal Row Enable
Double Back Enable
Start First Row Disable
Flip First Row Enable
Core To Left 200
Core To Right 200
Core To Bottom 200
Core To Top 200
按 OK。

6. 設定 macro 內部的 pin 為 visible
點選 CHIP.CEL 視窗左邊的 Window option。
Visible Pin Instances macro cell
按 Apply 後再按 Redraw，然後關閉 Window Options 視窗，此時就可看見 macro 內的 power ring
和 pin 的 layout。
7. 將 macro 擺放到 core region

“ Select > Select by Point ” (bind keys : p )，點選其中一個 hard macro，利用“ Modify >
Move ” (bind keys : m ) 或 “ Modify > Transform ” (bind keys : t ) 將 macro 移動或翻轉
至適當位置(macro 的 pin 朝向 core 內部)。
8. 建 Power Ring 及 Straps

“ PreRoute > Connect Ports to P/G ”
將 VDD, GND 分別填入，注意 Net Type 的區別。
Net Name VDD
Port Pattern VDD
Cell Master Pattern .*
Cell Instance Pattern .*
Net Type Power
Net SubType Core Pad
Cell Types Macro, Std/Module Cell, Pad
Update Tie Up/Down Disable
Mode Connect
Create Missing Ports Enable
按 Apply。此時會跳出一個 Dialog Box 視窗，按 OK。

Net Name GND
Port Pattern GND
Net Type Ground
Update Tie Up/Down Enable
Mode Connect
按 OK。此時會跳出一個 Dialog Box 視窗，按 OK。
“ PreRoute > Rectangular Rings ”

Around Core
Net Name(s) VDD, GND
Skip Side(s)
L-Width / L-Layer 60 / 52
R-Width / R-Layer 60 / 52
B-Width / B-Layer 60 / 50
T-Width / T-Layer 60 / 50
Offsets Are Absolute
Offsets Left 30
Offsets Right 30
Offsets Bottom 30
Offsets Top 30
All other options Default value
按 OK。

“ PreRoute > Straps ”
Direction Vertical
Start X 900
Width 30
Layer 52
Configure By Groups & Step
Groups 1
Step 0.0
Pitch within Group 30.32
Low Ends At First Targets
High Ends At First Targets
Place Straps 3
X Increment 330
按 DRC。
Spacing Rule Are Radial

Treat Fat Blockages as Thin Wires Enable
Use Fat Via If Width Meets Requirement Enable
按 Hide，再按 OK。
9. I/O Pad 到 Power Ring 及 Macro Ring 到 Power Ring 的連接。

“ PreRoute > Macros/Pads ”
Instance Type(s) Pad
Select Pins Automatically and Route All but Specified
Primary Routing Layer Specified
Horizontal Layer 50
Vertical Layer 48
按 OK。

選取右上角的 macro ( bind keys : p )。
“ PreRoute > Macros/Pads ” 先按 Default
Instance Type(s) Macro
Instances Selected
Skip Side(s) Bottom
Select Pins Automatically and Route All
Primary Routing Layer Preferred
按 OK。
按 CHIP.CEL 視窗左邊的 Deselect-all。
選取右下角的 macro。
“ PreRoute > Macros/Pads ”
Instance Type(s) Macro
Instances Selected
Skip Side(s) Top
Select Pins Automatically and Route All
Primary Routing Layer Preferred
按 OK。
按 CHIP.CEL 視窗左邊的 Deselect-all。
10. 建立 Placement Blockage 在 macro 周圍

“ PrePlace > Create Hard Blockage ”
直接在 CELL Window 上面建立 Placement Blockage 範圍。

11. “ Cell > Save! ”
Cell Name CHIP_floorplan
overwrite Enable
按 OK。

Lab1-3 Timing Setup


Library Name sparc
Library Path
按 OK。
“ Cell > Open ”

Cell Name CHIP
按 OK。
3. Attach TLU+ to MilkyWay Database

“ Tools > DataPrep ”
“ Tech File > ITF to TLU+ ”
Library Name sparc
delete all capacitance tables Enable
LPE Mode NOM
Nom Cap Table File ../star_rcxt/mixed18.tluplus
Nom ITF File ../star_rcxt/mixed18.itf
Star-RCXT Mapping File ../star_rcxt/mixed18.map
按 OK。
4. Configuring Timing Setup Panel

“ Timing > Timing Setup ”
選取 Environment tab
Ignore Interconnect Disable
Ignore Clock Uncertainty Disable
Enable Time Borrowing Enable
Ignore Propagated Clock Enable
Enable Ideal Network Delay Enable
設定完記得先按 Apply ，再選取 Parasitics tab。
Operating Cond Max, Min

Capacitance Model TLU+
按 Apply，再選取 Model tab。

Delay Model Elmore
按 Apply，再按 Hide 關閉 Timing Setup Pannel。
5. Load Synopsys Design Constraints (已編輯完畢)

CHIP.sdc 檔
set sdc_version 1.2
create_clock -period 20 -name CLOCK -waveform {0 10} [get_pins {ipad_CLK/Y}]

set_clock_uncertainty 1 -setup [get_clocks {CLOCK}]
set_clock_latency 1 [get_clocks {CLOCK}]
set_input_delay 1.5 -clock "CLOCK" [get_ports [all_inputs]]

set_output_delay 2.5 -clock "CLOCK" [get_ports [all_outputs]]
set_drive 1 [get_ports [all_inputs]]

set_load -pin_load 1 [get_ports [all_outputs]]
set_load -min -pin_load 1 [get_ports [all_outputs]]
在 Message/Input Area 輸入 ataRemoveTC
“ Timing > Load SDC ”

SDC File Name ../design_data/CHIP.sdc
SDC File Bus Naming Style [%d]
SDC File Hierarchy Separator /
按 OK。
確認是否全部的 constraints 都有下到。

“ Timing > Timing Data Check ” Default 值，按 OK。

Cell Name CHIP_timing
overwrite Enable
按 OK。

Lab1-4 Placement


Library Name sparc
Library Path
按 OK。
“ Cell > Open ”

Cell Name CHIP
按 OK。
3. Detach Scan Chain，因為 Scan Chain 會造成高的 congestion。

“ PrePlace > Trace Scan Chain ”
Start Port Name Y
Of cell instance
Instance Name ipad_TEST_SI
Allow Buffers Enable
Buffer Master Name(s) .*INV.*, .*BUF.*
Allow Muxes Disable
Mux Master Name(s)
Specify Chain End Enable
End Port Name A
End Instance Name opad_TEST_SO
按 OK。
“ PrePlace > Optimize/Delete Scan Chain ”

Chain Name .*
Pattern match Enable
Option Allow New Module Ports
Mode Delete only
按 OK。

4. Pre-Placement
“ InPlace > Placement Common Options ”
Optimization Mode Congestion, Timing
No Cells under Preroute of M1, M2, M3, M4, M5
按 OK。
“ PrePlace > Pre-Placement Optimization ” Default 值，按 OK。
“ Timing > Timing Report ” Default 值，按 OK。

Setup Slack Hold Slack Num Num
Slack Num Slack Num Trans MaxCap
5. “ PreRoute > Connect Ports to P/G ”

Net Name VDD
Port Pattern VDD
Net Type Power
Mode Connect
按 Apply。
Net Name GND

Port Pattern GND
Net Type Ground
Mode Connect
按 OK。

“ PreRoute > Standard Cells” Default 值，按 OK。
6. InPlace
“ InPlace > Design Placement ”
Speed medium
Mode congestion + timing
In-Placement Optimization Enable
Routability v.s. Timing bar 5
按 OK。
7. 觀察 Congestion 及 Critical Path

“ InPlace > Display Timing Map ” 按 Clear，再按 Cancel。
“ InPlace > Display Congestion Map ” 按 Apply，如果沒問題按 Clear，再按 Cancel。


8. “ PostPlace > Post-Place Optimization Phase 1 ”
Optimization Effort LOW
Re-do HFN Synthesis Enable
Using Global Routing Enable
Setup Fixing Enable
Hold Fixing Disable
Design Rule Fixing Enable
Fix Max Length Disable
Fix Tran/Cap Enable
Prevent Xtalk Disable
按 OK。


Cell Name CHIP_placed
overwrite Enable
按 OK。

Lab1-5 CTS (Clock Tree Synthesis)


Library Name sparc
Library Path
按 OK。
“ Cell > Open ”

Cell Name CHIP
按 OK。
3. “ Clock > Clock Common Options ” Default 值，按 OK。
4. “ Clock > Clock Tree Synthesis ” Default 值，按 OK。
5. 在 Message/Input Area 輸入 “ atCmdFreeTimer ” 來更新 timing view。
6. “ Clock > Skew Analysis ” Default 值，按 OK。

Global Skew Longest Delay Shortest Delay
CLOCK
7. “ Timing > Timing Setup ”

Ignore Clock Uncertainty Enable
Ignore Propagated Clock Disable
Enable Ideal Network Delay Disable

8. 重新連接 Scan Chain
“ PrePlace > Optimize/Delete Scan Chain ”
Chain Name .*
Pattern match Enable
Option Allow New Module Ports
Mode Optimize
按 OK。
9. “ Timing > Timing Report ” Default 值，按 OK。

10. “ PostPlace > Post Placement Optimization ” Default 值
11. “ Timing > Timing Report ” Default 值


Cell Name CHIP_cts
overwrite Enable
按 OK。

Lab1-6 Routing


Library Name sparc
Library Path
按 OK。
“ Cell > Open ”

Cell Name CHIP
按 OK。
3. 在 Placement Optimization 時有些 gate 或 buffer 可能被加入或拿掉，所以必須重新再作一次

Power/Ground Connection。
“ PreRoute > Standard Cells ” Default 值，按 OK。
4. “ Route Setup > Route Common Options ”

Global Routing Timing Driven
Clock Routing balanced
Track Assign Timing Driven
Detail Routing connect tie off,
connect open nets
Same Net Notch check and fix
按 OK。
5. “ Route > Route Net Group ”

Net Name(s) From: All clock nets
Phase global, track assign, detail
Search Repair Loop 5
Dangling wires Discard
Optimize routing pattern Enable
“ Route > Global Route ” Default 值，按 OK。

7. 觀察 congestion 情況
“ Route > Estimate Global Route Congestion! ”
“ Route > Display Congestion Map ” 按 Apply，如果沒問題按 Clear，再按 Cancel。
congestion 結果 ok，則不需作 Global Route Optimization。
8. “ Route > Auto Route ” Default 值，按 OK。

選取 Model tab
Delay Model AWE
按 Apply。

11. 若有 DRC violations，則需使用 Search & Repair 去修正。

“ Route > Search and Repair ”
按 OK。
12. 作最後的 Optimize

“ Route > Post Route Optimization ” Default 值，按 OK。


Cell Name CHIP_routing
overwrite Enable
按 OK。

Lab1-7 DFM (Design for Manufacturing)


Library Name sparc
Library Path
按 OK。
“ Cell > Open ”

Cell Name CHIP
按 OK。
3. 加入 Antenna Rules (已修改完畢)
antenna_rules.cmd
define _libId (dbGetCurrentLibId)
dbDefineAntennaRule _libId 2 2 0 0
dbAddAntennaLayerRule _libId 2 "met1" 400 '(0.359 0 0 999999999)
在 Message/Input Area 輸入 load “../tech/antenna_rules.cmd ” 加入 antenna rules。
“ Route Setup > HPO Signal Route Options ” 設定 antenna ratio 的計算模式
Timing-Driven Spacing Off
Change-Collecting Antenna advanced
按 OK。
在 Message/Input Area 輸入 axReportAntennaRatio (geGetEditCell)

如果有出現 violation (紅色框框的地方)，必須用 Search & Repair 修正。
“ Route > Search and Repair ” Default 值，按 OK。
輸入 axReportAntennaRatio (geGetEditCell) 確認 violation 是否還存在。
4. 加入 Pad Filler 和 Core Filler

“ PostPlace > Add Pad Fillers ”
Filler PFILL, PFILL_9, PFILL_1, PFILL_01
Overlap Filler PFILL_01
Side left, right, bottom, top
按 OK。
“ PostPlace > Add Core Fillers ”

Master Cell Name(s) Without Metal FILL64, FILL32, FILL16, FILL8,
FILL4, FILL2, FILL1
Master Cell Name(s) With Metal
respect hard placement blockage Enable
respect soft placement blockage Enable
between std cells only Enable
Connect to Power Net (optional) VDD
Connect to Ground Net (optional) GND
按 OK。
5. “ PreRoute > Standard Cells ” Default 值，按 OK。
6. 將單一個 via 置換成 2 個 via，作 contacts optimization

在 Message/Input Area 輸入 load “../scripts/optContacts.cmd”

optContacts.cmd (已編輯完畢)
axDrouteOptimizeContact (geGetEditCell) '(
("Via1" "Via1" 2)
("Via2" "Via2" 2)
("Via3" "Via3" 2)
("Via4" "Via4" 2)
)
7. “ Route > Search and Repair ” Default 值，按 OK。
8. 由於 Power Net 的寬度過大，違反 metal density rules。

“ PreRoute > Slot Wires ”
Select Wires Specified
CutWidth 20
CutLength 30
Width 2
Length 10
Side Space 10
EndSpace 10
Side Clearance 10
End Clearance 10
Stagger Enable
Treat Width as Minimum
Treat Length as Minimum
Treat Spaces and Clearances as Maximum
按 OK。
9. “ Route Utility > Fill Notch/Gap ” Default 值，按 OK。
10. “ Verify > DRC ” Default 值，按 OK。
11. “ Verify > LVS ” Default 值，按 OK。
12. 作 Calibre LVS 跟 Post Layout Simulation 時要在 layout 上加上 Text 才會正確。
在 Message/Input Area 輸入 load “../scripts/add_text.cmd”
add_text.cmd (已編輯完畢)
dbAllowToAddPGIOText #t
dbAddIOText (geGetEditCell) "*" "*" 103 20

Cell Name CHIP_dfm
overwrite Enable
按 OK。
14. Stream Out GDS II

“ Tools > Data Prep ”
“ Output > Stream Out ”
注意 Output Net 中一定要選取 As Text，否則 LVS 會有問題。
Stream File Name CHIP.gds
Library Name sparc
Layer File ../tech/stout.map
Child Extraction Depth 20
Convert Specified Cell
Cell Name CHIP
Convert Reference Lib Child Cells Enable
Flatten Devices & Device Arrays
Fill FILL
Pin/Net Options > Output Pins As Text
Pin/Net Options > Output Net As Text
按 OK。
15. SDF OUT

“ Timing > SDF Out ”
Specify Version Version 2.1
Operation Mode Normal SDF
File Name CHIP.sdf
按 OK。
16. Verilog Out

PS：若無法 dump verilog netlist，必須重新修復 net 和 instance 的連線(CHIP.CEL 要先關閉後才
能執行此動作)。
“ Cell > Repair Hierarchy Information ”
Flattened Cell Name(.CEL) CHIP.CEL
Repair net connections and instances Enable
按 OK。

“ Cell > Hierarchical Verilog Out ” ----for post layout simulation
Enter File Name CHIP_sim.vg
No power/ground ports Enable
No power/ground nets Disable
Output bus as individual bits Disable
No empty Cell Module Definitions Enable
No Corner Pad Instances Enable
No Pad Filler Cell Instances Enable
No Core Filler Cell Instances Enable
No Unconnected Cell Instances Enable
No Unconnected Ports Enable
Strip BackSlash Before Hierarchy Separator Enable
No Diode Ports Enable
Output Wire Declaration Enable
Output 1’b1 for Power(VDD, vdd, …) and 1’b0 for Ground(VSS, gnd, …) Enable
1’b1 Net Name VDD
1’b0 Net Name GND
Generate macro definitions Disable
按 OK。
“ Cell > Hierarchical Verilog Out ” ----for caliber block box LVS
Enter File Name CHIP_lvs.vg
No Corner Pad Instances Disable
No Pad Filler Cell Instances Disable
No Core Filler Cell Instances Disable
No Unconnected Cell Instances Disable
No Unconnected Ports Disable
No Diode Ports Disable
Output 1’b1 for Power(VDD, vdd, …) and 1’b0 for Ground(VSS, gnd, …) Disable
按 OK。

Lab1-8 Calibre DRC & LVS & Post-Layout Simulation
1. Change directory to lab1_8/drc

unix% cd ~/astro/Lab1/lab1_8/drc
2. 複製 DRC 相關檔案至 drc 的資料夾

Calibre-drc-cur Design Kit
180nm_layers.cal Design Kit
metal_slot_0.18_1P6M-MMC-Calibre-drc-2.2-p1 Design Kit
CHIP.gds Astro
unix% cp ~/astro/Lab1/lab1_7/CHIP.gds .
3. 修改 Calibre-drc-cur 檔
LAYOUT PATH "./CHIP.gds"
LAYOUT PRIMARY "CHIP"
4. 執行 Calibre DRC
unix% calibre –drc –hier Calibre-drc-cur
觀察 drc.sum 檔看看是否有 drc error
若有 error 則用
unix% calibre –rve drc.db

可找到 drc 錯誤的數量、原因、坐標等資訊，再回到 Astro 去作修正。
5. Change directory to lab1_8/lvs

unix% cd ~/astro/Lab1/lab1_8/lvs
6. 複製 LVS 相關檔案到 lvs 資料夾

CHIP.gds Astro
CHIP_lvs.vg Astro
umc18_lvs.spi Design Kit
umc18_lvs.v Design Kit
Calibre-lvs-cur Design Kit
unix% cp ~/astro/Lab1/lab1_7/CHIP.gds .
unix% cp ~/astro/Lab1/lab1_7/CHIP_lvs.vg .
7. 產生 RAM Black Box 的 Verilog 和 Spice 檔

修改原來的 hdsramsp512x32.v 檔，只留下 module 和 input、output 的宣告。
hdsramsp512x32_lvs.v (已編輯完畢)
module hdsramsp512x32 (
Q,
CLK,
CEN,
WEN,
A,
D,
OEN
);
output [31:0] Q;
input CLK;
input CEN;
input WEN;
input [8:0] A;
input [31:0] D;
input OEN;
endmodule
利用 v2lvs 產生 hdsramsp512x32_lvs.spi 檔
unix% v2lvs –v hdsramsp512x32_lvs.v –o hdsramsp512x32_lvs.spi

hdsramsp512x32_lvs.spi
$ Spice netlist generated by v2lvs
$ v9.3_1.4 Wed Mar 12 15:25:10 PST 2003
.SUBCKT hdsramsp512x32 Q[31] Q[30] Q[29] Q[28] Q[27] Q[26] Q[25] Q[24] Q[23]
+ Q[22] Q[21] Q[20] Q[19] Q[18] Q[17] Q[16] Q[15] Q[14] Q[13] Q[12] Q[11] Q[10]
+ Q[9] Q[8] Q[7] Q[6] Q[5] Q[4] Q[3] Q[2] Q[1] Q[0] CLK CEN WEN A[8] A[7] A[6]
+ A[5] A[4] A[3] A[2] A[1] A[0] D[31] D[30] D[29] D[28] D[27] D[26] D[25] D[24]
+ D[23] D[22] D[21] D[20] D[19] D[18] D[17] D[16] D[15] D[14] D[13] D[12] D[11]
+ D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] OEN
.ENDS
8. 將 CHIP_lvs.vg 轉換成 spice 格式

unix% v2lvs –v CHIP_lvs.vg –l umc18_lvs.v –l hdsramsp512x32_lvs.v –o CHIP.spi \
–s umc18_lvs.spi –s hdsramsp512x32_lvs.spi
9. 修改 Calibre-lvs-cur
LAYOUT PRIMARY "CHIP"

LAYOUT PATH "./CHIP.gds"
並在最後新增一行
LVS BOX hdsramsp512x32
10. 執行 Calibre LVS

unix% caliber –lvs –spice CHIP.spi –hier –auto Calibre-lvs-cur
觀察 lvs.rep 找到 OVERALL COMPARISON RESULT 部份是否 match
11. Change directory to lab1_8/tbench

unix% cd ~/astro/Lab1/lab1_8/tbench

12. 複製相關檔案到 tbench 資料夾
CHIP_sim.v Astro
CHIP.sdf Astro
Hdsramsp512x32.v Memory Compiler
umc18.v Design Kit
umc18io3v5v.v Design Kit
IRAM.bin Input Pattern
run.f Simulation Script File
test_postsim.v Testbench File
Checkfile3.golden Simulation results (golden)
unix% cp ~/astro/Lab1/lab1_7/CHIP.sdf .
unix% cp ~/astro/Lab1/lab1_7/CHIP_sim.v .
13. 編輯 run.f
../test_postsim.v
../hdsramsp512x32.v
../CHIP_sim.v
-v ../umc18.v
-v ../umc18io3v5v.v
+access+r
14. Change directory to lab1_8/tbench/run

unix% cd ~/astro/Lab1/lab1_8/tbench/run
15. unix% ncverilog –f ../run.f
simulation 結束後比對 checkfile3 和 checkfil3.golden 檔。

unix% diff checkfile3 ../checkfile3.golden
若兩個檔案一模一樣，表示 post-layout simulation 沒問題。

Lab2 Physical Design of a Pipelined 32x32 Multiplier
1. Change directory to Lab2/run

unix% cd ~/astro/Lab2/run
unix% Astro –cmdd logs/mul –logd logs/mul&
2. 建立新的 Library。
“ Library > Create ”
Library Name mul
Technology File Name ../tech/umc18_CIC.tf
Hierarchy Separator .
按 OK。
3. 加入 Reference Library，包括 umc18 的 standard cell 的 library。

“ Library > Add Ref ”
Library Name mul
Ref Library Name ../ref_lib/umc18_fram
按 Apply。
檢查 library 是否加入正確。
“ Library > Show Refs ”
Library Name mul
按 OK。
4. “ Tools > Data Prep ”

“ Netlist In > Verilog In ”
Verilog File Name ../design_data/pmult32_syn.vg
Library Name mul
Bus Naming Style [%d]
Model File Extension .v, .V
Net Name for 1’b0 GND
Net Name for 1’b1 VDD
Hierarchy Seperator .
Multiple PG Nets Disable
No Backslash Insertion to avoid Hier Name Collisions Disable
Remove First Backslash Of All Escaped Identifiers Disable
Create Bus for Undefined Cells From Connect
按 OK。檢查 sparc library 裡是否多了 NETL 的資料夾。

5. Expand the Netlist
“ Netlist In > Expand ”
Library Name mul
Unexpanded Cell Name pmult32.NETL
Expanded Cell Name pmult32.EXP
Precede hierarchical names with “/” Disable
Expand netlist cell with no instance Enable
Stop at FRAM view cells only Disable
Print out net has a pin but no connections Disable
按 Global Net Options。
Mode Add
Net Name VDD
Port Pattern VDD
按 Apply，分別加入 VDD、GND，每加入一個，Number Defined 會加 1。加完最後一個之後，
按 Hide，再按 OK 。 Expand 結束後 sparc 裡會多出一個 EXP 的資料夾。
6. 開啟 Library 並建立新的 Cell

“ Library > Open ”
Library Name mul
Library Path
按 OK。
“ Cell > Create ”

Cell Name pmult32
按 OK。
此時會開啟一個新的 CELL window。
7. 將 CHIP.EXP bind 到 CHIP.CEL 中

“ Design Setup > Bind Netlist ”
Net Cell pmult32.EXP
按 OK。
在 CELL window 上按 “ f ”，看看 design 是否有 bind 進來。
8. 保留 Hierarchy 名稱，以便 post-layout simulation 時不需再改 test bench。

“ Cell > Initialize Hierarchy Information ”
Flattened Cell Name (.EXP .CEL) pmult32.CEL
Hierarchical Top Cell Name (.NETL) pmult32.NETL
按 OK。

“ Cell > Mark Module Instances Preserved ”
Preserve Hierarchical Boundary for: All Module Instances
按 OK。

Cell Name mul_design_setup
overwrite Enable
按 OK。
10. 讀取 IO Constraints
“ Design Setup > Load TDF ”
Cell Name
TDF File Name ../design_data/iopin.tdf
Overwrite Enable
按 OK。
11. Floorplan 設定
“ Design Setup > Set Up Floorplan ”
Control Param aspect ratio
Core Utilization 0.7
Row/Core Ratio 1
Core Aspect Ratio(H/W) 1
Horizontal Row Enable
Double Back Enable
Start First Row Enable
Flip First Row Disable
Core To Left 70
Core To Right 70
Core To Bottom 70
Core To Top 70
按 OK。
12. 建 Power Ring 及 Straps

“ PreRoute > Connect Ports to P/G ”

Net Name VDD
Port Pattern VDD
Net Type Power
Mode Connect
按 Apply。此時會跳出一個 Dialog Box 視窗，按 OK。
Net Name GND

Port Pattern GND
Net Type Ground
Mode Connect
按 OK。此時會跳出一個 Dialog Box 視窗，按 OK。
“ PreRoute > Rectangular Rings ”

Around Core
Skip Side(s)
L-Width / L-Layer 30 / 52
R-Width / R-Layer 30 / 52
B-Width / B-Layer 30 / 50
T-Width / T-Layer 30 / 50
Offsets Are Absolute
Offsets Left 5
Offsets Right 5
Offsets Bottom 5
Offsets Top 5
按 OK。

Cell Name mul_floorplan
overwrite Enable
按 OK。
14. Attach TLU+ to MilkyWay Database

“ Tools > DataPrep ”
“ Tech File > ITF to TLU+ ”
Library Name mul
delete all capacitance tables Enable
LPE Mode NOM
Nom Cap Table File ../star_rcxt/mixed18.tluplus
Nom ITF File ../star_rcxt/mixed18.itf
Star-RCXT Mapping File ../star_rcxt/mixed18.map
按 OK。
15. Configuring Timing Setup Panel

“ Timing > Timing Setup ”
Ignore Clock Uncertainty Disable
Ignore Propagated Clock Enable
Enable Ideal Network Delay Enable
設定完記得先按 Apply ，再選取 Parasitics tab。

Capacitance Model TLU+
按 Apply，再選取 Model tab。
Delay Model Elmore
16. Load Synopsys Design Constraints
在 Message/Input Area 輸入 ataRemoveTC

“ Timing > Load SDC ”
SDC File Name ../design_data/pmult32_pr.sdc
SDC File Bus Naming Style [%d]
SDC File Hierarchy Separator /
按 OK。
確認是否全部的 constraints 都有下到。

“ Timing > Timing Data Check ” Default 值，按 OK。

Cell Name pmult32_timing
overwrite Enable
按 OK。
18. Pre-Placement
“ InPlace > Placement Common Options ”
Optimization Mode Congestion, Timing
No Cells under Preroute of M1, M2, M3, M4, M5
按 OK。
19. “ PrePlace > Pre-Placement Optimization ” Default 值，按 OK。
20. “ PreRoute > Connect Ports to P/G ”

Net Name VDD
Port Pattern VDD
Net Type Power
Mode Connect
按 Apply。

Net Name GND
Port Pattern GND
Net Type Ground
Mode Connect
按 OK。
“ PreRoute > Standard Cells” Default 值，按 OK。
21. InPlace
“ InPlace > Design Placement ”
Speed medium
Mode congestion + timing
In-Placement Optimization Enable
Routability v.s. Timing bar 5
按 OK。
22. 觀察 Congestion 及 Critical Path

“ InPlace > Display Timing Map ” 按 Clear，再按 Cancel。
“ InPlace > Display Congestion Map ” 按 Apply，如果沒問題按 Clear，再按 Cancel。
23. “ PostPlace > Post-Place Optimization Phase 1 ”

Optimization Effort LOW
Re-do HFN Synthesis Enable
Using Global Routing Enable
Setup Fixing Enable
Hold Fixing Disable
Design Rule Fixing Enable
Fix Max Length Disable
Fix Tran/Cap Enable
Prevent Xtalk Disable
按 OK。

Cell Name mul_placed
overwrite Enable
按 OK。
25. “ Clock > Clock Common Options ” Default 值，按 OK。
26. “ Clock > Clock Tree Synthesis ” Default 值，按 OK。
27. 在 Message/Input Area 輸入 “ atCmdFreeTimer ” 來更新 timing view。
28. “ Clock > Skew Analysis ” Default 值，按 OK。

Global Skew Longest Delay Shortest Delay
CLOCK

Ignore Clock Uncertainty Enable
Ignore Propagated Clock Disable
Enable Ideal Network Delay Disable
30. “ PostPlace > Post Placement Optimization ” Default 值
“ Timing > Timing Report ” Default 值

Cell Name mul_cts
overwrite Enable
按 OK。
32. 在 Placement Optimization 時有些 gate 或 buffer 可能被加入或拿掉，所以必須重新再作一次

Power/Ground Connection。
“ PreRoute > Standard Cells ” Default 值，按 OK。

33. “ Route Setup > Route Common Options ”
Global Routing Timing Driven
Clock Routing balanced
Track Assign Timing Driven
Detail Routing connect tie off,
connect open nets
Same Net Notch check and fix
按 OK。
34. “ Route > Route Net Group ”

Net Name(s) From: All clock nets
Phase global, track assign, detail
Dangling wires Discard
Optimize routing pattern Enable
“ Route > Global Route ” Default 值，按 OK。
35. 觀察 congestion 情況
“ Route > Estimate Global Route Congestion! ”
“ Route > Display Congestion Map ” 按 Apply，如果沒問題按 Clear，再按 Cancel。
congestion 結果 ok，則不需作 Global Route Optimization。
36. “ Route > Auto Route ” Default 值，按 OK。

選取 Model tab
Delay Model AWE
按 Apply。

38. 若有 DRC violations，則需使用 Search & Repair 去修正。
“ Route > Search and Repair ”
按 OK。
39. 作最後的 Optimize

“ Route > Post Route Optimization ” Default 值，按 OK。

Cell Name mul_routing
overwrite Enable
按 OK。
41. 加入 Antenna Rules (已修改完畢)
antenna_rules.cmd
define _libId (dbGetCurrentLibId)
dbDefineAntennaRule _libId 2 2 0 0
在 Message/Input Area 輸入 load “../tech/antenna_rules.cmd ” 加入 antenna rules。
“ Route Setup > HPO Signal Route Options ” 設定 antenna ratio 的計算模式
Timing-Driven Spacing Off
Change-Collecting Antenna advanced
按 OK。
在 Message/Input Area 輸入 axReportAntennaRatio (geGetEditCell)
如果有出現 violation (紅色框框的地方)，必須用 Search & Repair 修正。

“ Route > Search and Repair ” Default 值，按 OK。
輸入 axReportAntennaRatio (geGetEditCell) 確認 violation 是否還存在。

42. 加入 Core Filler
“ PostPlace > Add Core Fillers ”
Master Cell Name(s) Without Metal FILL64, FILL32, FILL16, FILL8,
FILL4, FILL2, FILL1
Master Cell Name(s) With Metal
respect hard placement blockage Enable
respect soft placement blockage Enable
between std cells only Enable
Connect to Power Net (optional) VDD
Connect to Ground Net (optional) GND
按 OK。
43. “ PreRoute > Standard Cells ” Default 值，按 OK。
44. 將單一個 via 置換成 2 個 via，作 contacts optimization

在 Message/Input Area 輸入 load “../scripts/optContacts.cmd”
45. “ Route > Search and Repair ” Default 值，按 OK。
46. 由於 Power Net 的寬度過大，違反 metal density rules。

“ PreRoute > Slot Wires ”
Select Wires Specified
CutWidth 20
CutLength 30
Width 2
Length 10
Side Space 10
EndSpace 10
Side Clearance 10
End Clearance 10
Stagger Enable
Treat Width as Minimum
Treat Length as Minimum
Treat Spaces and Clearances as Maximum
按 OK。
47. “ Route Utility > Fill Notch/Gap ” Default 值，按 OK。

48. “ Verify > DRC ” Default 值，按 OK。
“ Verify > LVS ” Default 值，按 OK。
49. 作 Calibre LVS 跟 Post Layout Simulation 時要在 layout 上加上 Text 才會正確。
在 Message/Input Area 輸入 load “../scripts/add_text.cmd”
add_text.cmd (已編輯完畢)
dbAllowToAddPGIOText #t
dbAddIOText (geGetEditCell) "*" "*" 103 20

Cell Name mul_dfm
overwrite Enable
按 OK。
51. Stream Out GDS II

“ Tools > Data Prep ”
“ Output > Stream Out ”
注意 Output Net 中一定要選取 As Text，否則 LVS 會有問題。
Stream File Name pmult32.gds
Library Name mul
Layer File ../tech/stout.map
Child Extraction Depth 20
Convert Specified Cell
Cell Name pmult32
Convert Reference Lib Child Cells Enable
Flatten Devices & Device Arrays
Fill FILL
Pin/Net Options > Output Pins As Text
Pin/Net Options > Output Net As Text
按 OK。
52. Verilog Out

PS：若無法 dump verilog netlist，必須重新修復 net 和 instance 的連線(CHIP.CEL 要先關閉後才
能執行此動作)。
“ Cell > Repair Hierarchy Information ”
Flattened Cell Name(.CEL) pmult32.CEL
Repair net connections and instances Enable
按 OK。

“ Cell > Hierarchical Verilog Out ” ----for caliber block box LVS
Enter File Name pmult32_lvs.vg
No Corner Pad Instances Disable
No Pad Filler Cell Instances Disable
No Core Filler Cell Instances Disable
No Unconnected Cell Instances Disable
No Unconnected Ports Disable
No Diode Ports Disable
Output 1’b1 for Power(VDD, vdd, …) and 1’b0 for Ground(VSS, gnd, …) Disable
按 OK。
53. Change directory to Lab2/verify/drc

unix% cd ~/astro/Lab2/verify/drc
54. 複製 DRC 相關檔案至 drc 的資料夾

Calibre-drc-cur Design Kit
180nm_layers.cal Design Kit
metal_slot_0.18_1P6M-MMC-Calibre-drc-2.2-p1 Design Kit
pmult32.gds Astro
unix% cp ~/astro/Lab2/run/pmult32.gds .
55. 修改 Calibre-drc-cur 檔
LAYOUT PATH "./pmult32.gds"
LAYOUT PRIMARY "pmult32"
56. 執行 Calibre DRC

unix% calibre –drc –hier Calibre-drc-cur
觀察 drc.sum 檔看看是否有 drc error
57. Change directory to Lab2/verify/lvs

unix% cd ~/astro/Lab2/verify/lvs

58. 複製 LVS 相關檔案到 lvs 資料夾
pmult32.gds Astro
pmult32_lvs.vg Astro
umc18_lvs.spi Design Kit
umc18_lvs.v Design Kit
Calibre-lvs-cur Design Kit
unix% cp ~/astro/Lab2/run/pmult32.gds .
unix% cp ~/astro/Lab2/run/pmult32_lvs.vg .
59. 將 pmult32_lvs.vg 轉換成 spice 格式

unix% v2lvs –v pmult32_lvs.vg –l umc18_lvs.v –o pmult32.spi –s umc18_lvs.spi
60. 修改 Calibre-lvs-cur
SOURCE PRIMARY "pmult32"
SOURCE PATH "./pmult32.spi"
LAYOUT PRIMARY "pmult32"

LAYOUT PATH "./pmult32.gds"
61. 執行 Calibre LVS

unix% caliber –lvs –spice pmult32.spi –hier –auto Calibre-lvs-cur
觀察 lvs.rep 找到 OVERALL COMPARISON RESULT 部份是否 match

Astro 2004 7

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Cell-Based IC Physical

Design and Verification with

NETL EXP CEL FRAM TIM lib

Net Expanded Cell Frame views Timing views

Reference CHIP IO99

NETL EXP CEL FRAM LM lib

NETL EXP CEL FRAM TIM lib

NETL EXP CEL FRAM TIM lib

Net Expanded Cell

z A necessary first step if you want to “mark as preserved” or do

z Depending on the verification technology, it may be

dbCreateCellInst (geGetEditCell) "" “PVSSC.FRAM" “vss_core_1" "0" "NO" '(0.0 0.0)

Cell ID Reference Reference Instance Rotation Mirror Origin (X,Y)

Return current cell

pad padName padSide Cul T1 T2 Cur

Aspect ratio: 40/50 = 0.8

Fillers command VSS

dbCreateCellInstPlacement _cell “D0" "270" "no" "origin" '(0 400.00)

z Unspecified pads are placed automatically

1. Connect power to standard cells

ring macro macro macro ring

macro macro macro

Connections are made to

Gate-level Netlist Back-annotated Parasitic

Block Models Estimated Wire Load Models

delay time (ns)

Cell Delay = T0 + Ac * Cload

output capacitance load (pf)

T0 : cell pin to pin intrinsic delay

Cell Delay Dcell(I2) = f(Dtransition(I1), Ceq)

Transition Delay Dtransistion(I2) = g(Dtransition(I1), Ceq)

Output Input Transition

0.2 0.222 0.432 0.801

Vin Dc Vout Dtransition(I2)

z Output transition direction depends on unateness

delay delay delay

Worst Typical Worst

Process Voltage Temperature

Gate-level Netlist Back-annotated Parasitic

Block Models Estimated Wire Load Models

z All register-to-register path are constrained now

Output Capacitance Load

Input delay = Delayclk-Q + a

Input Block My Design Output Block

Gate-level Netlist Back-annotated Parasitic

Block Models Estimated Wire Load Models

z RSPF – Reduced Standard Parasitic Format

Cwire = (fanout=3, length =2.8) x capacitance coefficient (1.3) =

Gate-level Netlist Back-annotated Parasitic

launch edge source clock (ideal)

R 2 Why are the

launch edge source clock (ideal)

F 2 Why are the

launch edge source clock (ideal)

18 target clock (source+network

source clock (ideal)

AT = 20 Why are the

source clock (ideal)

AT = 19 Why are the

launch edge source clock (source+

18 target clock (source+network

source clock (ideal)