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a.
The pole zero pattern of a certain filter is shown in Fig. below. The filter must be
(A) low pass.
(B) high pass.
(C) all pass.
(D) band pass.
b. For the logic circuit shown in Fig. below, the output y is equal to
(A) .
(B) .
(C) .
(D) .
c. 2’s complement representation of 16 bit number (one sign bit and 15 magnitude
bits) is FFFF. Its magnitude in decimal representation is
(A) 0. (B) 1.
d. A pulse train with a frequency of 1 MHz is counted using a module 1024 ripple
counter built with JK flipflops. For proper operation of the counter, the maximum propagation
delay per flipflop stage is
(B) 4V.
(C) 5V.
(D) 3V.
PART I
Answer any THREE Questions. Each question carries 14 marks.
Q.2 a. Find the output voltage of the following circuit assuming ideal op-amp behaviour.
(5)
Q.4 a. Show that the system shown in Fig. below is a double integrator. Assume ideal op-
amp. (7)
b. Design an active second order band pass filter with a centre frequency of 2 KHz, a
bandwidth of 150 Hz and a midband gain of 20. Derive the equations
used. (7)
Q.5 a. Explain with necessary timing diagram, the function of a dual slope A to D
converter deriving the necessary expressions for the same. (8)
b. For a 12 bit ADC, the normal full scale output is 12 volts. Determine
(i) resolution.
(iv)
Q.6 a. Find the value of in the circuit shown below for generating sinusoidal
oscillations and determine an expression for frequency of oscillation. (7)
c.
In the CMOS inverter circuit shown the input Vi makes a transition from VOL (OV) to VOH (5V).
Determine the high to low propagation delay time (tPHL) when it is driving a capacitive load of
20 pF. Device data :
NMOS: ,
PMOS : , , .
Neglect body effect. (7)
PART II
Answer any THREE Questions. Each question carries 14 marks.
Q.7 a. In a certain application, four inputs A, B, C, D (all are available in complemented and
uncomplemented forms) are fed to a logic circuit, producing an output F, which
operates a relay. The relay turns on when F (ABCD) = 1 for the following states of the
inputs (ABCD); 0000, 0010, 0101, 0110, 1101 and 1110. States 1000 and 1001 do not
occur and for the remaining states, the relay is off. Minimise F and realize it using
minimum number of 3-input NAND gates. (7)
b. The circuit diagram of a synchronous counter is shown below. Determine the sequence
of states of the counter assuming that the initial state is „000‟. Give your answer in a
tabular form showing the present state, next state and the JK inputs. From the table
determine the modulus of the counter. (7)
Q.9 a. For the CMOS monostable multivibrator shown in Fig. below, R=50 K , C=0.01 ,
and the CMOS NOR gates have a threshold of 1.5 volts, is a
trigger pulse ( ) as shown.
Q.10 a. Design a 4 bit adder cum subtractor using shift registers. (8)
b. Discuss how interfacing is achieved between
(i) TTL and CMOS gates. (ii) TTL and ECL gates.
(6)
(i) PLA.
(ii) CCD.
Q1. a. C The pole locations are mirror image symmetric to location of the
, or
, or .
f. C
PART I
Q2. a. By virtual ground the voltage at the –ve terminals of the two OpAmps are and
1V respectively. Assume that Va is the voltage at output of the first OpAmp Then,
KCL at the –ve terminal of first OpAmp gives
, or .
, or .
Q4.a. By virtual ground the –ve terminal of the OpAmp is at virtual ground. Therefore,
Similarly, the current going towards –ve terminal of the OpAmp from the second
and
, (4b.2)
Q6.a. The gain of the RC network of the given oscillator circuit can be obtained as
.
b. Refer to Section 8.8 [3] for derivation of the propagation delay time given by
PS NS
Q0 Q1 Q2 Q0 Q1 Q2 J0 K0 J1 K1 J2 K2
0 0 0 1 0 0 1 1 0 1 0 0
1 0 0 0 1 0 1 1 1 1 0 0
0 1 0 0 0 1 0 1 0 1 1 1
0 0 1 1 0 1 1 1 0 1 0 0
1 0 1 0 1 1 1 1 1 1 0 0
0 1 1 0 0 0 0 1 1 1 1 1
which can be realized with two 4-1 multiplexers as shown below. The inputs to
the multiplexers are the residues of the two functions. For example, when B=A=0,
Since the functions are of four variables, the ROM is required to have 2 4=16
Locations. Thus, the size of the ROM is 16x3. The data in the ROM is as per the
delays are zero, the waveforms at various points in the given monostable circuit are as given
below with V1 as the waveform at the output of first NOR gate.
A sudden change in Vo is transferred to the resistance R. The capacitor C discharges till VR
equals the threshold voltage of the driver transistor of the NOR gate (assume it to be 0.5VDD).
At this time, V1 suddenly switches to VDD and Vo to zero. This change is also transferred to R
and the capacitor then charges asymptotically to zero. Thus, during the time when Vo = VDD
(logic 1),
where RC=(50x103)x(0.01x10-6)=5x10-6s. The time period T of the output pulse will end when
VR = 0.5VDD. For this condition, T can be evaluated as 7.2x10 -6s.
b. The truth-table and the excitation table of the flipflop are as given below
Exc. X Y
X
Y
0 0 0→0 1 x
0 1 1 0→1 0 x
1 0 0 1→0 x 0
1 1 1→1 x 1
are X,Y and Q, and whose outputs are J and K inputs of the JK flipflop as shown
The truth table for this logic can be written as
0 0 0 1 1 1 1 0 0 0 0 1
0 0 1 0 1 1 1 0 1 0 0 1
0 1 0 1 1 0 1 1 0 0 0 0
0 1 1 1 1 0 1 1 1 1 0 0
Q10.a. For 4-bit 2‟s complement adder/subtracter, refer to Sections 7.2, 7.3 [2].
b. For a TTL to CMOS interface, refer to Section 8.12 [3] and for a TTL to ECL
(vi) For Switched mode power supply, refer to Section 17.7 [2].
References
DEC 2003
a.
(A) .
(B) .
(C) .
(D) .
(A) . (B) .
(C) . (D) .
(A) . (B) .
(C) . (D) .
e. A square wave with a period of 10 drives a T-flip-flop. The period of the output
signal will be
(A) . (B) .
(C) . (D) .
(A) . (B) .
(C) . (D) .
h. Boolean expression is equal to
(A) . (B) .
(C) . (D) .
PART I
Q.2 a. Write biquadratic transfer function for lowpass, highpass, bandbass and band reject
filters. (6)
b. Using verify that the circuit given in Fig.1 below is a band pass
filter. (8)
Q.3 a. Derive the input impedance of a close loop non-inverting op-Amp. amplifier and show
that it is greater than the open loop input impedance. (8)
b. What is an analog multiplier? Compare in brief, the performances of 1-quadrant, 2-
quadrant and 4-quadrant
multipliers. (6)
Q.4 a. Under what condition the circuit of Fig.2 can function as a log-amplifier? Use ideal op-
amps. (8)
b. Draw an op-amp based sample and hold circuit and explain the operation. (6)
Q.5 a. Discuss the switching time of a transistor with the help of a pulse waveform at the
input of a transistor. (4)
b. Draw the circuit of a 4-quadrant Gilbert multiplier and derive its output. State the
approximation made, if any. (10)
PART II
Q.7 a. Derive the necessary parameters to sketch and explain the transfer characteristic of the
TTL circuit of Fig.3 below: -
(8)
b. What are the problems associated with the interfacing of TTL with CMOS and Vice
Versa? How can these problems be removed? (6)
Q.8 a. Implement a simplest PLA circuit for the Boolean function given below.
(8)
b. Compare PROM, PAL and PLA with an example for each. (6)
Q.9 a. Discuss the rule of formation of CMOS network for arbitrary combinational function.
Using this rule form the CMOS network for the function f.
(8)
b. Design and explain a basic circuit to display a 3-digit number using only one 7-segment
decoder. (6)
Q.10 a. Design a digital circuit to compare two numbers A and B having 2-bit each for three
outputs A > B, A = B and A < B. Use only AND, OR NOT and NOR
gates. (8)
b. Implement a full adder circuit with MUX modules. (6)
6 6
c. B 7x10 bytes = 7x8x10 bits.
voltage of 2.16 volts. It is the highest level smaller than 2.17 volts.
, which is proportional to s if .
PART I
b. With finite gain A, the negative input terminal of the Opamp will be at .
, or
function as
Q3.a. The figure below shows the circuit of noninverting amplifier. The Opamp has an
input impedance of Rin and the current flowing through it develops a small
voltage V with the polarity shown in the figure. The KCL equation at negative
Q4.a. For details of the given logarithmic amplifier, refer to Section 16.13 [2].
The conditions are required for the circuit to be a logarithmic amplifier are:
Q6. (i) For Slew rate of Opamps, refer to Section 2.6 [1].
PART II
Q7.a. For Transfer Characteristics of TTL, refer to Sections 6.5, 6.6, 6.7 [3].
Q8.a. A simple PLA implementation of the given functions is shown in figure below.
b. For PROM, refer to Section 11.6 [1]. For PAL and PLA, refer to Sections 7.14 and 7.15
[2].
Q9.a. For rule of CMOS gate formation, refer to Section 10.3 [1].
Using this rule, the following circuit for the given function results.
b. A circuit for a 3-digit display using using only one decoder is shown below. The
data to be displayed by the three displays comes in to the display decoder serially.
The displays are also turned ON serially (one at a time) by mutually exclusive
waveforms applied to the displays as shown in the figure. Thus, a single BCD to
b. The Boolean functions describing a full adder having A, B and C as inputs, are given as
References
a.
(A) LPF.
(B) HPF.
(C) BPF.
(D) BSF.
b.
The frequency limit for the circuit shown in Fig.2 to operate as an integrator will be
(B) 16 Hz.
c. The three basic second order filtering functions LP, BP and HP are performed simultaneously
by a universal active filter that can be implemented using
(A) two integrator loop Biquad. (B) Second order LCR resonator.
(A) 14 .
(B) 28 .
(C) 12 .
(D) 24 .
e. The circuit at Fig.4 gives an output Y given by
(A) .
(B) .
(C) .
(D) .
f. A 4 bit ripple counter has a count of 1001 at some instant. The count after 23
pulses will be
h. A ripple counter uses flip flops having tpd = 12 nsec. The largest mod counter that
can be constructed from flip flops operated at 10 MHz is
PART I
Answer any THREE Questions. Each question carries 14 marks.
Q.2 a. What is the difference between open loop and closed loop gain of an Op-Amp? The dc
open loop gain of an op-amp is . What will be the open loop gain at its break
frequency? (4)
b. Does increasing the compensating capacitor increase or decrease the unity factor
bandwidth? How fast can the output of an op-amp change by 10 V, if its slew rate is
1 V/ . Also find the maximum frequency for a sine-wave output voltage of 10
V peak with an op-amp whose slew rate is 1 V/ . (5)
c. For a non-inverting amplifier R = , . The op-amp has the
following specifications.
Assume that the amplifier is nulled at . Calculate the value of the error voltage
Q.3 a. Explain with a circuit diagram, a two - stage CMOS op-amp configuration. What is
systematic offset? How can it be minimized? (7)
Q.4 Determine the ripple factor and order N of the network function that uses Chebyshev
approximation to satisfy the following
requirements
Q.5 a. What is a flash converter? Explain. Consider the design of a 4 bit flash ADC.
How many comparators are required? For an input signal in the range of 0 to +10V, what are
the reference voltages needed? Show how they can be generated using a 10V reference and
several 1 K resistors. If a comparison is possible in 50 nsec and the associated logic
requires 35 nsec, what is the maximum possible conversion rate? Indicate the digital
code you expect at the output of the comparators and at the output of the logic for an input of
PART II
Answer any THREE Questions. Each question carries 14 marks.
Q.7 a. Design a BCD to excess-3 code converter using a diode ROM circuit. (6)
b. Design a combinational circuit that converts a 4 bit reflected code number to a 4 bit
binary number. Implement the circuit with exclusive OR gates. (8)
Q.8 a. Signals A, B, C, D and are available. Using only one 8 : 1 MUX and no other
gates, implement the function,
(7)
Q.9 a. For the circuit shown in Fig.5 below, sketch against time. Assume that all flip flops
are reset to zero before the clock is applied. (8)
b. (i) How many flip flops are required to build a binary counter circuit to count from 0 to
1023?
(ii) What is the frequency of the output of last flip flop for an input clock frequency of
5 MHz?
(iii) What is the counter‟s MOD number?
(iv) If the counter is initially at zero, what will it hold after 2060 pulses?
(v) Does the maximum frequency of a counter depend on the modulus for
Synchronous counter?
Ripple counter?
Explain. (6)
the OpAmp) for both (both capacitors are open circuit) and
f. B After 16 pulses the counter will come back to the state it started
h. B The time taken for the input pulse to ripple through all the N flip-
-9
the counter is 1/(12x10 N).
N
or N=8. Therefore modulo count is 2 =256.
PART I
Gain at corner frequency is equal to Open loop gain (in dB) – 3dB. If the open
5 5
loop gain is 10 , then gain at corner frequency = 20log1010 – 3 = 97 dB.
If the slew rate is , the smallest duration in which the output can change by
10V is .
offset current will be 3nA. Thus, the Op-Amp inverter with input voltage, offset
voltage and offset current is as shown in the figure below. The output voltage is
With reference to the figure shown, the ripple factor can be evaluated from
The order must be an integer. Thus NCH = 4. Similarly, the order NBW of the
Butterworth filter having same specifications can be obtained from the following
equation as
or NBW = 6, which is 2 higher than the order used for Chebyshev filter.
Q5.a. The flash analog to digital converter is the fastest conversion method. A 4-bit
4
flash converter uses 2 -1=15 comparators. The analog input Va is applied to the
4
divider network consisting of 2 =16 1K resistances as shown in the figure below.
This arrangement sorts the analog input in a range between two adjacent reference
voltages. The outputs of the comparators are fed to a priority encoder to obtain the
If time taken for comparison is 50ns and that for priority encoder is 35ns, then total time for
The output Y3Y2Y1Y0 for inputs 0V, 5.1V and 10V will be, respectively, 0000, 1010 and 1111.
Q6. For TTL, refer to Sections 6.5, 6.6, 6.7, 6.10 [3].
Q7.a. The truth table for BCD to Excess-3 code is shown in the truth table given below.
given as ROM address. The data stored in the ROM for remaining inputs is don’t
care.
b. For truth table of Gray to binary converter, refer to Section 7.9 [2]. The corresponding
Boolean functions can be obtained from this table as
Q8a.The residues of the given Boolean function for various combinations of B, C and D are
shown in the following truth table, which can be implemented by an 8:1 MUX as shown
in the figure
B C D f
0 0 0 0
0 0 1
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1
1 1 0 1
1 1 1 1
b. The state diagram for the problem and the state table along with D inputs of the two
flipflops are as shown below.
PS NS D1 D0
Q1Q0 X=0 X=1 0 1 0 1
0 0 0 1 1 0 0 1 1 0
0 1 0 0 1 0 0 0 1 0
1 0 0 0 1 0 0 0 1 0
Q9.a. The given circuit is a modulo-6 twisted ring (Johnson) counter, whose outputs Q 0, Q1, Q2 are
fed to an inverting summer amplifier. Count sequence of the counter is
000,100,110,111,011,001. Therefore, the output of the Opamp will be a repeating sequence
0V, -1V, -2V, -3V, -2V, -1V changing at every falling edge of the clock. as shown in the
figure.
b. (i) 10
(iii) 1024
(iv) 2060=1024+1024+12. Hence, counter will hold 12.
(v) Yes, in case of a ripple counter. In a synchronous counter, the clock is applied
simultaneously to all flipflops and thus, the maximum frequency of operation does
not depend on the modulus of the counter.
Q10.a. A 2½ D organized 16X1 memory is using two 2-4 decoders is shown in the figure below.
c.
Q11. (i) For sequence generators, refer to Section 10.17 [3].
References
b.
(A)
(B) .
(C) .
(D) .
(A) 1.0 V.
(B) -0.5 V.
(C) 0.5 V.
(D) 0.0 V.
(A) . (B) .
(C) . (D) .
e. The T-input of a negative edge triggered has been tied to logic „1‟. If its clock input is as
shown in the fig.3, then ON and OFF time of its out will be, respectively
PART I
Answer any THREE Questions. Each question carries 14 marks.
Q.2 The OpAmp shown in the circuit of fig.5 has an open loop gain of 10000, input
impedance of 1MΩ and an output impedance of 1KΩ.
(i) Determine if –2.1V is applied between terminals A and B.
(5)
(iii) Find the gain of the amplifier when the input has a source resistance of 1KΩ. (4)
Q.3 Consider the function .
Q.4 Explain the working of a 12-bit dual-slope analog to digital converter using appropriate
diagrams and derive the relevant expression for the digital output. If the input
voltage is in range (0V, 10V) and the counter in the converter is given a clock of 1
MHz, determine
(i) the time taken for output of the integrator to reach its maximum
value. (8)
(ii) conversion time for input voltage = 5V, assuming reference
voltage of –10V. (6)
Q.5 a. Through proper sketches explain the electron density distribution in the base of a
n-p-n Bipolar Junction Transistor when
(ii) in Saturation.
PART II
Answer any THREE Questions. Each question carries 14 marks.
Q.7 a. A portion of TTL gate circuit is shown in the Fig.7(a), where the transistor Q has
Base-to-emitter voltage of the transistor is equal to 0.7V when it is in
active region and 0.75V when Q is in saturation. Determine the output voltage V if
the current I=2.5mA. (6)
b. Both NMOS and PMOS transistors in the circuit of Fig.7(b) have a threshold voltage of
2V and equal characteristic constants. Determine the value of input voltage and
the range of output voltage for which both transistors will be in
saturation. (8)
Q.8 a. Determine the Boolean function implemented by the multiplexer circuit shown in the
fig.8 (a). (4)
b. A 3-to-8 decoder has two enable inputs E1 and as shown in fig.8 (b). Write a truth
c. With the help of a diagram using Full-adders, explain the working of a 4-bit parallel
addition/subtraction of 2‟s complement numbers. (5)
Q.9 a. Explain the working of a positive-edge-triggered Master-Slave JK flipflop. What are
its advantages over a normal JK flipflop? If all NAND gates used in the flipflop have
a propagation delay of 5 ns, compute the delay of the Master-
Slave. (6)
b. Design a circuit to generate the sequence 100010 using JK flipflops and logic gates as
required. (8)
b. Draw the circuit of a CMOS static RAM cell and explain its operation. (4)
c. Three negative edge triggered flipflops having inputs , and
respectively, are connected to make a counter such that
Q1. a. B Refer to Section 16.9 [2]. The correct answer is B with 2N-1
instaed of N-1
f. D When inputs are 00, both outputs are 1. Switching the input to 11
current source.
PART I
Q2.a. With Opamp replaced by its equivalent circuit, the given amplifier can be drawn as shown in
the figure where Vi = -2.1V. The node equations at negative and positive terminals of the
Opamp may be respectively written as
where V=V+-V- and A=105. Solving these equations with gives
V=0.231mV.
b. Same figure can be used to obtain the gain. Neglecting current through 1M input impedance of
the Opamp, the node equations can be written as
Which give . Further, the following equations may be written for currents
through the three 1K resistances.
c. Same figure can be used to obtain the gain. Writing KVL for the loop containing the source,
we get
where is the source voltage and =1K is the source resistance. Using the result of Q2c
gives
.
Q3. (i) The poles and zeros of H(s) are respectively given by
and
Thus, the poles are at mirror image locations of the zeros as shown in the
figure.
(ii) The magnitude of this allpass filter is K. For plots of magnitude and phase, refer to
p.1105 [1].
Or,
Q4. For a description of Dual slope converter and derivation of expressions, refer to
(i) Time required for the out put to reach its maximum value is same as the
time required by the counter to reach its maximum count of 2 12. For a clock of
Q5.a. For electron density distribution and explanation, refer to Section 1.20 [3].
(ii) For Sample and Hold circuits, refer to Section 16.2 [2].
PART II
PMOS will be in saturation if Vo - Vi < VT , or Vo < 8 volts. Also, NMOS will be in saturation
if Vi - Vo < VT , or Vo > 4 volts. The range when both transistors are in saturation is 4< Vo <8.
Q8.a. It is easily seen that for AB equal to 00, 01, 10, 11, the output of multiplexer will
A B C D E O0 O1 O2 O3 O 4 O5 O6 O7
x x x 0 x 0 0 0 0 0 0 0 0
x x x 0 x 0 0 0 0 0 0 0 0
0 0 0 0 1 1 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0 0 0 0 0 0
0 1 0 0 1 0 0 1 0 0 0 0 0
0 1 1 0 1 0 0 0 1 0 0 0 0
1 0 0 0 1 0 0 0 0 1 0 0 0
1 0 1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 1 0 0 0 0 0 0 1 0
1 1 1 0 1 0 0 0 0 0 0 0 1
Q9.a. For an explanation of Master-Slave JK flipflop and its advantages, refer to Section 8.4 [2]. A
NAND flipflop will take 2 gate delays to stabilize the output after the inuts are applied. Thus,
both Master and Slave sections of the flipflop require 3 gate delays. Add 1 gate delay for the
gate used for complementing the clock. Thus the delay required after the positive edge of the
clock is 4 gate delays or 20ns.
b. A sequence generator is a shift register whose first flipflop gets its D-input from the present
state of the shift register through a combinational logic as shown in the figure below. The
output of a flipflop in this circuit is a delayed version of its predecessor flipflop. This makes
the truth table of the logic block as shown below. From the truth table the Boolean function
Q0 Q1 Q2 f
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0
PS NS
Q0 Q1 Q2 J 0 K0 J 1 K1 J 2 K 2 Q0 Q1 Q2
0 0 0 1 1 1 1 0 1 1 1 0
1 1 0 1 1 1 1 1 1 0 0 1
0 0 1 0 1 1 1 0 1 0 1 0
0 1 0 1 1 1 1 0 1 1 0 0
1 0 0 1 1 1 1 1 1 0 1 1
0 1 1 0 1 1 1 0 1 0 0 0
JUNE 2003
a.
The pole zero pattern of a certain filter is shown in Fig. below. The filter must be
(A) low pass.
(B) high pass.
(C) all pass.
(D) band pass.
b. For the logic circuit shown in Fig. below, the output y is equal to
(A) .
(B) .
(C) .
(D) .
c. 2’s complement representation of 16 bit number (one sign bit and 15 magnitude
bits) is FFFF. Its magnitude in decimal representation is
(A) 0. (B) 1.
(C) 32,767. (D) 65,535.
d. A pulse train with a frequency of 1 MHz is counted using a module 1024 ripple
counter built with JK flipflops. For proper operation of the counter, the maximum propagation
delay per flipflop stage is
(A) 6V.
(B) 4V.
(C) 5V.
(D) 3V.
PART I
Answer any THREE Questions. Each question carries 14 marks.
Q.2 a. Find the output voltage of the following circuit assuming ideal op-amp behaviour.
(5)
Q.4 a. Show that the system shown in Fig. below is a double integrator. Assume ideal op-
amp. (7)
b. Design an active second order band pass filter with a centre frequency of 2 KHz, a
bandwidth of 150 Hz and a midband gain of 20. Derive the equations
used. (7)
Q.5 a. Explain with necessary timing diagram, the function of a dual slope A to D
converter deriving the necessary expressions for the same. (8)
b. For a 12 bit ADC, the normal full scale output is 12 volts. Determine
(i) resolution.
(iv)
Q.6 a. Find the value of in the circuit shown below for generating sinusoidal
oscillations and determine an expression for frequency of oscillation. (7)
c.
In the CMOS inverter circuit shown the input Vi makes a transition from VOL (OV) to VOH (5V).
Determine the high to low propagation delay time (tPHL) when it is driving a capacitive load of
20 pF. Device data :
NMOS: ,
PMOS : , , .
Neglect body effect. (7)
PART II
Answer any THREE Questions. Each question carries 14 marks.
Q.7 a. In a certain application, four inputs A, B, C, D (all are available in complemented and
uncomplemented forms) are fed to a logic circuit, producing an output F, which
operates a relay. The relay turns on when F (ABCD) = 1 for the following states of the
inputs (ABCD); 0000, 0010, 0101, 0110, 1101 and 1110. States 1000 and 1001 do not
occur and for the remaining states, the relay is off. Minimise F and realize it using
minimum number of 3-input NAND gates. (7)
b. The circuit diagram of a synchronous counter is shown below. Determine the sequence
of states of the counter assuming that the initial state is „000‟. Give your answer in a
tabular form showing the present state, next state and the JK inputs. From the table
determine the modulus of the counter. (7)
Q.8 a. Design a full adder using Multiplexers. (7)
b. A ROM is to be used to implement the Boolean functions given below :
Q.9 a. For the CMOS monostable multivibrator shown in Fig. below, R=50 K , C=0.01 ,
and the CMOS NOR gates have a threshold of 1.5 volts, is a
trigger pulse ( ) as shown.
(i) Plot as function of time.
(ii) Write the equation for for t > 0.
(iii) Find the time period of the output pulse.
(7)
b. A new clocked X-Y flipflop is defined with two inputs, X and Y in addition to the
clock input. The flipflop functions as follows :
If XY = 00, the flipflop changes state with each clock pulse.
If XY = 01, the flipflop state Q becomes 1 with the next clock pulse.
If XY = 10, the flipflop state Q becomes 0 with the next clock pulse.
If XY = 11, no change of state occurs with the clock pulse.
(i) Write the truth table for the X-Y flipflop.
(ii) Write the excitation table for the X-Y flipflop.
(iii) It is desired to convert a JK flipflop to the X-Y flipflop (as mentioned
above) by adding some external gates, if necessary. Draw a circuit to show
how will you implement the X-Y flipflop using JK
flipflop. (7)
Q.10 a. Design a 4 bit adder cum subtractor using shift registers. (8)
b. Discuss how interfacing is achieved between
(i) TTL and CMOS gates. (ii) TTL and ECL gates.
(6)
(i) PLA.
(ii) CCD.
Q1. a. C The pole locations are mirror image symmetric to location of the
, or
, or .
f. C
PART I
Q2. a. By virtual ground the voltage at the –ve terminals of the two OpAmps are and
1V respectively. Assume that Va is the voltage at output of the first OpAmp Then,
KCL at the –ve terminal of first OpAmp gives
, or .
, or .
Q4.a. By virtual ground the –ve terminal of the OpAmp is at virtual ground. Therefore,
Similarly, the current going towards –ve terminal of the OpAmp from the second
and
, (4b.2)
Q6.a. The gain of the RC network of the given oscillator circuit can be obtained as
.
b. Refer to Section 8.8 [3] for derivation of the propagation delay time given by
PS NS
Q0 Q1 Q2 Q0 Q1 Q2 J0 K0 J1 K1 J2 K2
0 0 0 1 0 0 1 1 0 1 0 0
1 0 0 0 1 0 1 1 1 1 0 0
0 1 0 0 0 1 0 1 0 1 1 1
0 0 1 1 0 1 1 1 0 1 0 0
1 0 1 0 1 1 1 1 1 1 0 0
0 1 1 0 0 0 0 1 1 1 1 1
which can be realized with two 4-1 multiplexers as shown below. The inputs to
the multiplexers are the residues of the two functions. For example, when B=A=0,
Since the functions are of four variables, the ROM is required to have 2 4=16
Locations. Thus, the size of the ROM is 16x3. The data in the ROM is as per the
delays are zero, the waveforms at various points in the given monostable circuit are as given
below with V1 as the waveform at the output of first NOR gate.
A sudden change in Vo is transferred to the resistance R. The capacitor C discharges till VR
equals the threshold voltage of the driver transistor of the NOR gate (assume it to be 0.5VDD).
At this time, V1 suddenly switches to VDD and Vo to zero. This change is also transferred to R
and the capacitor then charges asymptotically to zero. Thus, during the time when Vo = VDD
(logic 1),
where RC=(50x103)x(0.01x10-6)=5x10-6s. The time period T of the output pulse will end when
VR = 0.5VDD. For this condition, T can be evaluated as 7.2x10 -6s.
b. The truth-table and the excitation table of the flipflop are as given below
Exc. X Y
X
Y
0 0 0→0 1 x
0 1 1 0→1 0 x
1 0 0 1→0 x 0
1 1 1→1 x 1
are X,Y and Q, and whose outputs are J and K inputs of the JK flipflop as shown
The truth table for this logic can be written as
0 0 0 1 1 1 1 0 0 0 0 1
0 0 1 0 1 1 1 0 1 0 0 1
0 1 0 1 1 0 1 1 0 0 0 0
0 1 1 1 1 0 1 1 1 1 0 0
Q10.a. For 4-bit 2‟s complement adder/subtracter, refer to Sections 7.2, 7.3 [2].
b. For a TTL to CMOS interface, refer to Section 8.12 [3] and for a TTL to ECL
(vi) For Switched mode power supply, refer to Section 17.7 [2].
References
DEC 2003
a.
(A) .
(B) .
(C) .
(D) .
(A) . (B) .
(C) . (D) .
(A) . (B) .
(C) . (D) .
e. A square wave with a period of 10 drives a T-flip-flop. The period of the output
signal will be
(A) . (B) .
(C) . (D) .
(A) . (B) .
(C) . (D) .
h. Boolean expression is equal to
(A) . (B) .
(C) . (D) .
PART I
Q.2 a. Write biquadratic transfer function for lowpass, highpass, bandbass and band reject
filters. (6)
b. Using verify that the circuit given in Fig.1 below is a band pass
filter. (8)
Q.3 a. Derive the input impedance of a close loop non-inverting op-Amp. amplifier and show
that it is greater than the open loop input impedance. (8)
b. What is an analog multiplier? Compare in brief, the performances of 1-quadrant, 2-
quadrant and 4-quadrant
multipliers. (6)
Q.4 a. Under what condition the circuit of Fig.2 can function as a log-amplifier? Use ideal op-
amps. (8)
b. Draw an op-amp based sample and hold circuit and explain the operation. (6)
Q.5 a. Discuss the switching time of a transistor with the help of a pulse waveform at the
input of a transistor. (4)
b. Draw the circuit of a 4-quadrant Gilbert multiplier and derive its output. State the
approximation made, if any. (10)
PART II
Q.7 a. Derive the necessary parameters to sketch and explain the transfer characteristic of the
TTL circuit of Fig.3 below: -
(8)
b. What are the problems associated with the interfacing of TTL with CMOS and Vice
Versa? How can these problems be removed? (6)
Q.8 a. Implement a simplest PLA circuit for the Boolean function given below.
(8)
b. Compare PROM, PAL and PLA with an example for each. (6)
Q.9 a. Discuss the rule of formation of CMOS network for arbitrary combinational function.
Using this rule form the CMOS network for the function f.
(8)
b. Design and explain a basic circuit to display a 3-digit number using only one 7-segment
decoder. (6)
Q.10 a. Design a digital circuit to compare two numbers A and B having 2-bit each for three
outputs A > B, A = B and A < B. Use only AND, OR NOT and NOR
gates. (8)
b. Implement a full adder circuit with MUX modules. (6)
6 6
c. B 7x10 bytes = 7x8x10 bits.
voltage of 2.16 volts. It is the highest level smaller than 2.17 volts.
, which is proportional to s if .
PART I
b. With finite gain A, the negative input terminal of the Opamp will be at .
, or
function as
Q3.a. The figure below shows the circuit of noninverting amplifier. The Opamp has an
input impedance of Rin and the current flowing through it develops a small
voltage V with the polarity shown in the figure. The KCL equation at negative
Q4.a. For details of the given logarithmic amplifier, refer to Section 16.13 [2].
The conditions are required for the circuit to be a logarithmic amplifier are:
Q6. (i) For Slew rate of Opamps, refer to Section 2.6 [1].
PART II
Q7.a. For Transfer Characteristics of TTL, refer to Sections 6.5, 6.6, 6.7 [3].
Q8.a. A simple PLA implementation of the given functions is shown in figure below.
b. For PROM, refer to Section 11.6 [1]. For PAL and PLA, refer to Sections 7.14 and 7.15
[2].
Q9.a. For rule of CMOS gate formation, refer to Section 10.3 [1].
Using this rule, the following circuit for the given function results.
b. A circuit for a 3-digit display using using only one decoder is shown below. The
data to be displayed by the three displays comes in to the display decoder serially.
The displays are also turned ON serially (one at a time) by mutually exclusive
waveforms applied to the displays as shown in the figure. Thus, a single BCD to
b. The Boolean functions describing a full adder having A, B and C as inputs, are given as
References
a.
(A) LPF.
(B) HPF.
(C) BPF.
(D) BSF.
b.
The frequency limit for the circuit shown in Fig.2 to operate as an integrator will be
(B) 16 Hz.
c. The three basic second order filtering functions LP, BP and HP are performed simultaneously
by a universal active filter that can be implemented using
(A) two integrator loop Biquad. (B) Second order LCR resonator.
(A) 14 .
(B) 28 .
(C) 12 .
(D) 24 .
e. The circuit at Fig.4 gives an output Y given by
(A) .
(B) .
(C) .
(D) .
f. A 4 bit ripple counter has a count of 1001 at some instant. The count after 23
pulses will be
h. A ripple counter uses flip flops having tpd = 12 nsec. The largest mod counter that
can be constructed from flip flops operated at 10 MHz is
PART I
Answer any THREE Questions. Each question carries 14 marks.
Q.2 a. What is the difference between open loop and closed loop gain of an Op-Amp? The dc
open loop gain of an op-amp is . What will be the open loop gain at its break
frequency? (4)
b. Does increasing the compensating capacitor increase or decrease the unity factor
bandwidth? How fast can the output of an op-amp change by 10 V, if its slew rate is
1 V/ . Also find the maximum frequency for a sine-wave output voltage of 10
V peak with an op-amp whose slew rate is 1 V/ . (5)
c. For a non-inverting amplifier R = , . The op-amp has the
following specifications.
Assume that the amplifier is nulled at . Calculate the value of the error voltage
Q.3 a. Explain with a circuit diagram, a two - stage CMOS op-amp configuration. What is
systematic offset? How can it be minimized? (7)
Q.4 Determine the ripple factor and order N of the network function that uses Chebyshev
approximation to satisfy the following
requirements
Q.5 a. What is a flash converter? Explain. Consider the design of a 4 bit flash ADC.
How many comparators are required? For an input signal in the range of 0 to +10V, what are
the reference voltages needed? Show how they can be generated using a 10V reference and
several 1 K resistors. If a comparison is possible in 50 nsec and the associated logic
requires 35 nsec, what is the maximum possible conversion rate? Indicate the digital
code you expect at the output of the comparators and at the output of the logic for an input of
PART II
Answer any THREE Questions. Each question carries 14 marks.
Q.7 a. Design a BCD to excess-3 code converter using a diode ROM circuit. (6)
b. Design a combinational circuit that converts a 4 bit reflected code number to a 4 bit
binary number. Implement the circuit with exclusive OR gates. (8)
Q.8 a. Signals A, B, C, D and are available. Using only one 8 : 1 MUX and no other
gates, implement the function,
(7)
Q.9 a. For the circuit shown in Fig.5 below, sketch against time. Assume that all flip flops
are reset to zero before the clock is applied. (8)
b. (i) How many flip flops are required to build a binary counter circuit to count from 0 to
1023?
(ii) What is the frequency of the output of last flip flop for an input clock frequency of
5 MHz?
(iii) What is the counter‟s MOD number?
(iv) If the counter is initially at zero, what will it hold after 2060 pulses?
(v) Does the maximum frequency of a counter depend on the modulus for
Synchronous counter?
Ripple counter?
Explain. (6)
the OpAmp) for both (both capacitors are open circuit) and
f. B After 16 pulses the counter will come back to the state it started
h. B The time taken for the input pulse to ripple through all the N flip-
-9
the counter is 1/(12x10 N).
N
or N=8. Therefore modulo count is 2 =256.
PART I
Gain at corner frequency is equal to Open loop gain (in dB) – 3dB. If the open
5 5
loop gain is 10 , then gain at corner frequency = 20log1010 – 3 = 97 dB.
If the slew rate is , the smallest duration in which the output can change by
10V is .
offset current will be 3nA. Thus, the Op-Amp inverter with input voltage, offset
voltage and offset current is as shown in the figure below. The output voltage is
With reference to the figure shown, the ripple factor can be evaluated from
The order must be an integer. Thus NCH = 4. Similarly, the order NBW of the
Butterworth filter having same specifications can be obtained from the following
equation as
or NBW = 6, which is 2 higher than the order used for Chebyshev filter.
Q5.a. The flash analog to digital converter is the fastest conversion method. A 4-bit
4
flash converter uses 2 -1=15 comparators. The analog input Va is applied to the
4
divider network consisting of 2 =16 1K resistances as shown in the figure below.
This arrangement sorts the analog input in a range between two adjacent reference
voltages. The outputs of the comparators are fed to a priority encoder to obtain the
If time taken for comparison is 50ns and that for priority encoder is 35ns, then total time for
The output Y3Y2Y1Y0 for inputs 0V, 5.1V and 10V will be, respectively, 0000, 1010 and 1111.
Q6. For TTL, refer to Sections 6.5, 6.6, 6.7, 6.10 [3].
Q7.a. The truth table for BCD to Excess-3 code is shown in the truth table given below.
given as ROM address. The data stored in the ROM for remaining inputs is don’t
care.
b. For truth table of Gray to binary converter, refer to Section 7.9 [2]. The corresponding
Boolean functions can be obtained from this table as
Q8a.The residues of the given Boolean function for various combinations of B, C and D are
shown in the following truth table, which can be implemented by an 8:1 MUX as shown
in the figure
B C D f
0 0 0 0
0 0 1
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1
1 1 0 1
1 1 1 1
b. The state diagram for the problem and the state table along with D inputs of the two
flipflops are as shown below.
PS NS D1 D0
Q1Q0 X=0 X=1 0 1 0 1
0 0 0 1 1 0 0 1 1 0
0 1 0 0 1 0 0 0 1 0
1 0 0 0 1 0 0 0 1 0
Q9.a. The given circuit is a modulo-6 twisted ring (Johnson) counter, whose outputs Q 0, Q1, Q2 are
fed to an inverting summer amplifier. Count sequence of the counter is
000,100,110,111,011,001. Therefore, the output of the Opamp will be a repeating sequence
0V, -1V, -2V, -3V, -2V, -1V changing at every falling edge of the clock. as shown in the
figure.
b. (i) 10
(iii) 1024
(iv) 2060=1024+1024+12. Hence, counter will hold 12.
(v) Yes, in case of a ripple counter. In a synchronous counter, the clock is applied
simultaneously to all flipflops and thus, the maximum frequency of operation does
not depend on the modulus of the counter.
Q10.a. A 2½ D organized 16X1 memory is using two 2-4 decoders is shown in the figure below.
c.
Q11. (i) For sequence generators, refer to Section 10.17 [3].
References
b.
(A)
(B) .
(C) .
(D) .
(A) 1.0 V.
(B) -0.5 V.
(C) 0.5 V.
(D) 0.0 V.
(A) . (B) .
(C) . (D) .
e. The T-input of a negative edge triggered has been tied to logic „1‟. If its clock input is as
shown in the fig.3, then ON and OFF time of its out will be, respectively
PART I
Answer any THREE Questions. Each question carries 14 marks.
Q.2 The OpAmp shown in the circuit of fig.5 has an open loop gain of 10000, input
impedance of 1MΩ and an output impedance of 1KΩ.
(i) Determine if –2.1V is applied between terminals A and B.
(5)
(iii) Find the gain of the amplifier when the input has a source resistance of 1KΩ. (4)
Q.3 Consider the function .
Q.4 Explain the working of a 12-bit dual-slope analog to digital converter using appropriate
diagrams and derive the relevant expression for the digital output. If the input
voltage is in range (0V, 10V) and the counter in the converter is given a clock of 1
MHz, determine
(i) the time taken for output of the integrator to reach its maximum
value. (8)
(ii) conversion time for input voltage = 5V, assuming reference
voltage of –10V. (6)
Q.5 a. Through proper sketches explain the electron density distribution in the base of a
n-p-n Bipolar Junction Transistor when
(ii) in Saturation.
PART II
Answer any THREE Questions. Each question carries 14 marks.
Q.7 a. A portion of TTL gate circuit is shown in the Fig.7(a), where the transistor Q has
Base-to-emitter voltage of the transistor is equal to 0.7V when it is in
active region and 0.75V when Q is in saturation. Determine the output voltage V if
the current I=2.5mA. (6)
b. Both NMOS and PMOS transistors in the circuit of Fig.7(b) have a threshold voltage of
2V and equal characteristic constants. Determine the value of input voltage and
the range of output voltage for which both transistors will be in
saturation. (8)
Q.8 a. Determine the Boolean function implemented by the multiplexer circuit shown in the
fig.8 (a). (4)
b. A 3-to-8 decoder has two enable inputs E1 and as shown in fig.8 (b). Write a truth
c. With the help of a diagram using Full-adders, explain the working of a 4-bit parallel
addition/subtraction of 2‟s complement numbers. (5)
Q.9 a. Explain the working of a positive-edge-triggered Master-Slave JK flipflop. What are
its advantages over a normal JK flipflop? If all NAND gates used in the flipflop have
a propagation delay of 5 ns, compute the delay of the Master-
Slave. (6)
b. Design a circuit to generate the sequence 100010 using JK flipflops and logic gates as
required. (8)
b. Draw the circuit of a CMOS static RAM cell and explain its operation. (4)
c. Three negative edge triggered flipflops having inputs , and
respectively, are connected to make a counter such that
Q1. a. B Refer to Section 16.9 [2]. The correct answer is B with 2N-1
instaed of N-1
f. D When inputs are 00, both outputs are 1. Switching the input to 11
current source.
PART I
Q2.a. With Opamp replaced by its equivalent circuit, the given amplifier can be drawn as shown in
the figure where Vi = -2.1V. The node equations at negative and positive terminals of the
Opamp may be respectively written as
where V=V+-V- and A=105. Solving these equations with gives
V=0.231mV.
b. Same figure can be used to obtain the gain. Neglecting current through 1M input impedance of
the Opamp, the node equations can be written as
Which give . Further, the following equations may be written for currents
through the three 1K resistances.
c. Same figure can be used to obtain the gain. Writing KVL for the loop containing the source,
we get
where is the source voltage and =1K is the source resistance. Using the result of Q2c
gives
.
Q3. (i) The poles and zeros of H(s) are respectively given by
and
Thus, the poles are at mirror image locations of the zeros as shown in the
figure.
(ii) The magnitude of this allpass filter is K. For plots of magnitude and phase, refer to
p.1105 [1].
Or,
Q4. For a description of Dual slope converter and derivation of expressions, refer to
(i) Time required for the out put to reach its maximum value is same as the
time required by the counter to reach its maximum count of 2 12. For a clock of
Q5.a. For electron density distribution and explanation, refer to Section 1.20 [3].
(ii) For Sample and Hold circuits, refer to Section 16.2 [2].
PART II
PMOS will be in saturation if Vo - Vi < VT , or Vo < 8 volts. Also, NMOS will be in saturation
if Vi - Vo < VT , or Vo > 4 volts. The range when both transistors are in saturation is 4< Vo <8.
Q8.a. It is easily seen that for AB equal to 00, 01, 10, 11, the output of multiplexer will
A B C D E O0 O1 O2 O3 O 4 O5 O6 O7
x x x 0 x 0 0 0 0 0 0 0 0
x x x 0 x 0 0 0 0 0 0 0 0
0 0 0 0 1 1 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0 0 0 0 0 0
0 1 0 0 1 0 0 1 0 0 0 0 0
0 1 1 0 1 0 0 0 1 0 0 0 0
1 0 0 0 1 0 0 0 0 1 0 0 0
1 0 1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 1 0 0 0 0 0 0 1 0
1 1 1 0 1 0 0 0 0 0 0 0 1
Q9.a. For an explanation of Master-Slave JK flipflop and its advantages, refer to Section 8.4 [2]. A
NAND flipflop will take 2 gate delays to stabilize the output after the inuts are applied. Thus,
both Master and Slave sections of the flipflop require 3 gate delays. Add 1 gate delay for the
gate used for complementing the clock. Thus the delay required after the positive edge of the
clock is 4 gate delays or 20ns.
b. A sequence generator is a shift register whose first flipflop gets its D-input from the present
state of the shift register through a combinational logic as shown in the figure below. The
output of a flipflop in this circuit is a delayed version of its predecessor flipflop. This makes
the truth table of the logic block as shown below. From the truth table the Boolean function
Q0 Q1 Q2 f
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0
PS NS
Q0 Q1 Q2 J 0 K0 J 1 K1 J 2 K 2 Q0 Q1 Q2
0 0 0 1 1 1 1 0 1 1 1 0
1 1 0 1 1 1 1 1 1 0 0 1
0 0 1 0 1 1 1 0 1 0 1 0
0 1 0 1 1 1 1 0 1 1 0 0
1 0 0 1 1 1 1 1 1 0 1 1
0 1 1 0 1 1 1 0 1 0 0 0