MC74HCT273A

Octal D Flip-Flop with

Common Clock and Reset
with LSTTL-Compatible
Inputs
High–Performance Silicon–Gate CMOS http://onsemi.com

The MC74HCT273A may be used as a level converter for MARKING

interfacing TTL or NMOS outputs to High–Speed CMOS inputs. DIAGRAMS
20
The HCT273A is identical in pinout to the LS273.
PDIP–20
This device consists of eight D flip–flops with common Clock and MC74HCT273AN
N SUFFIX
Reset inputs. Each flip–flop is loaded with a low–to–high transition of AWLYYWW
20 CASE 738
the Clock input. Reset is asynchronous and active low. 1
1
• Output Drive Capability: 10 LSTTL Loads 20
• TTL/NMOS Compatible Input Levels 20
SOIC WIDE–20
DW SUFFIX HCT273A
• Outputs Directly Interface to CMOS, NMOS and TTL 1 CASE 751D AWLYYWW

• Operating Voltage Range: 4.5 to 5.5 V 1

• Low Input Current: 1.0 µA A = Assembly Location
• In Compliance with the Requirements Defined by JEDEC Standard WL = Wafer Lot
YY = Year
No. 7A WW = Work Week
• Chip Complexity: 284 FETs or 71 Equivalent Gates
LOGIC DIAGRAM PIN ASSIGNMENT

3 2 RESET 1 20 VCC
D0 Q0
4 5 Q0 2 19 Q7
D1 Q1
7 6 D0 3 18 D7
D2 Q2
8 9 D1 4 17 D6
DATA D3 Q3 NONINVERTING
INPUTS 13 12 Q1 5 16 Q6
D4 Q4 OUTPUTS
14 Q2 6 15 Q5
D5 15
Q5 D2 7 14 D5
17
D6 16
18 Q6 D3 8 13 D4
D7 19
11 Q7 Q3 9 12 Q4
CLOCK
GND 10 11 CLOCK

PIN 20 = VCC
1 PIN 10 = GND
RESET
FUNCTION TABLE ORDERING INFORMATION
Inputs Output Device Package Shipping
Reset Clock D Q MC74HCT273AN PDIP–20 1440 / Box
L X X L MC74HCT273ADW SOIC–WIDE 38 / Rail
H H H
H L L MC74HCT273ADWR2 SOIC–WIDE 1000 / Reel
H L X No Change
H X No Change

X = Don’t Care
Z = High Impedance

 Semiconductor Components Industries, LLC, 2000 1 Publication Order Number:

March, 2000 – Rev. 8 MC74HCT273A/D
 MC74HCT273A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
be taken to avoid applications of any
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V
voltage higher than maximum rated

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
cuit. For proper operation, Vin and
Iout DC Output Current, per Pin ± 25 mA
Vout should be constrained to the
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ICC DC Supply Current, VCC and GND Pins ± 50 mA range GND (Vin or Vout) VCC.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be
PD Power Dissipation in Still Air Plastic DIP† 750 mW tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
SOIC Package† 500 level (e.g., either GND or VCC).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150 _C Unused outputs must be left open.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
TL Lead Temperature, 1 mm from Case for 10 Seconds _C
(SOIC or Plastic DIP) 260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Symbol
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎ
ÎÎÎ Parameter Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VCC

ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vin, Vout
ÎÎ
ÎÎÎÎÎÎ
DC Supply Voltage (Referenced to GND)

ÎÎ
ÎÎÎ
DC Input Voltage, Output Voltage (Referenced to GND)
4.5
0
5.5
VCC
V
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TA
ÎÎÎ
ÎÎ
ÎÎÎ
Operating Temperature, All Package Types – 55 + 125 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tr, tf
ÎÎÎ
ÎÎ
ÎÎÎ
Input Rise and Fall Time (Figure 1) 0 500 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
v ÎÎÎ VCC – 55 to
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VIH Minimum High–Level Input Vout = 0.1 V or VCC – 0.1 V 4.5 2.0 2.0 2.0 V
v Voltage |Iout| 20 µA 5.5 2.0 2.0 2.0

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VIL
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Voltage ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Low–Level Input

ÎÎÎ
Vout = 0.1 V or VCC – 0.1 V
|Iout| 20 µA
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
VOH

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Voltage
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Minimum High–Level Output

ÎÎÎ
Vin = VIH or VIL
|Iout| 20 µA
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VIH or VIL
v |Iout| 4.0 mA 4.5 3.98 3.84 3.7

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VOL
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
Voltage ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Low–Level Output

ÎÎÎ
Vin = VIH or VIL
|Iout| 20 µA
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Vin = VIH or VIL
|Iout| 4.0 mA 4.5 0.26 0.33 0.4

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Iin Maximum Input Leakage Vin = VCC or GND 5.5 ± 0.1 ± 1.0 ± 1.0 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Current
µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ICC Maximum Quiescent Supply Vin = VCC or GND 5.5 4.0 40 160
Current (per Package) Iout = 0 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
∆ICC

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Current ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Additional Quiescent Supply

ÎÎÎ
Vin = 2.4 V, Any One Input
Vin = VCC or GND,
GND Other In
Inputs
uts
≥ –55_C 25_C to 125_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
lout = 0 µA 5.5 2.9 2.4 mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).

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 MC74HCT273A

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
– 55 to
v v
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter Fig. 25_C 85_C 125_C Unit

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
fmax Maximum Clock Frequency (50% Duty Cycle) 1, 4 30 24 20 MHz

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPLH, Maximum Propagation Delay, Clock to Q 1, 4 25 28 35 ns
tPHL

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Propagation Delay, Reset to Q 2, 4 25 28 35 ns

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH,

ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTHL ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Output Transition Time, Any Output

ÎÎÎ
1, 5 18 20

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
22 ns

Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Gate)* 30 pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎÎÎ
TIMING REQUIREMENTS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ v
ÎÎÎ ÎÎÎ
ÎÎÎÎÎ v
ÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ – 55 to 25_C
Guaranteed Limit
85_C 125_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol

ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tsu ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
ÎÎÎÎ
ÎÎ ÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
Parameter

ÎÎÎ
Minimum Setup Time, Data to Clock
Fig.
3
Min
10
Max Min
12
Max Min
15
Max Unit
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
th
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
ÎÎÎÎÎÎ
ÎÎ
Î ÎÎÎ
Minimum Hold Time, Clock to Data

ÎÎ
ÎÎÎ
3 3.0 3.0 3.0 ns
trec

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tw
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎ
Minimum Recovery Time, Set or Reset Inactive to Clock

ÎÎ
Î ÎÎ
ÎÎÎÎÎÎ
Minimum Pulse Width, Clock
2
1
5.0
12
5.0
15
5.0
18
ns
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tw
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
ÎÎÎÎÎÎ
Minimum Pulse Width, Set or Reset 2 12 15 18 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tr, tf
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
ÎÎÎÎÎÎ
Maximum Input Rise and Fall Times 1 500 500 500 ns

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 MC74HCT273A

SWITCHING WAVEFORMS

tr tf tw
3.0 V 3.0 V
2.7 V RESET 1.3 V
CLOCK 1.3 V
0.3 V GND GND
tw tPHL

1/fmax 1.3 V
Q
tPLH tPHL
90% trec
Q 1.3 V 3.0 V
10% CLOCK 1.3 V
tTLH tTHL GND

Figure 1. Figure 2.

TEST POINT

VALID OUTPUT
3.0 V DEVICE
DATA 1.3 V UNDER
GND TEST CL*
tsu th
3.0 V
1.3 V
CLOCK GND
*Includes all probe and jig capacitance
Figure 3. Figure 4. Test Circuit

EXPANDED LOGIC DIAGRAM

C 2
3 Q Q0
D0 DR

C 5
4 Q Q1
D1 DR

C 6
7 Q Q2
D2 DR

C 9
8 Q Q3
D3 DR NONINVERTING
DATA
OUTPUTS
INPUTS C 12
13 Q Q4
D4 DR

C 15
14 Q Q5
D5 DR

C 16
17 Q Q6
D6 DR

C 19
18 Q Q7
D7 DR

11
CLOCK

1
RESET

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 MC74HCT273A

PACKAGE DIMENSIONS

PDIP–20
N SUFFIX
PLASTIC DIP PACKAGE
–A–
CASE 738–03
NOTES:
ISSUE E 1. DIMENSIONING AND TOLERANCING PER ANSI
20 11 Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
B 3. DIMENSION L TO CENTER OF LEAD WHEN
1 10 FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
C L
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
A 1.010 1.070 25.66 27.17
B 0.240 0.260 6.10 6.60
–T– C 0.150 0.180 3.81 4.57
K D 0.015 0.022 0.39 0.55
SEATING
PLANE M E 0.050 BSC 1.27 BSC
F 0.050 0.070 1.27 1.77
E N G 0.100 BSC 2.54 BSC
J 0.008 0.015 0.21 0.38
G F K 0.110 0.140 2.80 3.55
J 20 PL
L 0.300 BSC 7.62 BSC
D 20 PL 0.25 (0.010) M T B M M 0_ 15 _ 0_ 15_
0.25 (0.010) M T A M N 0.020 0.040 0.51 1.01

SO–20
DW SUFFIX
CASE 751D–05
ISSUE F

D
A q
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
20 11 2. INTERPRET DIMENSIONS AND TOLERANCES
M

PER ASME Y14.5M, 1994.

B

X 45 _

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD

H
M

PROTRUSION.
E
10X

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

0.25

5. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
1 10 MAXIMUM MATERIAL CONDITION.

MILLIMETERS
DIM MIN MAX
20X B B A 2.35 2.65
A1 0.10 0.25
0.25 M T A S B S B 0.35 0.49
C 0.23 0.32
D 12.65 12.95
E 7.40 7.60
e 1.27 BSC
A H 10.05 10.55
h 0.25 0.75
L

SEATING L 0.50 0.90

PLANE q 0_ 7_
18X e A1 T C

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 MC74HCT273A

Notes

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 MC74HCT273A

Notes

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 MC74HCT273A

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