Académique Documents
Professionnel Documents
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E. Arnold
&
P. Schepers
Philips Semiconductors
TV System Design, ICE, Eindhoven
?
File: Herc_1.ppt = Introduction, v1.2 29-09-2003 by E.Arnold
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Philips Semiconductors
3. Block diagrams
4. Intake open questions
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7. Answering questions
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Nijmegen
!! Emulator
Application
$$$
IC design
Spec & Debugger
ApNote
IPM
Nijmegen
+ Shanghai
Development
Herc
!?
?
?!
Philips Semiconductors
System
GTV
Architecture I2C
TVSD & Definition
ICE Reference Training TV System PC menu GTV platform
HW architecture I2C driver SW libraries
Eindhoven
TVSD (HW) + SDCE (SW)
Innovation Center
Eindhoven
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Technical support:
Philips Semiconductors
Software IPM/RSO GTV + Business Partners:
Eindhoven+Southampton
Objectives:
Philips Semiconductors
• Share layout & EMC experience
• STANDARD solutions (libraries, basic cell, IP-blocks)
Software has become a substantial part of the total design effort. Philips
Semiconductors understands that our technical information will be used by
experienced TV developers, but ALSO by “fresh” engineers. We are now
adding more (basic) functional descriptions to our (detailed) technical
application notes.
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Design-in approach:
Philips Semiconductors
(how we’ve done it) (how functions are intended)
• Description I2C-bus bits • TV functions & algorithms
• TV know-how required • Higher abstraction level
Please use the documentation of this course together with our technical
Application Notes and it should be easier to:
- understand how certain functions should be operated
- find the link between a function and its I2C-bus control bits
- prevent errors in TV chassis design
In the IC’s Application Note you can find descriptions of each pin and the I2C-
bus control bits. In this training course we will show how TV functions use the
I2C-bus bits.
The diagrams in this presentation are intended to explain the functional
behavior. The actual IC implementation may be different.
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ü Faster time-to-market
ü Faster factory throughput
The platform:
• Make TV design as
easy as possible Available as I/O pins:
- 4x ADC/IO
Philips Semiconductors
- 2x Int/IO
• Optimal process - 6x PWM/IO
- 2x IO
combination - 2x IO (no UART used)
- 5x Output (no I2S used)
(MCM of CMOS + BIMOS) - 1x Swo (no YUVoutput used)
- 1x SwIo/Vguard (p12)
= 23 lines, excluding I2C
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“Face-down” QFP-package:
97
• Two variants = easier choice for PCB layout 1 96
Old pinning
“Old” face (IC-top view)
• Existing QFP128 SMD 32 65
package SOT-320-2
33
64
⇓
• Same physical IC, ⇓
but legs bent the other
Philips Semiconductors
way
32
1
128 33
New, reversed
pinning
• Type number printed (IC-top view)
97 64
on the new “top” of the “New” face
96
65
“flipped” - IC
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The highlights:
Philips Semiconductors
• FM sound, no external filters (traps/band-pass 4.5/5.5/6.0/6.5)
• Full multi-standard colour decoder
• One Xtal reference for all functions (micro processor, RCP,
TXT, CC, RDS, colour decoder & stereo sound processor)
The highlights:
Philips Semiconductors
ADC / PWM / Push-Pull / Open-Drain …
All 3.3V supply pins should be permanently connected to the Standby supply.
Including peripheral components, the start-up current is less than ??100mA.
During standby mode the device’s power consumption can be reduced to
??12mA, by bringing the software in Power Saving mode (improved
POWERDOWN and IDLE modes).
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The highlights:
Philips Semiconductors
- Soft colours
- Soft scroll
- Reduced-intensity background
- Dynamic Redefinable Characters (DRCs)
Normal 8051 core can address up to 64KB of ROM. The address space is
enhanced with bank-switching.
DRCs make it possible to add dynamic animations to the OSD. They can also
be used to extend the number of OSD character fonts.
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Classification of TV receivers:
Mono
TDA8361 + TDA8362 + TDA8362 + TDA8362A + TDA8840 +
TDA4665 + TDA4665 + TDA4665 + TDA4665 + SAA5290 (uP + TXT)
PCA84C441 TDA8395 + TDA935x/6x/8x - FM Ultimate One Chip
TDA8395 + TDA8395 +
Y PR PB
Philips Semiconductors
PHILIPS PHILIPS
PHILIPS PHILIPS
TDA8842 + Stereo +
TDA8844 TDA8854 + TDA9801 + TDA8376A +
SAA5291 (1p TXT) SAA5296 (10p TXT) SAA5497 (10p TXT) TDA4665 + TDA8395 +
TDA935x/6x/8x - QSS Ultimate One Chip SAA5497 (10p TXT)
• TDA935x/6x/8x-FM for mono, -QSS for stereo
UOCIII “Hercules“
••UOC-III “Hercules“for forMono
Monoand andStereo
Stereo
• TDA95xx provides both QSS & FM/AM demod.
The largest production volume is found in the Low-end segment. The UOC-III
“Hercules” IC makes it possible to build a very compact TV chassis, including
extensive audio/video I/O switching.
Philips Semiconductors
Parabola Parabola
For more precise alignment, the corner parabola’s can be set independently for
the upper and lower corners.
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• 1V8, 3V3STANDBY and +VB needed to start line drive
• Secondary +5V and +8V can be generated by FBT
LSU, MSU = NOT yet available in ≤ ES7.2D samples
+5V and 1V8EXT must be ON during IC-reset ??
The IC can start generating HOUT line-drive pulses from only its 3.3V Standby
supply voltage. This is called “Low voltage start-up”.
The +VB for the FBT is normally well-stabilized (1%) by the SMPS
(determines picture width). Secondary supplies that are scan-rectified from the
FBT need NO stabilizers. Also the +5V second power supply for the IC can be
generated in this way.
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Pseudo auto Y/C detector
3-bit Signal-to-Noise ratio measurement
Integration of White Stretch capacitor
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Up to 16x18 font size
RDS (Radio Data System)
Character smoothing
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Dolby Pro Logic Delay & Pseudo Hall / Matrix function
I2S out for Sub-Woofer or full 5-channel DPL [Trademark of Dolby Laboratories]
Smooth volume control, soft mute, loudness, bass, treble,
Incredible mono / Incredible stereo
Programmable beeper
AV Stereo playback
Type
Number
TDA120xx
TDA110xx -
stereo
-
Sound
-
√
DSP
√
Number of TXT
pages
Multi BTSC Audio Mono 0 10
only Comb filter
Colour decoder
NTSC Multi
DW Panorama
FM radio
type selection:
Stereo Mono
RDS/RDBS
DBX
Dolby Pro Logic
Virtual Dolby
SRS 3D stereo
SRS TruSurround
BBE
ROM [kB]
128 4
256 8
inside:
switch
F
DAC
RGB Peaking
switch
YUV
Brightness Stereo
Saturation
RGB out YUV Sound
Contrast
DAC
TXT
Split - screen
Panorama
OSD
CC
Sync YUV RDS Micro
ADC
Comb Colour
Switch +
Filter Decoder Vref
IF Flash
Philips Semiconductors
“Cosmic” “Picasso”
UOCIII “Hercules”
Philips Semiconductors
- Micro TCG Teletext, Control and Graphics
FU Function class
- SU Start-Up, set before switching-on from stand-by
- AL Alignment, aligned during production, values set before switching on
- SC Setmaker Control, controlling normal operation
- UC User Control, accessible for the customer like contrast, brightness, etc.
- TK Tool Kit, can help to improve performance under difficult working conditions
like RF phase modulation, wrong burst/chroma ratio, etc.
GTV Function Function call within the GTV software Platform
Functional blocks:
Philips Semiconductors
Tuner Groupdelay -BP, Y-delay Scavem
Digital Audio BeamCurrent
Soundtrap PAL,NTSC,SECAM Digital processing RGB
Features Baseband-delay White Limit,
QSS Double window IBLACK
Softclipping
Stretching
Audio Switch, In/Out CVBS,Y/C, Brightness IBEAM
Goto
2x Volume YUV/RGB, matrix Contrast
Dictionary
QSS, I2S CVBS DVD (YPBPR) YUV
IFOUT or RGB+FBL loop
Y/C
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In/Out
IF:
• Integrated sound band-passes & traps (4.5 / 5.5 / 6.0 / 6.5 MHz)
Philips Semiconductors
• QSS versions with digital Second-Sound-IF SSIF (AM demodulator for free)
Four different IF-AGC time constants can be chosen via I2C-bus, for optimal
performance under various conditions. For positive modulation the AGC time
constant is automatically adapted to a larger value.
GTV Function: ptun_SetIFAGCSpeed
The UOC-III family makes no difference anymore between QSS- and Inter-
Carrier-IF, nearly all types are software-switchable between the two SAW-filter
constructions.
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IF modes:
AGC
AGC
TV VIF
DVB-Tuner
AGC TV SAW
Tuner
VIF
Tuner
(SIF)
TV SAW VIF
FM Tuner
add-on REFin
BP SSIF Optional BP SSIF
10.7 MHz (INTCO) (INTCO)
Philips Semiconductors
FMRO DVBO
TV-IF modes:
The cheapest IF mode is “Inter-Carrier”, using one SAW filter for both video
and sound. Better separation of video and sound is achieved, using “Quasi-
Split Sound”. The sound SAW is now optimised and passes > 10dB more
sound carrier. This results is better sound sensitivity and higher quality video.
FM-Radio modes:
Adding a special FM-radio tuner plus 10.7MHz band pass gives the best result
(FM tuner = optimised for phase-noise & selectivity). A QSS configuration
allows double-use of the TV tuner for low-cost FM-Eco-radio implementation.
The selectivity of the sound-SAW filter should be switched (FM radio =
narrower than TV-FM-sound). Various mixing frequencies can be used
(e.g. RIF=37.5MHz mixed with 43.008 gives 5.5MHz → FM-demodulator).
Extra selectivity can be added externally, but is usually not needed.
DVB mode:
The IF spectrum (36MHz) is mixed-down to a “low-IF” frequency (4.5MHz) ,
that can be handled by an add-on DVB demodulator. If the fixed down-mix
frequency does not match the DVB concept, the DVB part can deliver a
reference carrier to the UOC-III.
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Xtal detector
I/O switch
55 CVBS2
calibrated & AFC 58,59 Y/C3
Colour Comb 51,52 Y/C4
SAW 24
25 decoder filter 72,70 Y/C5
PC 64 CVBSO
VIF Video AM demodulator
28
PL Cross
bar
34,35
36,37
AV1
Philips Semiconductors
Mono Mono-FM
62,63 HP
60,61 LS
MonoOUT + 39 NB- Stereo
15K DAC1 ADC DAC2
DeEmphasis PLL I2SIN/OUT
Narrow-Band-PLL SSD
FM demodulator SSIF 102..106
33
SSIF IN
AGC
46
SSIF-AGC
The embedded Comb Filter function (some UOC-III type numbers) improves
the video decoding performance significantly.
A single, combined video + audio SAW filter is known as “Inter carrier”. With
the same UOC-III “Hercules” device, also a “QSS” construction can be made,
using separate VIF (Video-IF) and SIF (Sound IF) SAW filters. Selection
between QSS or IntC is done via software.
Although all required traps & band-pass filters are integrated, we maintain
flexibility to route the signals through external filters. This is useful for testing
and/or for unforeseen field conditions (see next slide).
External trap
Tuner
Group
Front-End out
Delay
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I/O switch
IF-PLL SID 55 CVBS2
Det. tuner AGC to ground Ident
IFS AFN 58,59 Y/C3
FMR Colour Comb 51,52 Y/C4
SAW 24
25 decoder 72,70 Y/C5
PC BPB YCD 64 CVBSO
VIF
28 MOD FMR
FM radio mode uses the INA..D,CS1A..D,SD2..0
SIF video mixer-path, to keep
29 49,50 AV4
SAW 30 SC2..0,
the Tuner-AGC operational
QSS HP2..0 Sound 56,57 AV3
SC QSS AM FMA..B,
Sound demod. BPB2 L,Ext MONO Cross 34,35 AV1
42 bar 36,37
SIF-AGC AGC AM Mute
53,54
MOD AV2
VOL
Philips Semiconductors
Mono AM/FM
38 FMI,FMWS 62,63 HP
Decoupling Narrow-Band-PLL mono-FM demodulator
QSS AM FMA..E
60,61 LS
MonoOUT + 39 NB- Stereo
15K Stereo DAC1
demodulator
ADC DAC2and 106 I2SIN
swapper
DeEmphasis Mute +6dB PLL DSPaudio processing 105 I2SOUT1
Digital Digital 104 I2SOUT2
E2D, SM0/1,AM AGN FML/W 103 I2SCLK
33 SSIF demod+ Sound
SSIF IN FMI L,Ext MONO 102 I2SWS
CMB2..0 AGC decoder Processor
46 5x I/O
SSIF-AGC
For European SCART TV sets the tuner-part must always remain active, but in
Asia-Pacific the tuner can be shut-off ( bit VSW=1) when an external source is
viewed. Please note that VSW also shorts the Tuner AGC output to ground.
The DC-range (max. and min.) must be limited by external resistors, otherwise
the Tuner AGC voltage may take very long to settle.
GTV Function: pimg_SetVideoMute
For flexibility you can take the Front-End signal outside the IC (IFVO, before or
after the internal sound trap). An additional, external sound trap can be added
in series with the signal path. Then it can be re-inserted via CVBSI or CVBS2.
Doing so via CVBS2 keeps the option to have Front-End output at pin SVO.
Further a 2-tuner system can be supported (e.g. one to “cable” plus another for
“antenna”). The base-band-output of a secondary (PIP) tuner+IF can be cross-
linked to the UOC-III : output via IFVO and input via CVBSI (or CVBS2). This
avoids an antenna switch.
Sound band-passes for FM mono demodulation are available at 4.5, 5.5, 6.0
and 6.5MHz. Other band-pass filters can be added outside the IC (4.72, 5.74).
Frequency of internal trap/band pass is determined by FMA..FMD.
GTV Function: psys_GetFMDemodulatorCentreFrequency,
psnd_SetFMDemodulatorSelection
FM radio IF (RIF) internally uses the part of the video mixer (FMR=1), so that
the Tuner-AGC output remains operational during (Eco-) FM radio mode.
GTV Function: ptun_SetTVFMMode
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fast & proportional tuning corrections (25kHz resolution)
• AFC only valid when IF-PLL in-lock,
practical range = -2MHz .. +500kHz (including SAW filter characteristic)
• Switch AFC detection off when not needed (improves sound cross talk)
The frequency of the IF-PLL is calibrated with a tolerance of 25kHz. This same
tolerance is applicable to the AFC-readout.
Because the AFC read-out is very precise, it is possible to correct tuning
deviations with ONE, proportional step. E.g when the transmitter is drifted
away by 375kHz, it will take SW only one action to correct the tuning. We
advice to keep such proportional jumps smaller than 800kHz; larger deviations
can better be corrected in more than one step.
When AFC indication is not needed, you can switch-off the detection
mechanism via AFN=1. For critical applications this can help to improve frame-
synchronous cross-talk to the sound. SW can e.g. randomize reading back the
AFC information.
GTV Function:
ptun_StartSearch / ptun_CancelSearch
ptun_IsSearchActive
ptun_TransmitterFound
ptun_GetIdents
ptun_SetAFCSwitch (Note: this sets AFN to 0)
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Phase modulation:
Fast PLL time constant
(follow carrier frequency variations)
Over modulation:
Philips Semiconductors
Slow PLL time constant
(don’t follow 180º jump)
For normal modulation, the standard loop filter is a good balance for most
situations, with sufficient reserve.
Phase modulation:
When a high level of phase modulation (~FM modulation) of the AM carrier
occurs, it helps to reduce the external filter time constant. This enables the IF-
PLL to follow the phase modulation faster.
Over-modulation:
When the modulation depth exceeds 100%, the phase of the AM carrier
suddenly changes 180 degrees. The IF-PLL tries to follow this phase jump but
this is NOT wanted. Performance can be improved by increasing the external
filter time constant. This prevents the IF-PLL from over-reacting on these
temporary phase inversions.
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Philips Semiconductors
FFI=1 : PLL time constant automatically adapted to carrier level
Better behaviour for phase modulation (FM) and over modulation
When both phase modulation and over-modulation occur, the requirements for
the IF PLL loop filter are contradictory.
Bit FFI adapts the time constant of the IF-PLL loop filter, depending on the IF-
amplitude of that moment:
- Normal time constant for high modulation (= low carrier amplitude)
- Fast time constant for low modulation (= high carrier amplitude)
This can improve the reception performance under difficult conditions (both
FM- and over-modulation of the picture carrier).
When FFI is set to 1, the PLL time constant for low carrier levels is kept
normal, while for higher carrier levels the PLL speed is increased. In this way,
a better compromise between phase modulation and over- modulation is
possible. GTV Function: ptun_SetFastFilterIFPLL
Remarks:
- FFI=1 has no influence on e.g. search-tuning speed
- Use FFI only for negative modulation (MOD=0)
- Use toolkit bit FFI=1 only if you really have to, we advice to implement it as
a service-mode option
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Philips Semiconductors
0 1 0 0 x 0 33.4 MHz Secam L1 with 5.5 MHz shift
0 1 1 0 x 0 33.9 MHz Secam L1 with 5 MHz shift
1 x x x x 0 External reference Flexible DVB down-mix
FM-Radio modes
0 x x x 1 x 10.7 MHz FM-Radio mode (independent of VIF)
0 1 0 1 0 1 43.008 MHz
Eco-FM-Radio mode
0 1 1 1 0 1 49.152 MHz
For 10.7MHz selectivity you can use a band-pass filter like e.g.:
Murata “SFE 10.7 MS3 A 20 G”.
- MS3=bandwidth 180kHz (needed with fully occupied FM-band), MS2=230kHz
- A=accuracy center frequency is exactly 10.7
- 20=tolerance of +/-20kHz, 10=10kHz, 30=30kHz
- G=flat group delay time, best for low distortion & large FM swing
GTV Function:
LOCK: ptun_GetIfPllLock
AFC,AFN: ptun_SetAFCSwitch (Note: sets AFN to 0)
FFI: ptun_SetFastFilterIFPLL
IFS: ptun_SetIFSensitivity
STM: ptun_SetFEIdentSensitivity
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Philips Semiconductors
BITS FUNCTION STEPS RANGE MACRO FU REM
TOP AGC Take-Over-Point 63 0.4..80 mV IF AL
OIF Offset IF-PLL 63 Small DC-offset IF AL 20 H = neutral
IFLF=1 prevent the IF oscillator from being re-calibrated. This is useful only in
European TV sets, where the Scart plug definition requires continuous tuner-
CVBS output. Normally IF calibration is vertically synchronised. But when
external video is selected, the vertical is no longer synchronous to the tuner-
CVBS. If e.g. by over modulation the IF-PLL accidentally gets out of lock
(LOCK=0), there is no need for a re-calibration, that might be visible in the
tuner CVBS output signal. Keep IFLF=0 during channel-change & at start-up;
the rest of the time it can be set to IFLF=1.
GTV Function → IFLF: sys_SetCalibrationIFPLLDemodulator
With OIF the IF-PLL can be given a small offset, for improved PLL behavior
under noisy signal conditions. This depends on tuner + SAW filter, so OIF can
best be a factory alignment (or set to 20HEX for no offset).
Philips Semiconductors
001 IFOUT Mute Without Sound Trap or Group Delay
010 IFOUT after SndTrap Mute Including GD for flat SAW filter
011 FMROUT / DVBOUT,P FMROUT / DVBOUT,N FM radio-IF Balanced DVB
100 FMROUT / DVBOUT,SE Mute output when bit ??ES7.2D:
FMR=1 Single ended DVB
110 Mute FMR / DVB
OUT OUT,SE IF-AGC set
at 6x (max)
111 Black DC Black DC Black-level-DC = mute without DC jump can be too
fast (see
below)
GTV Function:
AM: psnd_SetQssAm, psys_SetQssAmOutSelect
AMLOW: psnd_SetAMDemodulatorGain
MONO: psys_SetActivateFMmonoDemodulator
FMI: psnd_SetQSSAmplifierOutputSelection,
psys_SetConnectionOutputQSSAmplifier
SSIF: psys_SetCombFilterControl
QSS: psnd_SetQSSAmplifierMode,
psys_SetQSSAmpMode
VDXEN: psys_SetEnableVDX
VDX: psys_GetModeIFSyncInterface
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Philips Semiconductors
Proper AGC control requires feedback from a digital DVB demodulator. With
AGCM=1, the SIFAGC pin 42 becomes an input for an analogue AGC control
voltage (generated by DVB add-on).
GTV Function:
AGCM: ptun_SetAGCMode
EPVI: psys_SetIFPLLOscillatorPresetValue
IFE:
PVI1: psys_SetIFPresetValue1
PVI2: psys_SetIFPresetValue2
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Mono sound:
Philips Semiconductors
In/Out
This “Mono” sound section refers to the mono sound decoder in the analogue
part of UOCIII.
The sound demodulator in the digital part (mono & stereo) is described in
section “Stereo”.
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Philips Semiconductors
• Second-Sound-IF-input (SSIF) and
INTer-Carrier-Output (INTCO) for additional selectivity
(4.72 / 5.74MHz & FM-radio modes)
The IF frequency is stabilised using the X-tal reference oscillator. Sound band
pass filters are integrated, although for extremely critical signal circumstances
it is still possible to add one externally.
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Synchronous AM demodulation:
0o
Clipper
LPF
VOUT
Philips Semiconductors
The Multiplier in an AM sound demodulator folds the IF frequency spectrum
back to zero Hz. Together with a Low-Pass-Filter this has the same effect as a
bandpass filter in the IF stage.
The incoming AM signal is rectified. After integration (LPF) the result is the
amplitude variation (LF) of the IF spectrum.
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OSC
Loop Filter
VOUT = 0 at 90o
Philips Semiconductors
Narrow-Band PLL frequency range =
VOUT = -1/2 at 45o
fOSC +/- 150 kHzTYPICAL
No external
No filters needed
filters needed VOUT = +1/2 at 135o
(internally added for enhanced FM performance)
The narrow PLL loop filter is especially optimized for selectivity. Therefore the
external bandpass filter can be omitted. The PLL frequency is selected via I2C-
bus (gives improved sensitivity), making the NB-PLL solution multi-standard.
To optimize the sound performance with extreme, non-standard signals it is still
possible to add an external filter.
Audio THD should be measured with equipment that filters out only the applied
audio modulation plus its harmonics. Otherwise you include noise into the THD
measurement.
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Volume
MAX. sound volume (DSG=1)
+ 12 dB
1400
1000
De emphasis level
De emphasis level
C=33p for
0 dB 500 BTSC stereo
C=3n9
oct -6
dB/ dB/ T=54µs
+6 oct
Sound f1 f2
output 100
Philips Semiconductors
[mV] 10 100 1k 10k 100k
f [Hz]
FM-
Sound
Carrier
Narrow
Window
Bits FMWS1..0
Wider
Window
Philips Semiconductors
• Digital acquisition helper brings FM-PLL back in range, when it
loses lock to the FM carrier
(set auto-mute: SM1,0=0,1 to limit noise from acquisition helper)
modes
0 0 0 x 0 5.5 MHz Intern 5.5 MHz PAL-BGIDK, SECAM-BG
0 0 1 x 0 5.74 MHz Extern 5.5 MHz 2nd language A2
1 0 0 x 0 6.0 MHz Intern 6.0 MHz PAL-I
1 1 0 x 0 6.5 MHz Intern 6.5 MHz PAL-DK, SECAM-DK
x x x 1 x 10.7 MHz Extern x FM radio mode
Philips Semiconductors
1 0 1 x 1 7.902 MHz Extern Video blanked Eco FM radio USA
1 1 1 x 1 9.608 MHz Extern Video blanked Eco FM radio Euro
GTV Function:
FMR: ptun_SetTVFMMode
FMA..FMD: psys_GetFMDemodulatorCentreFrequency
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Philips Semiconductors
AGN Adapted Gain for Ntsc mono sound 1: +6dB gain I Sound SC
SM1..0 Sound Mute 00: no mute I Sound SC “Auto” limits noise
01: Auto-mute FM audio from digital
10: mute FM/AM audio acquisition-helper
For areas where over-modulation is expected, FMWS1,0 can enlarge the FM-
PLL window to 900kHz (effective after the acquisition is complete).
The 100kHz narrow window is only intended for FM-radio. The 225kHz window
can be used for areas where over modulation never occurs. Use 450kHz for all
other circumstances.
GTV Function: FMWS: psnd_SetFmWindowSelect
We advice to use SM1,0=0,1 for automatic muting of the mono FM-PLL
demodulator (fast attack and slow decay of 20..40ms).
Position SM1,0=1,0 can be used to mute the sound during channel switching.
Position SM1,0=1,1 will not mute at all and is reserved for test purposes.
During channel-change you can set AVLM=1 to get faster settling of the mono-
AVL-circuit to the new selected audio signal.
GTV Function: AVL: psnd_SetAVL
AVLE: psnd_SetAVLEnabledOnEastWestOutputPin
AVLM: psnd_SetAVLGain
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BPB=1, sound band pass off BP-off makes FML more sensitive
yes Follow SAW filter switching of the
M-SAW selected ?
video-colour-search
FMA,B,C= 5.5/6.0/6.5MHz = 4.5MHz Narrow
SAW filter
FMD=1, wait 3ms, FMD=0 Best order: 6.5→5.5→6.0→4.5
Wait 10ms
Read FML Need SW integration of FML bit
yes
Max 10 times ?
no
> 5x FML=1 ? 5 out of 10 or earlier
BPB=0, band pass on BP-on makes FMW more reliable
Philips Semiconductors
Wait 20ms
5 out of 10 or earlier
Read FMW
yes FMW=0 means FM-NBPLL in window
Max 10 times ?
no
> 5x FMW=0 ? ??Toggling FMD necessary for ≤ ES7.2D, to
“unstick” mono NB-PLL at: power on cycle,
Found: De-Mute search tuning and changing system or channel
With the help of some software, an audio carrier search can be implemented.
1- Simply select an FM frequency.
2- Then wait and see if the PLL demodulator can lock (bit FML).
3- Finally check if the PLL-FM demodulator is in window (bit FMW).
With BPB=1 the sound band passes are off. This makes FML more sensitive.
With BPB=0 bit FMW is more reliable. A solution is to integrate FML and FMW
by software over several read-outs.
To avoid a false lock on other carriers (4.43 MHz colour, 5.85 MHz NICAM),
the search order should be: 6.5 → 5.5 → 6.0 → 4.5 MHz.
GTV Function: mono/av-stereo: psnd_DetectStandard
After an FM carrier is found, the NB-PLL will try to stay locked. If the carrier
goes outside the frequency window (FMWS1,0), the digital acquisition helper
will quickly bring the NB-PLL back into the window.
We advice to select FMWS1,0=1,0 (=450kHz) as best compromise between
selectivity and over-modulation.
RESTRICTED, contains NDA items
Stereo sound:
Philips Semiconductors
In/Out
The digital demodulator can handle stereo and mono standards, independent
of the analogue mono-NB-PLL demodulator.
RESTRICTED, contains NDA items
InL,R5 InL,R5
Dual Scart
InL,R4 InL,R4
Tuner
HP
AM/FM AM/FM
AM
SSIF DSP LS
SSIF
output switch
input switch
SSIF
ADC
Noise I2SOUT2
2NDsound IF Beep, Control .. I2S3
gen I2SIN/OUT3
Philips Semiconductors
• 1st SIF = QSS down-mixing • 2nd SSIF with separate AGC
Analogue domain : • AM demodulation • Switch for external SSIF input
• FM mono demodulation • Analogue cross-bar switches
• Volume controlled HP output
Digital domain : • Stereo sound demodulation
• Output processing I2C write address of SSD = B0 H
• Digital cross-bar switching
• I2S In and outputs, FM stereo radio I2C read address of SSD = B1 H
• DCXO Xtal oscillator trimming
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Colour
carrier(s) Second sound carrier:
FM or NICAM
frequency
Philips Semiconductors
• Modulation Schemes for Terrestrial TV Sound Carriers:
- FM (Frequency Modulation) : most common
- AM (Amplitude Modulation) : mono & only in France (L,L1)
- NICAM (DQPSK) : Digital transmission
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25 dbx dbx
Pilot compressed Professional
compressed
15 L+R channel
5
f/fH
1 2 3 4 5 6 6.5
Philips Semiconductors
25
15 (L-R)/2 or “B” Pilot
5 (L+R)/2 FM
f/fH
1 2 3 4
RESTRICTED, contains NDA items
Demodulator / Decoder:
silence
Noise /
DCXO
I2S3
FM ident Dec AUX3/DAC1 Channel
Easy
Audio Monitor
Noise det. Programming
DemDec HW
Philips Semiconductors
• Auto L,R or dual A,B decoding, whatever standard detected or selected
(or identical to “MONO” if no multi-channel available, indicated by flags: GST,GDU=0,0 )
Philips Semiconductors
D/K Nicam 6.5 5.85 mono Nicam 27/50/80
L/L1 Nicam 6.5 5.85 AM Nicam AM index: 54/100/- [%]
FM radio Stereo 4.5 ..10.7 - MPX - 40/75/150 pilot=19kHz
TM
• DBX noise reduction included, according BTSC system specification
RESTRICTED, contains NDA items
DDEP features:
Philips Semiconductors
• Optional over-modulation adaptation to overcome problems with largely
over-modulated FM carrier (China, India...)
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Philips Semiconductors
SNDMOD Sound MODe 0000: Normal I SSD UC
0001, 0010: Hall, Matrix
0011: DPL (normal centre)
0100: DPL 3-stereo
0101: DPL phantom centre
0110, 0111: VDS 422, 423
1000: SRS TruSurround
1001: Noise sequencing
GTV Platform:
stereo: psnd_SetStandard, psnd_DetectStandard for EPMODE, STDSEL,
REST, STDREST
stereo: psnd_SetMute for DDMUTE
stereo: psnd_SetEffect for SNDMOD
stereo: psnd_SetSAPDecompression for SAPDBX
Rest of bits is not implemented
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Philips Semiconductors
ASDAC1L Idem DAC1 left output 0100: Surround
Connect any
ASDAC1R Idem right output 0101, 0110: Aux1 L, R
signal to any output
ASI2S1L Idem I2S output 1 left 0111, 1000: Aux2 L, R
ASI2S1R Idem right 1001, 1010: Aux3 L, R
ASI2S2L Idem I2S output 2 left 1011: Main Sum
ASI2S2R Idem right 1100: Digital Silence
Philips Semiconductors
Channel 2: 6.258MHz Channel 2: 6.742MHz Channel 2: 5.85MHz Channel 2: 5.742MHz
FM, Europe IDENT on FM, Europe IDENT on FM, Europe IDENT on FM, Europe IDENT on
This audio detection algorithm is executed by firmware in the audio DSP. It can
be configured by embedded (GTV) software to suit a certain application.
GTV Function: stereo: psnd_DetectStandard
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Philips Semiconductors
Adjust Back-End Possibly adapt AVL, volume-trim etc.
Found
Main Equal
Main Bass
AVL
Ext L/A
BBE
Msel + DAC2
DVB or DBB
Bass Management
or 3D sound
or TruSurround
(L+R)/2
Pseudo Hall
Matrix
VDS422/423
SW
DPL C DAC1
L/A SM
S Bass C Bass
C Equal
S
(L-R)/2
R/B C
C C
DemDec
CIN SM
Msel
(L+R)/2
S-DPL
Mono
Tre
S S S
SIN Msel Delay SM
SAP
AUX1
Volume +Trim
AUX1/I2S1 Channel SM I2S1
AUX2
Level AUX2/I2S2 Channel I2S2
SM
Adjust
Philips Semiconductors
AUX3
AUX3/DAC1 Channel SM I2S3
Noise / Silence
Audio Monitor
Level Detector
Attack / Decay Filter
(optional weighting) 1/X
UREF
Philips Semiconductors
• Weighted-mode reduces influence of bass components (optional)
Sound-Field features:
Extended
Spatial
Stereo Stereo
Philips Semiconductors
encoded
RESTRICTED, contains NDA items
TM
SRS 3D Sound:
TM
SRS TruSurround :
Philips Semiconductors
• SRS TruSurround virtualizer (422/423), SRS approved
Philips Semiconductors
• Pseudo Matrix: Centre: (L+R)/2
Surround: (L-R)/2, up to 30 ms delayed
+ +
Auto Balance
3ST
Left a2 -10 -100 -100
+ DPL a3 + a3 -10 -4.5 -100
Ph C C’
C* b3 a4 -10 -4.5 -100
-3dB 3ST
Right a4DPL -100 -100 -100
DPL a2
Sw 0 1 1
R* +
Ph R b2
+ R’
3ST b1 HP Flat Flat
+ b2 HP Flat Flat
DPL a4
Surround S* Ph S b4 S’ b3 HP HP Flat
Processing 3ST b4 HP HP Flat
Mode
DPL Phantom 3-Stereo
L L+C-3dB L+S-6dB
• BMT1 = single woofer system with improved filtering:
Philips Semiconductors
C - C
R R+C-3dB R+S-6dB small speakers for L, R, C, S plus extra SubWoofer
S S - • BMT2 = normal center mode with bass splitter (DPL):
large speakers for L, R; small for C, S (SW is optional)
• Virtualize speaker(s) for
• BMoff = wide center mode (DPL):
“Centre” or “Surround”
large speakers for L, R, C; small speaker for S
The internal Low-Pass-filter for the SubWoofer can be switched flat, to allow
the use of external SubWoofer filtering.
Philips Semiconductors
Mono
De-correlator Stereo expander
Right Out
Philips Semiconductors
• 5 bands equalisers in L/R-Main
and Centre channels @16kHz; range 30dB
• -12dB to +12dB in 1dB steps • Adjustable non-attack-level
& non-attack -frequency
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Dynamic
Ultra
Bass - II
Dynamic Virtual Bass (DVB):
Level Sensor
Left Out Advice:
Generate Auto Do not combine
higher Gain DVB, DBB, BBE
harmonics Right Out together
Right In
Dynamic
Bass
Enhancement Dynamic Bass Boost (DBB):
Philips Semiconductors
Left In Left Out
+12dB Level
Right In 0dB Sensor Right Out
60Hz
Boost
Control
• Level-dependant Bass-Boost, needs subwoofer or large main speakers
RESTRICTED, contains NDA items
TM
BBE :
Audio Delay
loudspeaker
BBE
frequency
frequency
loudspeaker
Philips Semiconductors
• Dynamic delay compensation + program driven bass/treble augmentation
• Improves reproduction of transients
• Restores brilliance and clarity of original live sound
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Left In M+L
LowL+M+L Left Out (½SW)+M+L
½SW+M+L
LowL+LowR=SW
Philips Semiconductors
Sub Woofer SW+(L-R)
control Right Out
LowR+M+R M+R
Usually one of the loudspeaker amplifiers is inverting. The low Sub Woofer
spectrum can not be reproduced by the (small) L & R speakers, so no filtering
is needed for L & R. But in this construction, the Sub Woofer speaker has to
deal with a heavy extra load (+2M+L+R).
Via software you can enable “Eco Sub Woofer” mode, that avoids this problem.
Note: the 2 loudspeaker amplifiers must have the same polarity.
RESTRICTED, contains NDA items
Philips Semiconductors
Module
• Bass & Treble: (independent of equaliser = easy control)
– Range from -16dB up to +15dB
– External resolution 1dB
– Smooth: Internal resolution 1/32dB, max. rate of change 15.6dB/sec
During power-off state the outputs “LS” and “HP” are muted.
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Clip management:
Philips Semiconductors
• Dynamic Control mode: (Set Loudness none-attack level ≤ 0dB)
Bass/Treble
active
-12dB Master Volume
+15dB +Trim
-16dB
Bass/Treble
-16dB 0dB +15dB
selected
RESTRICTED, contains NDA items
In / Out switching:
Philips Semiconductors
In/Out
RESTRICTED, contains NDA items
OutL,R2
YsyncIn
CVBSO
CVBS3
CVBS2
InL,R2
InL,R3
InL,R4
InL,R5
YUVin
RGB3
UVout
IFVO
Y,C4
SVO
Yout
Fbl3
C3
LSL,R
R
L
RIN
R
L
RIN RIN
PIP
• 1x full SCART
LIN LIN LIN
Vid Vid • 1x SCART-in
Feature
Vid Vid Vid
Stat
Fbl R / PR
Stat C • 3x CVBS
R
G G/Y
Y
• 2x S-VHS
B Loop
B / PB
AV1 AV2 AV3 • 1x DVD
OutL,R1
OutL,R2
YsyncIn
CVBSO
CVBS3
CVBS2
InL,R2
InL,R3
InL,R5
InL,R4
RGB3
RGB2
IFVO
Y,C4
SVO
Yout
Sw0
Fbl3
Fbl2
C3
LSL,R
R R PIP
RIN RIN RIN • 2x full SCART
Philips Semiconductors
L L
LIN LIN LIN
Vid Vid
• 4x CVBS
No YUV Loop
Vid Vid Vid
Stat Stat C
Fbl
R
R / PR Fbl
R/C
R/ C /PR • 3x S-VHS
Y
G
B
G/Y G
B
G/Vid/Y
• 2x DVD
B / PB B / PB
AV1 AV2+4 AV3
The DC-level on CVBS output pins allow direct coupling of a 75Ω transistor
buffer/driver:
+5V
1k
75 Ohm cable
CVBSOUT 1k
75Ω
75Ω
1k
UOC- III
YsyncIn
CVBSO
HPL,R2
CVBS2
InL,R4
InL,R2
InL,R3
InL,R5
YUVin
RGB3
UVout
IFVO
Y,C3
Y,C4
SVO
Yout
Fbl3
LSL,R
PIP
R RIN RIN RIN
L LIN LIN LIN • 3x CVBS
•
Feature
Vid Vid Vid Vid 2x S-VHS
C
PR
HP
Y
• 1x DVD
Y
PB
Loop • 1x MonitorOUT
Monitor-OUT AV1 AV2 AV3
OutL,R1
YsyncIn
HPL,R2
CVBSO
RGBF3
CVBS2
InL,R2
InL,R3
InL,R4
InL,R5
RGB3
RGB2
IFVO
Y,C3
Y,C4
SVO
Yout
Fbl3
Fbl2
Sw0
LSL,R
PIP
R RIN RIN RIN RIN • 4x CVBS
Philips Semiconductors
L LIN LIN LIN LIN
• 3x S-VHS
No YUV Loop
Philips Semiconductors
00 IF video output (CVBS1) SCART, after Sound trap & GD
01 Selected Video Output See bit INA..D YCD Y/C D etection
10 IF video input To Sound trap & Group Delay 0 CVBS signal at input
11 Spare - 1 Y/C signal detected
GTV Function:
IN: psys_SetSourceSwitch
CV2: psys_SetCVBS2InputSignalSelection
YCD: psys_GetOutputYCDetector
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77 78 79 80 75 76 74 73 YSync IN 72 71 70
U V Y Y U V
RGB3 IN2 Clamp
IN3 DVD/RGB2
RDS,TXT,CC
RGB2
YUV2..0, SYS Digital Scaling &
IE3/2 Sync Double Window IE3/2,IN3,FI
Y U V Y U V N,FINM,
ADC
ADC
ADC
DAC
DAC
DAC
RGB DVD YUV
INTF
INTF
YUV2..0
-to- -to- -to-
DVD YUV DVD VBI Fast-Insertion
CLD
CVBS & Y/C Switch
IntC
CVBS/Y3 58
Peaking,coring
DVD RGB YUV Digital RGB YUV
Colour decoder
CVBS/Y4 51
Comb
Philips Semiconductors
C4 52 DINT
C5 70
CVBSOUT 64
All input signals are “translated” into YUV or YPRPB (=DVD) and can be looped
through an external interface. In this loop you can insert e.g. a picture
improvement feature or PIP.
All input signals can be routed through the digital interface for half-screen-
compression or panoramic-zoom.
For PIP insertion you can use bit FINM to insert AFTER the digital interface.
Please note that PIP insertion always requires a Fast-blank insertion control,
so IE2 or IE3 and pin Fbl2 or Fbl3 must be activated too (but must be inactive
during vertical).
GTV Function:
FINM: psys_SetFastInsertionMode
INTF: psys_SetAmplitudePolarityYUV
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Philips Semiconductors
I 1 000 - RGBF3 input (IE3=1) RGBF3 priority over Y/C
CVBS5 or Y5/C5
J 1 111 - DVD3 input (IE3=1) DVD3 priority over Y/C
• DVD = YPRPB = colour bar 100% saturation: Y= +1.0VPP, PR= +0.7VPP, PB= +0.7VPP
• YUV = colour bar 75% saturation: Y= +1.4VPP, U[B-Y]= -1.33VPP, V[R-Y]= -1.05VPP
• For insertion, always IE3/2 and pin Fbl3/2 must be activated (not for loop interface)
GTV Function:
YC: psys_SetCVBS
IE: pimg_SetRGBYUVBlankingEnable
YUV: psys_SetRGBYUV
INTF: psys_SetAmplitudePolarityYUV
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0 1 0 x low
Both
1 1 0 high low If input-2 and input-3 are of the W hen both are RGB,
Both
Philips Semiconductors
RGB2 completely
1 1 1 x x priority over input-2
Input Output
• While FIN=1, pins Fbl2+Fbl3 are not in use but they can still Fbl3 Fbl2 IN3 IN2
be read via IN3/IN2 ⇒ useful as digital inputs low low 0 0
low high 0 1
• FINM=1 inserts fast-insertion after digital interface (PIP), high low 1 0
full-insertion remains before digital interface high high 1 1
Bits IN3 and IN2 (while FIN=0) are sampled during the vertical interval (VBI).
This allows software to detect the difference between fast-OSD-RGB-insertion
(Fast-blanking overlay on just a few lines) and full-screen RGB insertion. Only
during full screen insertion the Fbl3/2 line will be permanently high (so also
during VBI).
GTV Function:
FIN: psys_SetForcedInsertion
FINM: psys_SetFastInsertionMode
IE: pimg_SetRGBYUVBlankingEnable
IN: psys_SetSourceSwitch
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Philips Semiconductors
• PIP insertion AFTER feature loops: set FINM=1 & use Fast-blanking
1. Insertion can always be done into a YUV- or DVD-loop interface
2. PIP can best be inserted as YUVF2, or in series with RGBF3 (via own switch)
3. Dual full-SCART with 2x RGB can only enable one RGB at a time
RESTRICTED, contains NDA items
PIP use-cases:
PIP insert
RGBF or YUVF FBL Y U V
Y PIP not
Compressed
74 73 75 72 71 70
Philips Semiconductors
PIP insert
R
G
RGBF or YUVF
B +bypass RGBF
FBL G B R
FBL
+ Now PIP can show
RGB/YUV input
75 72 71 70
HPVC
SIF
InL,R2 InL,R2
FM FM
AM AM HP
QSS
FM
AM
LS Optional
SSIF
DSP DAC1
SSIF ADC
SMLS
SSIF LS1
ADC
AC3 DSP
Dec I2SOUT1 LS3
DSP I2S1 DAC
I2SOUT2 LS4
Noise gen I2S2
External I2S3 I2SIN/OUT3 DAC LS5
2ND sound IF LS6
I2SIN for test purposes
Philips Semiconductors
• SCART: DAC1 = Front-End signal InL,R1 (from tuner)
• DAC2 available for monitor (outputs LS), when I2S DACs are added (LS1..6)
GTV Function:
SAS register is used in psnd_Connect to establish signal paths.
Bit HPVC has no implementation (initially set in LibCoMa)
RESTRICTED, contains NDA items
Stereo use-cases:
Right Left
Audio DSP
Digital
DAC2 Right
DemDec
Centre LS
DSP
DAC DAC1 Centre
UDA1334BT Surround
I2S1 Surround
I2S2 DAC
UDA1334BT
Sub Woofer DAC2
I2S3
SRC SPDIF • Monitor output is sound controlled
• Headphone independently switchable
Philips Semiconductors
InL,R2/3/4/5 Dual Scart InL,R2/3/4/5 Dual Scart or OFF
FM 8 : 1 8:1 VOL FM 8 : 1 8:1 HPCV
AM AM
FE HP OFF or Centre
OFF or Surr
DemDec
DemDec
LS LS
DSP
DSP
DAC1 Left DAC1 Left
Right Right
DAC2 DAC2
Full DPL:
In European SCART chassis, the tuner signal (Front-End) must always remain
present at the SCART output. This occupies DAC1. A full Dolby Pro-Logic
implementation with 5 loudspeaker channels requires two external I2S DACs.
Virtual DPL:
The sound DSP inside UOC- III “Hercules” can also virtualize DPL, requiring
just two audio amplifiers.
European Eco DPL:
This option allows the TV-user to decide between either SCART-Front-End-
sound output or four independent channels for DPL. The Sub Woofer channel
can be virtualized or connected between L&R amplifier outputs.
Asia DPL:
Asian TV chassis normally have a “monitor” output that reproduces the same
audio & video as displayed on the TV screen (so Front-End = inactive while
external sources are selected). If you don’t implement independent
HeadPhones control, then 4 channels are available for DPL reproduction.
RESTRICTED, contains NDA items
I2S-DAC application:
1Ω
1Ω
Xtal
DCXO
24.576MHz
VSSD
VDDA
VSSA
VDDD
VREF
100Ω OutL
I2S_CLK = 256*fS SysClk
220k
:4 Sfor1
BitClk = 64*fS I2S_CLK BitClk
Sfor0
I2S_WS = fS I2S_WS WordSel 100Ω OutR
220k
I2S_D0 Data
PCS
I2S_D1
Mute Deem
I2S_D2
UDA1334
I/O pin
Philips Semiconductors
UOC- III “Hercules”
UDA1334
• I2S_Clk can be set 4 times faster to act as SysClk for noise shaping
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Philips Semiconductors
BITS FUNCTION SETTING I / O MACRO FU REM
H P V C H ead P hones V o l u m e C ontrol active 0: bypassed I Sound S C Better S/N
S M L S S ound M ute L S outputs 1: LS outputs muted I Sound S C Not HP outputs
DSG D efine S ound G ain from input to output 0: 0dB, 1: +6dB I Sound SC +6dB needs 8V
GTV Function:
psnd_Connect
psnd_SetMuteChannel
RESTRICTED, contains NDA items
Philips Semiconductors
011 SWO high output = 4.5V O Switch output
2.1V+Ref OUT
100 Reference carrier input for I Ref to DVB 33
DVB down-mix (REFIN) IF down mixer +4.5V Mix Ref input
101 SSIF to NB-PLL and Stereo Dec. I SSIF
To Stereo Decod. SSIF input
111 SSIF input to mono NB-PLL, I
To mono NB-PLL 330..10kΩ
intern SIF to Stereo Decoder CMB2..0
From intern SIF
The function of these pins depend on the chosen application, e.g the capacitor
for mono-AVL can be connected at pin 21 or pin 33.
CMB2..0=000:
In a mono-FM-configuration pin 33 can be used to connect the AVL capacitor.
CMB2..0=101 or 111:
By setting bit SSIF=1, pin 33 can become a Second-Sound-IF input. Useful for:
- FM-radio
- external sound band pass filter for 2nd of dual-carrier sound 4.724, 5.74MHz
- extra selectivity (4.5, 5.5, 6, 6.5MHz) for extremely difficult signal
circumstances
GTV Function:
QSS: psnd_SetQSSAmplifierMode
FMI: psnd_SetQSSAmplifierOutputSelection
AM: psnd_SetQssAm
E2D: ptun_SetAudioSignalOnAUDEEMPin
CMB: psys_SetCombFilterControl
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Int
Ext CVBS1 Int CVBS Out
SCART1-output is
SVO DeEmph Sound Out always Front-End
FM 15k (tuner)
E2D
Int
Int Monitor
Philips Semiconductors
CVBS1 Int CVBS Out
Ext Out
SVO
DeEmph Sound Out
FM 15k Monitor-output is
E2D viewed source
Int
Asia-Pacific
Select VOL
Philips Semiconductors
• UART added for communication to add-on micro (DVB, DVD)
GTV Function:
3 level output: rbsc_SetMLPort
Analogue value readout: rbsc_GetADC
Switching from output to input an setting a value: rbsc_ConfigPort,
rbsc_SetPin
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Vguard-input + I/O:
VGM1 VGM0 Mode of pin Vguard
LED
560
4.5V Vertical
VGM1,0 blanking
Vguard 13 period
47k
Sample
3.6V Blanking of
& Hold
NDF RGBOUT pins
TDA8357 EVG=1
Philips Semiconductors
• Double use of Vguard-input-pin (e.g. as LED driver or as Mute-output)
• Input: read bit NDF (=1 when guard-pulse fails), Vertical protection if bit EVG=1
• Open-drain Output : low when LED=1, floating during Vblank (1ms out of 20ms)
GTV Function:
NDF: psys_GetVerticalOutput
EVG: psys_SetVerticalGuardMode
LED: psys_SetModeLEDDriver
RESTRICTED, contains NDA items
100k
1/
Config. 7
180 S2 RL2
2/
7
UOC III “Hercules” 240 S3
3/
7
330 S4
Upper 0.75V of ADC range 4/
7
can not be used, due to 470 S5
+5V tolerant-construction 5/
Philips Semiconductors
7
of I/O pads. 820 S6
6/
7
Reading back the ADC input costs just a few micro seconds. This is not
noticeable in the light output of the LED.
The ADC input range VDD,MINIMAL- 0.75 Volt is lost, due to internal protections
that make I/O pins 5V tolerant.
The ADC input has 8 bit resolution, so the resistor ladder network can be
increased to handle more keys. In the application however, one should allow
enough margin between the levels to handle noise from large currents flowing
through ground tracks, cross talk etc.
GTV Function:
rbsc_GetLocalKeyboard
rbsc_SetLEDState
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25.25%
1K2
R0
(due to +5V tolerant-construction of I/O pads)
ADC
0.75 * 100 / VDD,MIN = 75 / (3.3 * 90%) = 25,25%
½
Highest usable level = 255 * 74.75% = 189D = BDH
1 S6
820
• Divide this into the no. of keys you want, R6
1 S5
e.g. into 7 areas
470
SW level R5
1 S4
• Position each switch in the middle of its area,
330
SW level R4
S0 needs only ½ area (no tolerance below zero) 1 S3
240
R3
• Reserve ½ area noise margin above highest switch
Philips Semiconductors
1 S2
180
R2
• Choose e.g. R0 = 1.2kΩ (not too high, for noise immunity) 1 S1
150
R1
½
• Re-calculate levels with REAL resistors S0
1k5
3.3V 3.3V 3.3V 3.3V 10k +3V
1k
47k
47k
Config Config Config
Hi
Low Mid High
47k
47k
Mid
47k
Out Out Out
Lo
10k
Philips Semiconductors
Lo =Off
Open-Drain and Push-Pull +3V Mid=VCR stby
10k
Hi =On
47k
47k
a TV+VCR combi Standby-VCR
UOC III 10k
GTV Function:
3 level output: rbsc_SetMLPort
Switching from output to input an setting a value: rbsc_ConfigPort,
rbsc_SetPin
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Power:
Philips Semiconductors
In/Out
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Philips Semiconductors
• Set µC SFR bit ROMBK.STDBY=1 to disable: VSP, OSD, RDS, TXT/CC-
acquisition and Stereo sound Decoder (SSD)
• Set SFR bit PCON.IDL=1 to halt SW execution of the 80C51-µC, while
PWM, RCP, UART, I2C, INT, Timers/Counters, WatchDog stay active
When H+V deflection is not needed (e.g. VCR-mode or LCD-TV), all other
functions in the VSP can be kept active, simply by maintaining +5V.
If any of the +5V supply inputs fail (or too low), each has a supply-guard
detector that will immediately stop the related functions in the VSP.
In µC-STDBY mode the 8051 core remains fully functional, but the VSP is put
to sleep.
Before going into µC-IDLE mode, the software should enter µC-STDBY mode
first. This takes care that after wake-up from IDLE mode, many circuits stay off.
GTV Function:
fpmt_SetPowerState
psys_SetTVProcessorStandby
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Power Modes:
Standby
(extern)
DecDig
needed
+3.3V
+1.8V
2.5VOUT
(+5V)
part part
+5V
+8V
Application
on
190mA 2mA 100mA 280mA STB=1 on On = All functionality available
mode
on
on VCR mode = Front-end still active
VCR 190mA 2mA 100mA 280mA STB=0 tuner
Deflection off
transition no - ??mA - STB=0 off µC fully functional (set OSD=off)
off
Standby 40mA limited µC-STDBY mode (Remote wake-up)
Sleep
no - - STB=x
coma Clock µC-POWERDOWN mode
Stop ??mA
stop Re-activate via INTerrupt or reset
Philips Semiconductors
• Startup Standby ⇒ Application mode can be done from 3.3V-only
• Mode Stop = Clock off ⇒ slower wake-up ⇒ check compatibility
with Remote Control protocol (may miss first command, mode STOP needs repeating
full command codes like with RC-5)
In Standby & Idle the external 1.8V for the u-processor is switched off. Only a
part of the digital core is kept alive, to detect wake-up events, by an internal
1.8V, derived from the 3.3V standby supply.
It is even allowed to generate the 1.8V in the line output stage, when switching
to Standby & Idle, this 1.8V supply will automatically be 0. To get the lower
power consumption, the digital Micro-core still has to be switched to IDLE
mode (bit PCON.IDL).
In the transition to Standby mode, the micro must first disable the OSD.
In mode Stop the internal clocks are halted. Re-starting takes more time.
Therefor this mode is not suitable when a RC-protocol is used that doesn’t
repeat the whole command code at every key-repetition (e.g. NEC: sends key-
code only once, followed by fixed repeat-codes). If you missed the first
command, you can not detect what it was
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Philips Semiconductors
SW set SFR PCON.PD=1
HOUT = active HOUT = off VSP disabled
+5V = needed +5V = not required 1.8V loop off
1.8V loop active 1.8V loop active OSD/TXT/CC off
For minimal TV-sleep-mode power we advice to use the RCP. This will reduce
the number of false wake-ups significantly. As estimated average TV-sleep-
mode power you can use: 90% µC-IDLE-current + 10% µC-STANDBY-current.
47k
R
47k
R
VddPeriphery µC
VddAnalogue 93 +1.8V2
Audio SDACs Audio ADCs 140mA
96 +1.8V1 ??Temporary reset
Video ADCs
Audio SDACs (dig.) 3 solution for ≤ ES7.2D
100, 117, 124 140mA samples: “System
DecV1V8 118 Consistency Check”.
I/O 10µF 1k
See next slide.
PWM 114
+1.8VddCore
ADC
I/O Buffers
4k7
INT 1.8VEXT ≥ 80% V1V8Se 1.8Vfeedback
Source=3mAMAX
25mA Sink = 1mAMAX
1.8V +3.3VddA1 DDLE 2.5V 14
SDA max DecDig (2.5V)
IrefO
SCL
INT,Timers,
Sleep mode
controller
Philips Semiconductors
+Vp3 for RGB 82
+Vdd for Comb 69
+8V
• All µC-I/O lines use 3.3VddP +Vp for ScartAudioOut 45
(1.8V is used only internal, most I/O pins are 5V compatible)
• ALL 3.3V supply inputs must be connected to the same net (all 5V inputs also to one net)
+3.3VSTANDBY is used for I2C, H-drive and to generate 2.5V DecDig. With simple
transistors the 1.8V supply for the digital part can be made. Via pin 96 this is
monitored (DDLE=1) to adjust the 2.5V DecDig, keeping the 1.8V within limits.
When the DecDig voltage is OK, setting bit STB=1 can start the horizontal
deflection (=LowVoltageStartUp: only 3.3V input required).
Note: the external 1.8V should not be available before 3.3VSTANDBY.
DDLE=0 makes 2.5V DecDig independent of the 1.8V feedback signal. Use
this if you want to apply an external 1.8V instead of the self controlled loop.
When the digital core is switched to a SLEEP mode (µC-STDBY, IDLE or
POWERDOWN), the 2.5V DecDig switches off. As the external generated 1.8V
drops below 80%, an internal 1.8V supply (pin 118, derived from 3.3VSTANDBY)
takes over and many circuits are disconnected. Pins 93+96 must de switched-
off; all other 1.8V inputs are allowed to stay on: temporarily powered via pin
118 (1.8V supply transistors should NOT pull current OUT of pin 118).
The 1.8V for the 80C51 core is monitored by a reset circuit. When this
decoupled voltage is less than 1.2V, a reset is generated.
Whenever pin DecDig drops < 2.0V, a POR is generated for the VSP and all
I2C-bus registers must be re-written (including DDLE). Below 2.0V bit DDLE is
ignored, to guarantee start-up of DecDig. At first-power-up the 2.5V DecDig
always goes high, to assure proper start-up of the IC.
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Philips Semiconductors
for start-up of power supplies. Still we advice to reserve a pin (114,
push-pull-configured) plus 1 transistor for the "full reset"
??
The current ES5.2 samples of UOC-III (with Picasso-10) sometimes show a
failure at start-up, dependent on how the various power-supplies are rising.
Should you experience such problems, we can offer you a combined HW/SW
solution to overcome this. In future samples this will be repaired. For the time
being, we advice to use one I/O pin to be able to force a “full reset” by short-
circuiting pin 118 to ground (150mA). Use e.g. pin 114 that is LOW during reset
(= all I/O-pins except HW+SW-I2C pins). Keep 114 low unless you want to
trigger the reset. As a result, pin 114 will again be made low by the reset.
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A Short- No With
Problem? Problem?
RPROT
C
47k
cirtcuit protection protection
A No 1.8V No No 1.8V No
B B VDD=3.3V Yes VDD pulled up, No
T2 protected by zener
T1 VDD=2.1V, No
VDD 1.8V C VDD=3.3V Yes
protected by zener
D D T2 Yes No 1.8V, T2 No
4k7
Philips Semiconductors
• DecDig can source max. 3mA or sink max. 1mA
Total load on 1.8V is about 300mA (including sound DSP)
• Don NOT pull current out of 1.8V supply inputs
• VDD1.8 > 2.1V shortens lifetime drastically. A built-in detector (bit SUPR=1)
signals this unwanted situation (e.g. show error message on OSD)
The UOC- III “Hercules” avoids the need of (expensive) 1.8V stabilisers.
Instead, it offers a 2.5V (3mA) output (pin DecDig) for an emitter-follower
(PNP-boosted NPN), with analogue feedback via 1.8V input pin 96.
Note: It is not allowed to pull current out of the 1.8V inputs. Use emitter- or
diode-type to supply these pins (or supply 1.8V out of 3.3VSTANDBY).
Philips Semiconductors
• X-ray protection: (anti-glitch : condition must be active > 1µs)
– pulling pin 32 “EHTO” > 3.9V sets XPR=1 & forces slow-stop of HOUT
– XDT=1 disables auto-switch-off, but error condition (XPR=1) can still be read
Status bit XPR is latched and cleared after an I2C-bus read action, unless the
fault condition still exists. XPR is triggered when the EHT-compensation pin 32
is forced outside its normal operating range (1.2 .. 2.8V), above 3.9V. XPR=1
will cause a slow-stop of the horizontal line drive (HOUT, pin 67) plus discharge
of the picture tube (OSO=1). This protection can be disabled by setting XDT=1.
Hint: Pin 32 can be used for switch-off via the mains switch, using an external
detection circuit to monitor when the supply voltage drops.
Pulling phi-2 pin 17 above 4.1V will immediately stop HOUT. If pin 17 is left
floating again, the line drive will automatically restart (Unless software reacts to
protection bits like SUP before HOUT is restarted) :
- with DFL=0 it will do a gentle soft-restart.
- with DFL=1 it will immediately continue with normal HOUT periods. This gives
fastest recovery, but make sure that your line-deflection stage can handle it.
Status bit NDF is NOT latched. It is cleared after the fault condition is removed.
In some chassis during source- or channel-change the vertical guard pulse is
missing for some frames. Therefore we advice to check NDF=1 during at least
> 200ms, before reacting to it in software (e.g. switch to standby).
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• Software must read POR until POR=0 (POR and XPR are cleared after reading)
Philips Semiconductors
• New: If Flash-prot did shut-down HOUT, SW can detect this via DFL4..0
• HOUT slow-start process takes at least 1175ms (DFL4..0)
Status bit POR is cleared after an I2C-bus read action, unless the reset
condition still exists.
POR is only related to the 3.3V part of the VSP and the reset input. It has
nothing to do with the 5V part. When POR=1, all I2C register data needs to be
rewritten: after POR=0 again.
Bits DFL4..0 represent the status of slow-start (-stop). With DEFL=1 the
software can read this to monitor the line-start-up (-shut-down) process.
GTV Function:
POR: psys_GetTVProcessorPOR
STB: psys_SetTVProcessorStandby
DEFL: psys_SetReadOutDeflectionTimerControl
DFL: psys_SetFlashProtection
EVG: psys_SetVerticalGuardMode
NDF: psys_GetVerticalOutput
DFL: psys_SetFlashProtection
XDT: psys_SetOvervoltageInputMode
XPR: psys_GetXrayProtection
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Philips Semiconductors
• ⇒ MSU / LSU : SW has to toggle STB:=1→0→1, before HOUT restarts
+ execute “TV-Switch-On” (can not restart automatic because 5V derived from line deflection)
Important : when the 5V falls below a certain level (4V), other protection bits
can accidentally get triggered. If e.g. XPR=1, the HOUT will NOT automatically
restart. Therefore all UOC- III “HERCULES” software should continuously check
POR, XPR (or disable the protection functions).
GTV Platform:
SUP: psys_GetTVProcessorPowerSupply
SUPR: psys_GetSupplyProtection
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OUTPUT BITS important for PMT
Bit name Bit function Remark
POR Power on Reset
XPR Xray prot
NDF No vert. defl
SUP Supplies OK
SUPR 1.8V to high prot
setoff read back when soft stop has finished
dfl0..dfl4 read back of deflection timer
GTV Function:
STB: psys_SetTVProcessorStandby
SDC: psys_SetDutyCycleHorizontalDrive
OSO: psys_SetVerticalScanAtSwitchOff
VGM: psys_SetFunctionVguardSwioPin
DFL: psys_SetFlashProtection
XDT: psys_SetOvervoltageInputMode
FBC: psys_SetFixedBeamCurrentSwitchOff
RBL: pimg_SetRGBBlanking
RGBL: pimg_SetRGBOutputBlanking
DDLE:
RED: psys_SetREFOKBit
DEFL: psys_SetReadOutDeflectionTimerControl
SSD: psys_SetSlowStartUpMode
POR: psys_GetTVProcessorPOR
XPR: psys_GetXrayProtection
NDF: psys_GetVerticalOutput
SUP: psys_GetTVProcessorPowerSupply
SUPR: psys_GetSupplyProtection
DFL: psys_SetFlashProtection
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On / Off flow:
Store cap-bank value in Eeprom SW should recall this value every time
“Power-On” AC-on
?? Consistency Check +5V & 1.8VEXT available @ reset
To TV-standby
On or Off ? Go into TV-standby or switch-on ?
On
??Check SSD availability Load optimal value from Eeprom
“Load DCXO cap-bank” Check for start-up problems
“TV-Switch-On”
Philips Semiconductors
No
Serious problem?
Yes Main Loop:
“Safety-Shut-Down” “Regular Check OSD, SSD”
<3 No
Retry max. 3x Off ?
Yes
“TV-Sleep”
Power Topologies:
1.8VEXT 5V
Mains
• MSU= Mixed Start-Up supply
SMPS
3.3VSTB
UOC-III
“Hercules” HOUT FBT
/LOT
– +1.8VEXT from main-SMPS ?? ES7.2D: 5V must be present during
– +5V from Line deflection LOT/FBT reset, use DSU instead
Philips Semiconductors
?? 1.8V from Line not possible yet,
use DSU instead 5V, 1.8VEXT
Mains
UOC-III
supply 3.3VSTB HOUT FBT
• LSU= Line-voltage Start-Up SMPS
“Hercules”
/LOT
Moment of AC-on
E:
4.0V SUP=OK level
Philips Semiconductors
D: detector level
C: µC reset starts
DCXO forced
0V
• If 3.3VSTB has risen > 2.7V, the VSP-digital part is in control & forces HOUT=high
• 2.5VDECDIG & 1.8VPERMANENT will come-up too (µC internal reset sequence begins > 1.2V) until
software starts running, then SW enables 5V & 1.8VSWITCHED
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THEN SW switch “TV-Sleep”
ELSE
- SW refresh configuration control of µC & SSD and SW Reset-OSD
- SW make sure µC is NOT in SLEEP-mode (µC-STBY/IDLE/POWERDOWN)
- SW read VSP status until VSP-POR=0
DSU/MSU: TV-Switch-On
Philips Semiconductors
– IF startup fails (too long > 5s) (SW check DFL4..0 )
THEN do a “Safety-Shut-Down” (and blink error LED)
ELSE (no need to check SUP ⇒ is already part of DFL4..0 during slow-start)
– IF VGUARD used (EVG=1 to enable VGUARD-protection)
THEN check that vertical reads back NDF=0 within 1000ms
– Optional: SW (re-)enable desired protection DFL
– Start up the CCC loop (black current + RGB gain stabilisation)
The slow-start-process begins with setting STB=1. If DEFL=1 the SW can now
monitor the start-up of HOUT. Normally this takes 1175ms unless any protection
mechanism is activated. Should the start-up take much too long (>5s), then
software can best do a safety shut-down (e.g. retry 3 times and then stay off).
Set STB=0, switch-off and show the error (e.g. on an LED).
If a vertical guard pulse is connected, bit NDF (No DeFlection) can be checked
to verify correct operation of the vertical deflection stage. Use this option
always together with EVG=1 (Enable Vertical Guard), to mute the display and
prevent damage to the picture tube. If software keeps on reading NDF=1 for
more than 1000ms after SUP=1, apparently the vertical deflection is damaged.
Set STB=0, switch-off and show the error (LED).
Philips Semiconductors
then switch off & remain in standby (blink error LED, signal WHY)
ELSE
IF XPR=1 (Xray prot via EHT pin)
or DFL4..0 < 0FH (flash prot triggered)
THEN TV-Switch-On (fast)
Regular check:
When the TV in running, the timing for error conditions is different from the
“cold” start-up timing.
Some status bits are latched (POR, XPR) others are not. All status bits should
be read within one I2C-bus message. This avoids that one routine clears a
latched bit, that should have been read by another routine.
GTV Function:
LibCoMa settings for the time-out of violations
psys_GetProtectionViolation
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Reset OSD:
Philips Semiconductors
• SW Reset-OSD consists of:
– Mute sound, switch SSD=off
– Switch-off DINT=0
– SW toggle bit SFR ROMBK.D6:= 0→1 (⇒ resets OSD & all except 8051 core)
GTV Function:
Interrupt definition in fpmt_dcn.c file
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DSU/MSU: TV-Sleep
•
• SW read DFL4..0 & wait until < 02H?? (Hdeflection ready with slow stop process)
• Disable supply for FBT/LOT
• Temp. for N1C??: disable EDET
• SW set µC SFR ROMBK.STANDBY=1 (DecDig falls low)
Philips Semiconductors
– Upon RCP interrupt: temporary in STANDBY, then return to IDLE mode
• Upon wake-up:
– re-enable WatchDog, Keyboard, SFR ROMBK.STANDBY=0
– Temp. for N1C??: re-enable EDET & discard one false EDET-interrupt
– TV-Switch-On
– µC-SFR register:
• P3DCXOCTRL.D6..D0 (POR value = factory-FLASH-value )
• P3DCXOCTRL.CAPMUX (1= from SSDNICAM , 0= from SFR)
Philips Semiconductors
– SSDNICAM register: (non-SSD versions: set CAPMUX=0)
• DCXO_CTRL_REG.NICPLCENTER (POR value = 3FH,7bit = 3F8H,10bit)
• DCXO_CTRL_REG.NICPLPLIM (Frequency-range limiting)
• DCXO_CTRL_REG.NICPLSCALE (Phase adaption speed)
GTV Function:
psys_SetCrystalAlignment
psys_GetCrystalOptimumViaNicam
psys_GetCrystalOptimumViaColour
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– µC-SFR register:
• I2S.I2S_CLK1..CLK0 (I2S bit clock, 00 = 256 x FS)
• I2S.EN_I2SCLK (1 = I2S bit clock out, 0 = GPIO)
• Remarks:
• 256 x FS = 8.192 MHz = DCXO output frequency / 3
• I2S output clock can be made visible on GPIO pin 103 (P0.3/I2SCLK)
Philips Semiconductors
• I2S output is only available in full stereo or AV stereo version
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– SSDDEMDEC register:
• DDEP_CONTROL_REG.DPMODE (DEMDEC easy programming mode)
• DDEP_CONTROL_REG.STDSEL (Standard selection)
• DDEP_CONTROL_REG.REST (Reset DEMDEC)
– SSDINFO register:
• INF_NIC_STA_REG.VSP (Identification of NICAM sound)
• INF_NIC_STA_REG.CO_LOCKED (NICAM frame and CO sync.)
Philips Semiconductors
– SSDDEV register:
• INF_DEV_STA_REG.VDSP_C (NICAM decoder VDSP flag)
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• During DCXO tuning, the internal 24.576Mhz reference VCO of the VSP could
loose its lock to the DCXO. No-lock sets bit SUPOK=0 and HOUT will switch-off.
This is prevented by setting bit red=1 during DCXO tuning
Philips Semiconductors
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1. Per IC you can read back it’s FLASH-value via P3DCXOCTRL.D6..D0, directly
after µC-POR
2. For a specific IC+application, find it’s best ABSOLUTE-value:
-A- NICAM test signal ⇒ read back from NICPLCENTER (CAPMUX=1)
-B- SW controls cap-bank ⇒ measure frequency e.g. via I2S clock output
-C- Colour test signal, determine middle of colour locking range
⇒ read back from P3DCXOCTRL.D6..D0 (CAPMUX=0)
Philips Semiconductors
3. OFFSET-value = ABSOLUTE-value – FLASH-value
Store the OFFSET-value in Eeprom (Nvmemory)
4. Combine this OFFSET-value per IC with it’s own FLASH-value
• Remark: when each individual TV is aligned, you can also store the
ABSOLUTE-value of it’s IC in Eeprom
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• Load SSD with FLASH-value (read-out via SFR, directly after POR)
– Set DCXO_CTRL_REG.NICPLPLIM to 0x1FF (511=max)
– Set DCXO_CTRL_REG.NICPLSCALE to 0x0 (0=max range, scale 1.0)
– Set DCXO_CTRL_REG.NICPLCENTER to 0x0
• Set-up the DEMDEC in the SSD (via DDEP_CONTROL_REG)
– Set EPMODE (bits 1..0) to 0x01: Static Standard Selection mode
Philips Semiconductors
– Set STDSEL (bits 6..2) to 0x05: B/G NICAM
• Re-start the DEMDEC to acquire NICAM (via DDEP_CONTROL_REG)
– Set REST (bit 7) in DDEP_CONTROL_REG to ‘1’
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• Save in Eeprom
• Set COSMICSYNC1 bit red=0 (reg 0x3E.bit 6)
Philips Semiconductors
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Philips Semiconductors
• Set COSMICSYNC1 bit red=0 (reg 0x3E.bit 6)
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Philips Semiconductors
• Save this in Eeprom
• Set COSMICSYNC1 bit red=0 (reg 0x3E.bit 6)
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Philips Semiconductors
• N1B: Note: non-SSD version is not possible for N1B !!!
POR
I2C
STB
Philips Semiconductors
Hout Sl.Start Sl.Start Sl.Start
When POR=1, read till POR=0, write all I2C registers with STB=0. Then set STB=1
POR is reset to 0, at the first I2C status register-read after 3.3 Volt supply > 2.50 Volt
1 When POR = 1, software must read till POR = 0. Then all I2C
registers must be written with STB = 0
Pending on the power supply:
5 V from main supply: check SUP = 1
5 V from FBT: Low Voltage Start-up, no extra check needed
Then write STB = 1
2 When the power drops shortly (spike )below 2.50 V, POR is set to 1
and latched. H-out is immediately switched off.
When the software detects POR = 1, the start-up procedure as in 1
must be repeated
3 When the power drops below 2.50 for a longer time, Hout is
immediately stopped and the device is put in reset condition
4 Once the voltage rises above 2.50 V again, the start-up procedure as
in 1 must be followed
The presence of the 3.3 Volt is basic for reliable working of the µprocessor part
and the digital part (I2C registers and Hout drive circuit). Checking the 3.3 V
regularly by reading POR and taking appropriate action when POR = 1 has
absolute priority over all other matters. The µprocessor will not work when 3.3V
is too low (< ~1.9V).
GTV Function: LibCoMa settings for the time-out of violations
psys_GetProtectionViolation
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SUP
STB
+3V3 stays intact
Automatic Automatic
4.1V
Pin 17
Philips Semiconductors
PHI-2
3.9V
Pin 32
EHTO
XPR
We assume the 3.3 Volt is OK. Note that the 4.0 level of the + 5 V supply
has in reality a hysteresis of about 0.2 Volt (4.1 V SUP → 1, 3.9 V SUP → 0)
1 Check SUP = 1. Write STB = 1. Then Hout will begin via Slow Start.
2 When 5 V supply drops below 3.9 V, Hout will be stopped according the
Slow Stop procedure. The RGB outputs are immediately blanked.
3 When the supply rises again above 4.1 V, Hout will automatically
start again via Slow Start
4 The Flash protection is activated when the voltage at pin 17 is kept ≥ 4.1V
longer than 1 µs. Hout is immediately stopped to protect the line transistor
and RGB outputs are blanked. When pin 17 drops again < 6 Volts, Hout is
automatically started via Slow Start.
5 The Overvoltage protection is activated when the voltage at pin 32 is
kept above 3.9 V longer than 1 µs. XPR is set to 1, Hout is switched
off according the Slow Stop procedure, RGB outputs discharge the
EHT and the IC is set in Stand-by. When XPR = 1, software must
read till XPR = 0, then write STB = 0 followed by STB = 1
6 Writing STB = 0, Hout Slow-Stops and RGB outputs discharge the EHT.
GTV Function:
STB: psys_SetTVProcessorStandby
SUP: psys_GetTVProcessorPowerSupply
XPR: psys_GetXrayProtection
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SUP
STB
Handling differs from previous slide !!
Hout LSU Slow St. LSU LSU Slow St. LSU Slow St.
4.1V
Pin 17
Philips Semiconductors
PHI-2
Pin 32 3.9V
EHTO
1 When the 3.3 V is ok and all I2C registers are written, STB can be
set to 1. Hout performs a Low voltage Start-up via Slow Start
The 5 Volt from FBT will rise. At 4.1 V (0.2 V hysteresis.) all other
video processor blocks are released (including RGB outputs)
2 When the 5 V drops below 3.9 V (e.g. due to overload), H-out will
stop according the Slow Stop procedure and the RGB outputs are
immediately blanked. Because the Hout is stopped, the 5 V will not
return any more. The µprocessor can check this by monitoring the
SUP bit. A new Low Voltage Start-up must be initiated by writing
STB = 0 followed by STB = 1.
3 Activating the Flash protection stops immediately Hout and blanks
the RGB outputs. Also now the 5 V doesn’t return because Hout is
stopped. A new Low Voltage Start-up must be initiated by toggling
STB (see 2)
4 Activating Overvoltage protection stops Hout via Slow Stop, RGB
outputs discharge the EHT and the IC is set in Stand-by.
The µprocessor must check XPR and SUP and when XPR = 0 initiate
a new Low Voltage Start-up by toggling STB.
5 Setting STB = 0 switches off Hout via Slow Stop and the RGB
outputs discharge the EHT.
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Philips Semiconductors
In/Out
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Philips Semiconductors
• H & V Zoom function for 16:9 + (digital) Panorama
• Slow Start / Stop procedure
The low voltage start-up (LVS) makes it possible to initialise the horizontal
drive using only 3.3 V. It is possible to supply the +5 Volt from scan rectification
of the FBT/LOT.
Parallelogram and Bow correction are available for applications with real flat
picture tubes.
When vertical is zoomed out more than 105%, the extra over-scan is blanked
to prevent picture tube damage.
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With bit SDC the duty cycle can be changed from 55:45 to 60:40 when STB=0
time
Switch Off
TON %
25%
Philips Semiconductors
0 1175ms
24µs 24µs 8µs 24µs
1mA picture tube discharge, during 38ms
43ms
During slow start, the off-time of HOUT is kept fixed at 28.8 µs. The on-time
increases from 0 to 35.2 µs (for 55:45 duty cycle). In this way, overstress of the
line transistor is prevented and the EHT builds up gradually. The three speed-
variations even enable the use of very large picture tubes with a “DAF” gun.
During switch-off, the Hout frequency is doubled immediately and the duty
cycle is set to 25% fixed, during 43 ms. The RGB outputs are driven high to get
a controlled discharge of the picture tube with 1 mA during 38 ms. This will
decrease the EHT to about half the nominal value (= safety requirement). For
this feature, the RGB amplifier must be able to return a 1mA “Iblack”
measurement current (like TDA6108A).
When bit OSO is set the white spot/flash during switch off will be written in
overscan and thus will not be visible on the screen. Careful application must
guarantee that the vertical deflection stays operational until the end of the
discharge period.
With bit SDC the duty cycle can be changed from 55:45 to 60:40 when STB=0.
GTV Function:
STB: psys_SetTVProcessorStandby
OSO: psys_SetVerticalScanAtSwitchOff
SDC: psys_SetDutyCycleHorizontalDrive
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3V3
Clk
Dig
BG
5V
SD2..0,CMSS XDT
XPR
Switch
Video SID Safety
sources Flash
VID FXTAL DFL HBL,WBF/R
Prot.
74 Calibrator >4V Blanking
YOUT SN2..0 FOA/B
67
Timing Horizontal
Noise VCO Slow Start
PHI1 :1600 PHI2 drive
detector HOSD & Stop
DC clamp
SYM POC
Hsync HP2 HSH, HP,
STB,SDC
73 separator STM Line oscillator 66 FlybackIN /
YSYNC LineHB,SDC
Phase “soft” lock
phi-1 loop SandCastleOUT
50% Coincidence SL SandCastle phi-2 loop
30% VA,VSH,SC,VLIN,VX,
detector Generator
V VSC,SBL,VSD
SSL IVW/F, OSD 22
Vertical Vertical drive
Philips Semiconductors
FSI 23
Selected Data CSO Geometry
Vsync Vertical Vertical Vertical
Video sync Geometry 32
separator Divider Sawtooth HCO EHT/XrayProt
sep. >3.9V
HTXT Auto70/35
FORF/S, DL, East-West
70% EW,PW, XPR
To TXT/CC NCIN,OSVE Geometry 21 EW drive
decoding L/UCP,TC
FSL
(AVL)
26 27
New: Better sync performance, due to clamp right before sync part.
The horizontal oscillator (PHI-1) uses the X-tal reference frequency to calibrate
it's free running frequency (roughly 25MHz). It has several time constants and
gating modes, including a “very slow” mode (stable OSD) when SID does not
identify valid CVBS.
By forcing phi-2 pin 17 above 4.0Volt, the HOUT is immediately stopped. Using
an external detection circuit this can be used for flash protection. When the
voltage drops < 4.0 volt, HOUT starts via the slow start procedure.
For non-EW versions, pin 21 connects the AVL capacitor (bit AVLE=1).
The R and C at pins 26 and 27 must have good temperature stability
To enable TXT/CC decoding from YPrPb input, set bit HTXT=1. In all other
cases the data comes via the CVBS-switch and HTXT should be set 0
GTV Function:
SID: ptun_GetIdents, ptun_GetVideoIdent
XPR: psys_GetXrayProtection
AVLE: psnd_SetAVLEnabledOnEastWestOutputPin
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SandCastle pulse:
DFL4..0
5.3V = Burst-Key
Sand-
Castle 3V = H-clamp
Philips Semiconductors
2.7V = DC detect
Active Pull down
at start-up 2V = Vertical
If you have colour detection problems, then check the timing of the H-flyback in
the SandCastle pulse. If the Burst-Key pulse is distorted, then also the timing
for the colour recognition may be affected.
RESTRICTED, contains NDA items
PHI-1 loop:
Philips Semiconductors
SID,SL= 0,0 detector
CVBSSW
Switch
No signal Very Slow CVBSINT
Switch
SID Video Y/CVBSEXT
Ident
• Use OSD-mode or POC=1 only when Slicer
CMSS SD2..0
video-sync-performance is irrelevant
(and SW must detect SL=1 to exit from OSD mode)
• If you use FOA,B=0,1 (Slow mode) ⇒ SW must select FOA,B=0,0 when IVW=0
(otherwise catching may be slow)
IF-AGC-gating:
When PHI-1 sync is synchronous to the tuner signal, active gating can improve
the signal stability. If a tuner CVBS signal goes via a “SCART-loop-through” (=
external input), set VDX,VDXEN=0,1 to active IF-AGC-gating.
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SD2..0=0,0,0 & CMSS=1 Couple SID to the main video & sync separator
Philips Semiconductors
Gives better OSD stability during noise-only,
Coupled circuits prevents PHI-1 from staying FAST @ no sync
• When sync fails (SL=0) then PHI-1 will try to re-acquire in fast-mode
• With VID=0, SID can automatically select slow-mode (gives more steady OSD)
With CMSS=1, the SID detection bit uses the main sync separator, which is
always coupled to the displayed picture (as selected by INA..D).
When SID has to judge a signal from another, non-selected source, then bit
CMSS=0 makes SID use another, independent sync separator circuit.
GTV Function:
CMSS: psys_SetVideoIdentSyncSelection
FO: psys_SetPhiOneLoopTimeConstant
VID: psys_SetVideoIdentificationActsOn
FO: psys_SetPhiOneLoopTimeConstant
SID: ptun_GetIdents, ptun_GetVideoIdent
SL: ptun_GetSyncIdent
VID: psys_SetVideoIdentificationActsOn
POC: psys_SetSynchronisationEnable
SD: psys_SetVideoIdentificationSource
IN: psys_SetSourceSwitch
VDX: psys_GetModeIFSyncInterface
VDXEN: psys_SetEnableVDX
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1x per second Once per second SID is used for other tasks
yes
Check: Sample presence of sync on all sources
Auto source switching Integrate the result over several samples
Philips Semiconductors
Loop forever
Every time when the source selection for SID is modified, or when it’s sync
separator (CMSS) is changing, please always allow some 10ms stabilisation
time before reading back SID.
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no
SL=0 ? If sync was already failing,
yes
then set PHI-1 slow during the sampling of SID
FOA,B= 0,1 slow OSD mode
CMSS=0, SD2..0 > 0,0,0 Test all available sources (SD2..0 ≠ 0,0,0)
Temporary: for SD2..0=001 (CVBS1) SID to Front-End + CMSS=0 temporary gives false sync indication
use LOCK instead of SID
Next SD2..0 Wait 10??ms Detection time of SID circuit + switch-over time
Read SID=1 ? Is sync available on that source ?
no
All tested ? Test all & do the switching after some integration
CMSS=1, SD2..0=000 Re-couple SID to PHI-1
Philips Semiconductors
Wait 10 ??ms Let it stabilise to avoid glitch
VID=0
Restore FOA,B Put PHI-1 back to your own preference
Coupled circuits
• No need for sense-contacts & signal detectors, fully under SW control
• For RGB(F) sources, check also IN2,IN3
If you want to “borrow” the SID bit for detecting sync on other input signals
(non-selected), then you will have to stop using SID as PHI-1 helper.
SW can quickly poll all available sources and then restore SID as PHI-1 helper.
Advice: Integrate the read-outs of SID for each external source over several
samples, e.g. continuously “1” during 1 second. This avoids too nervous
switch-over when e.g. a plug is connected or a VCR starts to play.
While you are polling other external sources, you can either:
- force PHI-1 always slow during this polling period (= simple)
- check the IF-lock bit IFPL & switch PHI-1 slow if it fails (= need SW)
- only force PHI-1 slow when SL=0 before you started polling (=advised),
and accept some OSD instability during a few ms.
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SCART1
SID (4): IF gating & recalibration
Tuner
De-Scrambler
FE
Philips Semiconductors
• IF-gating makes LOCK more reliable
• With [1] during external AV input the IF-PLL can loose lock too early at high modulation,
result = re-calibration of IF-PLL with visible distortion
• SW can improve this, during AV input:
– Disable auto-recalibration via IFLF=1, couple SID to tuner (SD2..0=0,0,1 CMSS=0)
– When SID also detects no tuner signal, then temporarily set IFLF=0 (= recalibrate)
When the De-Scrambler detects a signal that it can decode, it will activate the
“CVBS-Status” line. Now SW should react by switching to AV1 external input.
Front-End mode:
While the tuner signal is selected (INA..D=0,0,0,0) the IF-gating is keyed by
the sync circuitry, so SID is then freely available to do other functions. If the IF
gets out-of-lock AND there is no sync, then the IF-PLL will be recalibrated
(IFLF=0).
In AV modes: (not Decoder-On)
Now sync coupling is not possible (not synchronous to tuner signal), so then
the SID circuit can be used to decide about recalibration. While IFLF=1 it will
not recalibrate.
Remark:
In TV/VCR combi’s the Front-End can be kept active during TV-standby
(STB=1) by maintaining the +5V power supplies. In this special case the SID
detector is forced to Front-End (SD2..0=irrelevant, overruled by hardware), but
SW needs to set CMSS=0 (= use dedicated sync separator).
The SID detector can only work while +5V is available.
GTV Function:
IN: psys_SetSourceSwitch
VDX: psys_GetModeIFSyncInterface
VDXEN: psys_SetEnableVDX
IFLF: psys_SetCalibrationIFPLLDemodulator
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Philips Semiconductors
Restore IFLF IFLF=1 prevents IF from recalibrating
Background process Loop Mute/Demute as a background process
• Use SID →temporay: LOCK to mute tuner output signal on SCART1 if no sync
• When SD2..0=0,0,1 and IFLF=0 then SID=0 will recalibrate the IF
Video mute:
Do NOT mute the Front-End via VSW=1, as this will shut-down the whole IF
section and tuner-AGC. Consequently SID will never detect sync anymore.
-Front-End video output “IFVO” (pin 43,44) can be muted via IFO2..0.
- Selected video output “SVO” can be muted via SVO1..0=1,0 (??=1,1).
- CVBS-PIP video output can be muted via CS1A..D=0,0,0,0.
GTV Function:
IN: psys_SetSourceSwitch
SL: ptun_GetSyncIdent
SD: psys_SetVideoIdentificationSource
CMSS: psys_SetVideoIdentSyncSelection
IFLF: psys_SetCalibrationIFPLLDemodulator
SID: ptun_GetIdents, ptun_GetVideoIdent
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Temporary problem,
will be solved by trimming
the dedicated sync slicer
LOCK detection:
• SID has a tiny problem while CMSS=0 (dedicated sync slicer) but only when:
– A tuner signal without sync is received (Front-End no signal), gives high noise amplitude
– AND an other source is viewed
• Unwanted effect: SID keeps telling there is sync, while there’s only noise
• Temporary solution: use LOCK instead, but only in this case (FE while AV selected)
Philips Semiconductors
– When AV is viewed (Back-End synchronised to other source) & VIF input signals are
modulated > 85% (white picture), then LOCK toggles between lock/no-lock,
while there’s still signal
• Solution: read LOCK several times and integrate via SW
– E.g read 4 times with > 20ms interval; then integrate: ≥1 out of 4 = OK
GTV Function:
CMSS: psys_SetVideoIdentSyncSelection
SID: ptun_GetIdents, ptun_GetVideoIdent
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PHILIPS
PHI-2 corrections (HP, HB, HSH) not
active on OSD
Philips Semiconductors
TEXT PHI-2 corrections (HP, HB, HSH) also
active on OSD
PHILIPS
PHILIPS Slightly less stable OSD with noise
& VCR trick modes
When using the parallelogram and bow correction the horizontal reference of
the OSD must be connected to the PHI-1 to obtain the same geometry
correction for incoming signal and OSD (HP2 = 0).
When these corrections are not needed, the setmaker is free in his choice
Note when the horizontal reference is taken from the PHI-2, (HP2 = 0) the
horizontal position of the OSD is not changed when shifting the video with
HSH.
GTV Function:
HP2: psys_SetSyncForTextOSD
HB: pimg_SetHorizontalBow (BOW)
HSH: pimg_SetHorizontalShift (HS)
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70% 35%
70%
60%
100%
100% >350mV
Top
TopSync
Sync
175mV
Philips Semiconductors
• FSL=1 forces 60% (use for non-standard signals with distorted black level)
• Similar bit for Horizontal: SSL (SSL=1: 30%, SSL=0: 50%)
With negative modulation, the sync pulses have the largest amplitude of the IF
signal. When there is noise, it is best to slice near the top of the pulse, at 60%.
For strong signals (no noise) we slice at 35%. This improves behavior with
signals that have compressed sync, only during vertical interval.
In areas where this is not needed, the sync performance can be made more
immune to disturbances by fixing the level to 60% via bit FSL=1 (e.g. coded
signals with variable black level during vertical or some cheap DVD players).
When the sync amplitude becomes extremely large (> 350mV), the slicing is
done at a fixed level of 175mV below top sync (end of proportional AGC range)
Philips Semiconductors
• Divider system + DC vertical amplifier gives:
- Fast settling (speed-up with NCIN=1 : keeps vertical forced into Acquisition Mode)
- Minimal visibility of (short) sync interruption
• Automatic Comb-filter = OFF in “Acquisition Mode”
Philips Semiconductors
OVSE Enable Vertical OverScan 1: enabled I Sync SC
(RGB measurment lines)
HTXT Href for TeleteXT from own 0: dedicated sync slicer I Sync SC 0= normal, 1=
dedicated TXT sync slicer 1: from main sync circuit TXT/CC via YPRPB
MVK (anti) MacroVision Keying 1: active I Sync SC Active only during
NORM mode
For enhanced stability of On Screen Display e.g. during search-tuning, the phi-
1 loop can automatically be switched slow by SID (=Signal-Ident = simple
16kHz detector). Set bit VID=1 to enable this.
With POC=1, the phi-1 is set to free-run mode (X-tal locked). In this mode bit
SL can not be used to detect line-sync-lock.
GTV Function:
NCIN: ptun_SetVerticalDividerMode
SL: ptun_GetSyncIdent
IVW: ptun_GetStandardVideo
FOR: psys_SetForcedFieldFrequency
SSL: psys_SetSlicingLevelSyncSeparator
FO: psys_SetPhiOneLoopTimeConstant
POC: psys_SetSynchronisationEnable
VID: psys_SetVideoIdentificationActsOn
FSL: psys_SetVerticalSyncSlicingLevel
OVSE:
HTXT: psys_SetCsoSourceForTxt
MVK: psys_SetMacroVisionKeyingEnabled
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Philips Semiconductors
BITS FUNCTION STEPS RANGE MACRO FU REM
HB Horizontal Bow 63 -1.. +1 us Sync AL
HP Horizontal Parallelogram 63 -0.75.. +0.75 us Sync AL
HSH Horizontal SHift 63 -2.. +2 us Sync AL
WBF Wide Blanking Front 15 3.5 .. 5.9 us Sync SC
WBR Wide Blanking Rear 15 7.8 .. 10.2 us Sync SC
For the “real-flat” picture tubes the IC offers controls for Horizontal-Bow and -
Parallelogram (HB and HP). These controls are internally made as dynamic
offsets between phi-1 and phi-2 loops.
Philips Semiconductors
AVG Adjustment VG2 voltage 0: normal operation I Geo AL
1: enable measurement
FBC Fixed BeamCurrent switchoff 0: Blanked RGB outputs I Geo SC
1: Fixed beam current
EVB Extended Vertical Blanking 1: active I Geo SC
To minimise visibility, the discharge of the picture tube during slow stop can be
done in vertical overscan by setting bit OSO=1.
To help Vg2 alignment, the vertical deflection can be disabled via VSD=1 (one
horizontal line on the screen). With AVG=1 the beam current can be read out
via HBC and WBC, to align the “VG2-voltage (see section “RGB processing”).
This even makes automatic alignment of VG2 (“screen”) possible.
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Philips Semiconductors
VL0..1 Vertical Linearity 00 Full screen Geo AL
01 Lower vert lin
10 Upper vert lin
VLIN Vertical Linearity 63 85 .. 117 % Geo AL VL0/1=00
Geometry Zoom:
SubTitle
16:9 tube, + Vertical Scroll
picture 4:3
side bars SubTitle SubTitle SubTitle
SubTitle
Horizontal + Vertical
Expand Zoom SubTitle
SubTitle
+ Vertical Slope :
16:9 tube,
Move up bottom,
picture 16:9 top remains
Philips Semiconductors
sub title in
black bar SubTitle SubTitle SubTitle
SubTitle SubTitle
On a 4:3 picture tube the vertical zoom function can be used to compress a
“full-screen” 16:9 picture back to normal aspect ratio.
On a 16:9 picture tube, a 4:3 picture can be displayed with black, vertical side
bars. To make the picture “fill” the screen again, we can use H + V expand. If
sub titles needs to be lifted, the Vertical Slope (VS) or Scroll (VSC) can be
used. VS will keep the top of the screen constant, but modify the aspect ratio.
VSC will move the whole picture and keep aspect ratio constant.
GTV Function:
VS: pimg_SetVerticalSlope (VSL)
VSC: pimg_SetVerticalScroll
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Wide blanking:
Outside visible
picture, in overscan
WBF WBR
Philips Semiconductors
LEFT: Wide-Blanking Front (bits WBF)
RIGHT: Wide-Blanking Rear (bits WBR)
On /off = bit HBL (Horizontal Blanking)
Wider range = bit WBI (6.24µs shift to center, use for
digital 4:3 compression on 16:9 CRT)
When a 4:3 picture is displayed on a 16:9 tube, the East/West modulation can
be used to compress the picture to normal aspect ratio. But the edges of the
video, that are normally in the overscan, will then become visible. This can be
adjusted with Wide Blanking front and rear.
In case the CVBS timing is not symmetrical, both Front and Rear edge
blanking can be adapted individually.
GTV Function:
WBF: pimg_SetWideBlankingStart
WBR: pimg_SetWideBlankingEnd
HBL: pimg_GetWiderHorizontalBlanking
WBI: psys_SetTimingWideBlanking
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Colour decoding:
Philips Semiconductors
In/Out
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Colour Decoder:
Philips Semiconductors
• Automatic COMB filter for PAL-M/N/BG and NTSC-M
– Enabled by CFA=0, permanently off when CFA=1
– Automatically switches off when:
• No proper colour-system detected
• No vertical in-lock (IVWF=0, or while NCIN=0)
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Philips Semiconductors
mode IDS H/2 SBO1..0
B-Y
R-Y BPS
SECAM 1H
CLO Cloche VCO
15
For NTSC signals, the U+V baseband delay line can be bypassed or can be
used as simple kind of comb filter. When the real comb filter is ON and NTSC
is decoded, please set BPS=1 (=bypass) for optimal effect.
The base-band delay between Y and U&V (e.g. caused by different group-
delay in SAW filter) is aligned by the luminance-delay bits YD3..0.
Too large
colour
carrier
Philips Semiconductors
Too small
colour
carrier
A video signal (CVBS) is fed through a chroma band pass filter, to separate the
burst and colour carrier from the Black & White part.
The Automatic Colour Control circuit measures the chroma amplitude during
the burst-key pulse (generated by synchronization part). It then tries to make
this amplitude equal to the nominal value.
Since chroma amplitude and burst amplitude have a fixed relationship in the
video standards, the colour carrier will be stabilized to its nominal value too.
Philips Semiconductors
• Too high chroma carrier level = over saturation
• ACL=1 reduces during scan, burst unaffected
When the ratio between burst amplitude and chroma level is wrong, severe
over-saturation can occur.
The Automatic Colour Limiter will reduce undesired over saturation, caused by
too high chroma/burst-ratio. It reduces the too high chroma carrier level to a
maximum allowed level.
The ACL adapts the chroma gain only during scan, so that the burst amplitude
remains unaffected (maintain good chroma sensitivity).
Note:
Please disable the ACL circuit during SECAM reception (FM-modulated
chroma) by setting I2C-bus bit ACL=0. In most other cases the ACL can best
be left “on” (ACL=1).
GTV Function:
ACL: pimg_SetAutomaticColourLimiting
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+
SAW filter roll-off
PC CC
=
A-symmetrical
Ideal chroma spectrum
Band-pass-filtered
chroma
chroma
spectrum
spectrum
Philips Semiconductors
Setting bit CB=1 gives 10% shift:
When a SAW filter has too much roll-off for high chroma frequencies, this can
be compensated by setting tool-kit bit CB=1 or CLO=1 for SECAM. This shifts
only the chroma bandpass (not the calibration).
The AM-modulated PAL and NTSC chroma systems are less affected by SAW
filter roll-off, but under specific field conditions the “tool-kit” bit CB can help to
improve weak-signal ident-performance
Use CB=1 or CLO=1 only if necessary because it does affect the chroma
spectrum.
GTV Function:
CLO: psys_SetCentreFrequencyClocheFilter
CB: pimg_SetChromaBpCentreFrequency
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Philips Semiconductors
function
CFA C o m b Filter Action 0: 4H-PAL/2H-NTSC I Filt/Sw SC
1: off
FCO Forced Colour O n 1: no colour killing I ColDec TK
COMB C O M B filter active 0: Not active O ColDec SC
YCD Y/C D etector, higher chroma 0: CVBS detected O ColDec S C Works only once, directly after
burst on ”C” than on “Y/CVBS” 1: Y/C signal detected a source change
Pin 33 (RefIn/Out…) can have different functions, which can be selected by the
bits CMB2..0.
With FCO=1 the colour killing function can be disabled (only when one single
colour system is forced). This enables colour under non- standard condition,
e.g. trick play in TV-VCR combinations.
Philips Semiconductors
1100 PAL/NTSC Full Auto Fb,c,d Tri-norma 1000 “PAL?” Fd
1101 PAL/NTSC Auto Fd 1010 SECAM
1110 PAL Forced Fd
1111 NTSC Forced Fd NTSC-M
The CD info is derived from the information of the three different demodulators,
plus the locked frequency of the digitally controlled chroma oscillator.
Normally there is no coupling to the vertical frequency, so even “non-standard”
(VCR) signals like e.g. “PAL-443 at 60Hz with DK-sound” can be recognised.
Except “SECAM-60Hz” can not be decoded in AUTO-mode.
Handling non-standards:
Philips Semiconductors
(always wait until next Vertical Blanking Interval (= VBI-interrupt EBUSY), before it is effective)
GTV Function:
fmst_SetColour / Sound / System
fmst_GetColour / Sound / System
fmst_GetDetectedColour / Sound / System
fmst_IsColourNTSC / PAL / SECAM
fmst_IsColour / Sound / SystemDetectionBusy
SL: ptun_GetSyncIdent
PSNS:
CM: pimg_SetColourDecodingDirect
FSI: psys_GetFieldFrequency
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Loop 3x
Wait 2xVBI 2 x 20ms per chroma frequency
60Hz yes
Standard OK ? PAL-M, PAL-N or NTSC-M
Select BG-SAW no
All 3 tested ? Test FSI before switching SAW
Set CM=Auto at freq. Fa yes = 50Hz
FSI=0 ?
Low sensitivity, wait 2xVBI
no Select BG-SAW
Allow PAL-60 ? “China”-option
Set CM=Auto at freq. Fa
PSNS=1, wait 1xVBI
yes
Wait 2xVBI
PAL detected ? PAL-60 yes
Standard OK ? PAL-443,
Philips Semiconductors
NTSC detected
yes
NTSC-443 SECAM-50 or
Not found, try again
NTSC-50
High sensitivity, wait 1xVBI
yes PAL-60 or
Standard OK ?
NTSC-443 or • If not found, retry a few times
Not found, try again SECAM-60
Philips Semiconductors
In/Out
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YUV processing:
Philips Semiconductors
• Peaking, Coring, Black \ Blue \ White-stretch,
Transfer-Ratio and Scavem (also on TXT)
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Signal routing:
Calibrator
Y IN3 77 Fbl3
Fa=4.433619 MHz FXTAL Scavem
PR
Fb=3.582056 MHz TXT Delay Scavem
PB 65 Svm
Fc=3.575611 MHz processing
Fd=3.579545 MHz Delay
BKS,BSD,
CVBS & Y/C Switch
Matrix
Peaking,coring
Bluestretch
TNTSC
CVBS/Y5 72
Switch
Switch
Comb U G
UV offset
Tint
C3 55 GINT
C4 59 PAL +
Philips Semiconductors
C5 70 SECAM
V B BINT
NTSC
33 +4.5V CD2..0 HUENTSC IE2, PK, TINT, DSK SAT MUS,MAT CON
IE3 COR TUV Halftone Ins
Alternative OUV, OFB,
function BLOG,BLOR OSD RGB
CMB0/1
MMR: 87F7H
• During DVD/YUV input colour detection is impossible; SW must select the correct RGB-matrix
(NTSC-matrix when FSI=1 (60Hz) : CM3..0=1,1,1,1 & MAT=0 or PAL-matrix when FSI=0 (50Hz) : MAT=1)
Philips Semiconductors
PF1,0 Peaking Freq Delay Used for REM
00 2.7 MHz 190 ns NTSC-M/N, PAL-M/N 3.6 MHz Chroma
01 3.1 MHz 160 ns Alternative for 00 Set makers choice
10 3.5 MHz 143 ns PAL-BG, SECAM, NTSC-443 4.4 MHz Chroma
11 4.0 MHz 125 ns External RGB/DVD No Chroma encoding
GTV Function:
YD: pimg_SetLuminanceDelayTime
HCT: psys_SetHighContrastOSD
SYS: psys_SetYUVSynchronisationInputMode
FSI: psys_GetFieldFrequency
CM: pimg_SetColourDecodingDirect
MAT: pimg_SetColourMatrixAdaption
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SVM output
SVM2..0 SMD0 CRA0 Hor.
position
Position-
dependent
gain adapt 10 50 IRE Yin 100
left right
Philips Semiconductors
• High VM-gain for grey signals up to 50IRE; less gain for larger signals
• Selectable delay between VMOUT and RGBOUT (max. Video: -210ns, OSD: -300ns)
Scan Velocity Modulation improves the horizontal spot quality of a picture tube,
by temporary changing the scan speed of the electron beam. Near left&right
edges we need more SVM than in the center, especially for real flat CRT tubes
GTV Function:
CRA0: pimg_SetCoringOnScavem
SVMA: psys_SetScavemOutputSignal
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=0
Yout
S
BK
20 Stretch
10
0
BSD=0
BSD=1
-10
Philips Semiconductors
-20
10 20 Yin 50 IRE
• I2C bit BSD sets black stretch depth to -10 or -20 IRE (above 50 IRE no stretch)
GTV Function:
BSD: pimg_SetBlackStretchDepth
BKS: pimg_SetBlackStretchMode
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90%
0
S=
AA
1
S=
10%
AA
Test method : black pluge on a
grey background
active area
Philips Semiconductors
• 1: Determine dynamic black-stretch-reference level (in window)
• 2: In window, measure sum of area’s where video is below that reference
• 3: If more than 10% area (relative to full screen) is below the reference,
then switch black stretcher off (or 20% when AAS=1)
The easiest way to check the black stretcher, is with a gray background (below
50 IRE, otherwise no stretching at all). Then apply a black section, a bit less
than 10% of the viewing area. If you increase the section above 10%, the black
stretcher will switch off smoothly (no discontinuities).
So when there is enough black in the video, stretching stops.
GTV Function:
AAS: pimg_SetBlackStretchArea
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max. 18%
18% White Stretch
WS
WS
1,0
12%
1,0
=1,1
WS
=1,
10%
1,0
Yout
=0
,1
Philips Semiconductors
• GAM=0: White-Stretching dependent on average detector (= APL)
Bits WS1/0 determine:
- the Average Picture Level (APL) where the white stretching begins
- maximum achievable stretch (at 50 IRE)
• GAM=1: fixed non-linear luminance transfer (gamma)
Bits WS1/0 select one of 4 characteristics
GTV Function:
GAM: pimg_SetGammaControl
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TFR=0
4
TF
R
=1
⇓
2 TFR=1
0 TFR=0
Philips Semiconductors
• Transfer Ratio = dynamic brightness reduction, changing linearly with the
Average Picture Level (APL)
• No video-dependent shift when bit TFR = 0
• Eco-Histogram = combined Black&White-Stretch plus Transfer-Ratio
GTV Function:
TFR: psys_SetLuminanceDCTransferRatio
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Blue Stretch:
R,G,B gain
20
0
20 Yin 80 IRE
Philips Semiconductors
• No effect on lower-intensity parts (e.g. skin tones)
• Blue Stretch switched off when bit BLS=0
• NRR=1 : no RED reduction during Blue Stretch (taste dependent)
GTV Function:
BLS: pimg_SetBlueStretch
NRR: psys_SetNoRedReduction
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Philips Semiconductors
In/Out
The Cut-Off control circuit with “Continuous Cathode Calibration” stabilizes the
picture tube alignment during age-ing of the TV set.
Not only a White Point adjustment, but also a Black level offset adjustment is
now provided. This enables independent colour temperature setting for Low-
and High- light. With this new feature even (cheap) picture tubes with non-
standard gamma characteristics can be used.
White Point registers: WPR, WPG & WPB for Red, Green & Blue.
Black Level Offset registers: BLOG & BLOR = offsets on Green and Red
(Blue instead of Red if OFB=1).
The contrast of the OSD can be set via the RGBOSD control in a µProcessor
MMR register. The Contrast setting has no effect on the OSD, but
BeamCurrent limiter and PeakWhite limiter do (see next slide).
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Philips Semiconductors
• Hide visibility of gain adaptation (e.g. SW adapts gain during channel-change)
CCC-loop:
ICATHODE
150µA
Philips Semiconductors
10µA
130V 60V
VCATHODE
OUV
RGB output control:
Philips Semiconductors
PGR/G/B PTW Discharge
Peak White Limiter
10µA
OSO,FBC
CBS,PWL,SOC SLG1,0
Leakage
220µA
Compensator
190
280
150
A fast Peak White Limiter (PWL) and a slow Beam Current Limiter (BCL) can
reduce contrast and brightness to avoid over-drive of the picture tube
(prevent: geo-distortion, local doming, de-focusing).
The Continuous Cathode Calibration loop (CCC, AKB= Auto Kine Bias)
consists of a DC-offset correction (black current) and a gain correction loop.
For good performance, the RGB amplifiers must be able to handle positive and
negative leakage currents. This is included in all Philips Semiconductors RGB
amplifiers with a current measurement output (e.g. TDA6107A/08A). The gain
control loop annihilates gain differences between R,G and B channels (due to
age-ing, component tolerances etc.)
Before adapting the RGB drive, the IC will measure and compensate the
leakage currents (normally 2..10µA). The IC can handle +/- 75µA.
The black current input is also used to set 1 mA discharge current during
controlled shut-down of HOUT (if bit OSO=1), and to measure the beam current
during Vg2 alignment (VSD=1).
During blanking (RBL=1) the outputs are driven 1.1V below black level.
GTV Function:
EGL: pimg_SetEnableGainLoopCCC
LPG: pimg_SetRGBGainPresetLoad
OSO: psys_SetVerticalScanAtSwitchOff
VSD: psys_SetVerticalScanDisable
RBL: pimg_SetRGBBlanking
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Philips Semiconductors
gain-measuring line causes a current larger than the current selected
(SLG1..0 :150, 190, 220 or 280µA)
• Set EGL back to 0 (makes PTW indication invalid)
• After loading desired preset gains, toggle LPG=1→0
Before the cathodes of the CRT-picture tube are warm enough, it is not
possible to display any picture/OSD. The heating-up takes several seconds
and determines most of the “TV-cold-start-time”.
Using the PTW bit, your software can read back exactly when the CRT can
start to display = automatic adaptation of start-up time.
GTV Function:
PTW: psys_GetIndicationPictureTubeWarm
EGL: pimg_SetEnableGainLoopCCC
LPG: pimg_SetRGBGainPresetLoad
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Init: STB,RGBL,RBL=1;AKB,EGL=0
Set: gain current SLG to last value
Start up CCC loop:
Philips Semiconductors
Increment: BCF_OK_Cntr+1
no Continuously stable during 400ms
BCF_OK_Cntr=20?
Set: EGL=0 Freeze the gain loop = best stability
Set: gain preset PGx=last value
Switch back to stored optimal value
Clock-in presets, toggle: LPG=1→0
Set: RBL=0
It is not mandatory to postpone OSD display until BCF=1, but severe OSD
discoloration may occur. Suggestion: use “rainbow” OSD colours for start-up,
this also helps to speed-up the stabilisation of the CCC loop.
For CCC-loop-start-up, we advice to check for a continuous period of 400ms
where BCF=1, before releasing the blanking (RBL=0). But if for any reason
this would take more than 10s, simply let go and un-blank the screen.
Note: To enable the mechanism for PTW, the gain-loop must be active
(EGL=1) but the CCC-loop counters must be kept frozen (LPG=1).
The check for PTW+BCF uses only the RED channel, so SW only needs to
add the ∆ in the RED preset PGR.
Philips Semiconductors
– After TV-production ⇒ “Virgin-mode” (e.g. first 10 times switch-on)
– After Servicing (calibrate) ⇒ re-enable “Virgin-mode” (replacing IC or CRT)
Normally the GAIN hardly changes in a TV, only a little bit due age-ing of
components. An Automatic loop sometimes over-reacts on glitches, that is why
we now make it possible to integrate over a longer period. SoftWare now has
full control how fast/slow corrections are done.
In Factory mode you can leave the CCC-loop ON during a burn-in period. If
the CCC-loop has reached its stable end-value (GLOK=1) within about 1
second, the TV chassis is OK, else it could be redirected to a repair stage.
Hint:
If something was damaged in the TV set, also the SW-integration may end-up
at max. or min. values of PGR/G/B. This could be used as a trigger to enter
“Protection-mode” → blink an error LED and switch power off.
GTV Function:
GLOK: pimg_GetIndicationCCCGainLoop
PGR: pimg_SetPresetGainRed
PGG: pimg_SetPresetGainGreen
PGB: pimg_SetPresetGainBlue
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Philips Semiconductors
Store PGx in Eeprom
Do not measure/adapt the gain settings while the TV is cold (e.g. 15 minutes).
The three CCC-gain-loop counters do one INC/DEC per 40ms, so if you start
at 50% of 128 (7bits) it can take 64x40ms=2.56s to reach min/max PGx value.
We advice to limit the sample-time < 350ms, otherwise channel-switching
becomes too slow.
During some “invisible” periods, the Software can measure the correctness of
the gain settings. We advice to do this:
- during (black) channel switch-over
- when switching the TV into standby
We temporarily enable the gain loop; after taking an “RGB-sample” we will go
back to the previous gain setting. Integrate the “samples” over a longer period,
to cancel out spikes/noise etc.
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ICATHODE
BLOG
Philips Semiconductors
BLOR
VCATHODE
Low-light color temperature adjustment:
BLOG on Green, BLOR on Red (or on Blue when OFB=1)
GTV Function:
WPR: pimg_SetWhitePointRed
WPG: pimg_SetWhitePointGreen
WPB: pimg_SetWhitePointBlue
BLOG: pimg_SetBlackLevelOffsetGreen
BLOR: pimg_SetBlackLevelOffsetRedOFB:
psys_SetBlackLevelOffsetBlue
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Vertical compression
CCC-measurement
lines become visible
OSVE=0
on the screen
OSVE=1
Philips Semiconductors
vertical over-scan
Note: check compatibility with your vertical deflection amplifier !
GTV Function:
OVSE: dsys_SetBlackCurrentMeasuringLinesInOverscan
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CVBS/Y
< 2µs 2 µs
Philips Semiconductors
Spike shorter than 2 µs : Only Soft Clipping active
Peak longer than 2 µs : White Limiter also becomes active
The soft clipper is intended to clip high frequency peaks if the video signal. Its
attack level can be selected 0, 5 or 10% above the selected PWL level, via bits
SOC1,0.
GTV Function:
PWL: psys_SetPeakWhiteLimitingControl
SOC: psys_SetSoftClippingLevel
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DAC DAC
Decrease capacitor voltage:
- CONTRAST reduction
< <
- BRIGHTNESS reduction
EXTERNAL
BCL pin PWL
Beam
White level
Philips Semiconductors
Current 2 1 2µs
detector
Info
Philips Semiconductors
CM3..0=1,1,1,1
MUS NTSC Matrix USA 0 : Japanese NTSC I RGB SC “0” often preferred
1 : USA NTSC matrix also for USA
CLD CLamp Delay 1: 400ns compensation I RGB SC When YUV-loop
feature needs this
LLB Low Level Beamcurrent 1: enable 0.5mA pull- I RGB SC
down on BCL pin
HCT High Contrast selection for OSD/TXT 1: 3dB more I RGB SC
The CCC-loop can be switched off for LCD applications by setting AKB=1.
The beam current during Vg2 alignment can be monitored using HBC and
WBC (under / above window, in window).
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Philips Semiconductors
11: 18%, APL=28%
SOC1..0 SOft Clipping level 00: PWL level I RGB SC
01: 5% above PWL
10: 10% above PWL
11: soft clipping off
YUV1..0 YUV/RGB input selection I RGB SU
OUV Offset UV or Red & Green 1: UV colour offset I RGB SC
0: RG(B) low-light offset
The RGB outputs can be blanked using RBL. Also black switch-off is possible
(when the picture tube is discharged, using a bleeder).
When the CCC loop has not yet stabilised, e.g. during switch-on, the RGB
outputs can temporarily be forced to a fixed DC level via RGBL=1.
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Philips Semiconductors
OFB BLOR OFfset active on 0: on Red I RGB SC Depends on alignment method
Blue or Red channel
OUV Offset UV or Red & Green 1: UV colour offset I RGB SC Depends on alignment method
0: RG(B) low-light offset BLOR/G range –50..+50mV
EGL Enable Gain Loop in CCC 1: loop active I RGB SC
system
SLG Select Loop current Gain 00: 220uA I RGB SC
01: 150uA
10: 280uA
11: 190uA
GTV Function:
HBC: dsys_GetBlackCurrentLevel
WBC: psys_GetBlackCurrentWindow
BLOR: pimg_SetBlackLevelOffsetRed
BLOG: pimg_SetBlackLevelOffsetGreen
AVG: psys_SetVG2AdjustmentMode
VSD: psys_SetVerticalScanDisable
AKB: psys_SetBlackCurrentStabilisation
WPB: pimg_SetWhitePointBlue
WPG: pimg_SetWhitePointGreen
WPR: pimg_SetWhitePointRed
CL: psys_SetCathodeDriveLevel
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Philips Semiconductors
(Using Brightness-DAC for DC offset, levels out system tolerances)
VCATHODE [Volt]
160
Choose high Cut-off = allow more range
860 to increase drive while VG2 is lowered
130
due to Beam Current load
540 690 VG2 [Volt]
The brightness DAC can select the proper DC cathode-cut-off voltage for your
picture tube (=BRIVSD while VSD=1). Via this DC you can find the optimal
position for the VG2 potentiometer.
Maintaining this VG2 we now adapt BRIAVG (AVG=1) to find the “15µA-IBEAM”
point via I2C-read-back bits HBC,WBC. For a given combination of tube &
amplifiers & FBT/LOT, this BRIAVG value should be determined ONCE.
Now the VG2 alignment can be automated, using HBC,WBC=1,1 (=15µA) as
a reference.
The Cut-Off voltage is a function of VG2. Under working conditions, the Beam
Current load will lower EHT & VG2 voltage. The CCC loop must increase the
drive voltage to compensate for this. We advice to choose a high Cut-off
voltage, allowing more room for the CCC loop to compensate.
Spec TDA6108A:
3V
190VOUT at 1VIN
- DC-range for the CCC-loop
VIN = VRGB,OUT
Ga
RGBOUT = 1.65V +/- 0.85V in =
2.3V 80x
1.65V
1V
86V 138V 190V
VOUT,CATHODE
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Philips Semiconductors
Decrease VG2
20µA “Black” DC level
HBC,WBC=1,0
WBC=1 determined
VG2 is OK by BRIAVG
HBC=0 12µA and VG2
PHILIPS
Increase VG2
Keep OSD position below measurement bar
After VG2 alignment, set AVG=0 and Brightness to nominal position. Then
align the white-point via the WPR,G,B registers.
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Philips Semiconductors
6. Align WPR/G/B (after VG2 alignment)
LCD-mode (1):
Philips Semiconductors
– SandCastle-pulse, via simple slicing circuit
– Pins HOUT and VSCAP
Pin HOUT does not change function since it would be disastrous for CRT-
deflection, if it ever modified the timing accidentally.
For safety also pin FBISO can only change function during standby.
So toggling bit CSY only has effect while STB=0.
The “composite H+V” output on pin FBISO uses the PHI-1 as horizontal
reference pulse (sync-acquisition PLL). During sync-loss or noisy video signal,
this reference may take fast phase jumps. If an LCD scaler has problems with
this, SW can set FOA/FOB=1,0 bits to damp the PHI-1 loop (= very slow).
GTV Function:
CSY: psys_SetConditionFlybackInputPin
STB: psys_SetTVProcessorStandby
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LCD-mode (2):
Philips Semiconductors
(vertical, HBL,WBF,WBR, see Notes Page below)
When the black-current CCC-loop is switched off (AKB=1), the black level is
determined inside the IC (fixed 1.65V). At nominal BRIghtness, the blanking
level is 0.3V below this black. You can adapt this difference by increasing BRI,
since the horizontal blanking level is NOT influenced by BRI.
Note:
With AKB=1, some black level offset may appear between R,G and BOUT, that
can be slightly temperature-dependent. The artificial blanking functions are still
active, but they will act differently from normal CRT operation (loop on):
- the video is no longer suppressed
- the brightness DC-adding is suppressed (= normal during blanking)
- the signal is not pulled below black anymore
You can use BRIghtness to make the video “black” equal to the blanking level
(blanking level does NOT change with brightness control).
With AKB=0 (loop on), the black level is determined by the application (pin 84:
BlkIn) so internal offsets & temperature effects are eliminated. With a dummy
circuit any black level can then be made and all artificial blanking functions will
behave normal.
GTV Function:
DSS: psys_SetSlowStartUpMode (SSD)
AKB: psys_SetBlackCurrentStabilisation
DFL: psys_SetFlashProtection
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YsyncIN
• TDA9178 needs SandCastle pulse YOUT +8V
TDA9178
U,VOUT
for its H & V measurement windows Y,U,VIN
I2C
(Falling-edge of blanking pulse must be after edge of Burst Key) SandCastle
10k
HOUT H shaper HSYNC
V slicer VSYNC
+5V
74HCT04 R2
10k
39k
HOUT R1 C2 HSYNC
C1
4k7
H H-flyback pulse as
1n2 680p
in CRT-application
10k
10k
Philips Semiconductors
SandCastle 200µA 4k7
HOUT
47k 4k7
NPN Delay= Duration=
10k
res
HSYNC R1*C1 R2*C2
VSYNC
TDA9178
SandCastle
V
Micro controller:
Philips Semiconductors
In/Out
Text/Control/Graphics µ-Controller:
FLASH
System 12 x 9/10 SCAVTXT
Programming 12 x 13 Display
Power 2MHz Hs-I2C Matrix 12 x 16 Generator R,G,BOSD
On 16 x 18
Reset FblOSD
Composite 50/60Hz
Sync Timing SFR Contrast
Supply CC Reduction
Input Data
guards Data
CVBS Capture Decoder TXT Memory Interface
RAM
YUV-Processing
Double Window
& Panorama
Main RAM PK26 Display RAM
FLASH
Watch 256 Bytes ROM 4K 10K (10pages)
Dog 80c51 Program
Aux RAM
Philips Semiconductors
24.576 CPU ROM 128K SSD TV
MHz 4KBytes
Xtal 6-cycle
DCXO 12.288 MHz
:2 UART I/O I2C
Oscillator
SFR extensions
Timers+Counters RDS TPWM D/A ADC
To Analogue part Remote Cntrl Proc RBDS
Abbreviations:
PK26 = packet 26, a TXT extension to transmit more than 127 characters
UART = Universal Asynchronous Receiver Transmitter
RDS = Radio Data System
Fbl = Fast-blank insertion of characters over video (also called InSw or VDS)
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Philips Semiconductors
• Data Capture, TXT, CC, RDS, RBDS
• Display, Double-Window
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Philips Semiconductors
• Address Spaces: 8-Bit ‘MOV’ and 16-Bit ‘MOVX’
• UART (asynchronous serial transceiver)
The most frequently used instructions require only 1 byte ROM and 488ns
execution time (at 24.576MHz Xtal = 12.288 MHz internal clock).
The 8-bit MOV instruction is more code efficient, but has limited working range.
The 16-bit MOVX instruction can access the full 64K RAM space within one
instruction.
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Philips Semiconductors
OSD & data aquisition off off off
RAM contents maintained maintained Some are lost
Exit from power saving SW resets bit Interrupt clears Interrupt clears
mode via: STANDBY in bit IDL in SFR bit PD in SFR
SFR ROMBK PCON PCON
Optimal power efficiency for the TV’s standby mode is achieved if software
puts the micro first into STANDBY and then in IDLE / POWER-DOWN.
(bit STANDBY in SFR ROMBK and IDL,WLE in SFR PCON)
The watchdog timer should be disabled, before entering a sleep mode (reset
bit WLE in SFR PCON).
80c51 Interrupts:
Philips Semiconductors
- ES2 33H I2C transmit/receive
- EBUSY 3BH V-blanking period BUSY (config H/V via MMR 87FFH)
- ET2PR 43H 16-bit Timer 2 with 8-bit PRescaler
- EUART 4BH UART transmit/receive
- ERDS 53H RD(B)S data available
- EX2 5BH INTerrupt 2
Software can give each interrupt source its own priority level. Processes that
require very accurate timing can be given higher priority.
Safety interrupt EDET signals conditions that can harm the silicon. Status can
be read via bits: 1V8GUARD, 3V3GUARD, TEMP130 & TEMP140. Interrupt is
cleared by writing bits to zero (=different from other interrupts).
A voltage of > 2.1V at the 1.8V inputs drastically shortens lifetime. This error
condition can be read from the VSP via I2C-bus bit SUPR.
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Timer/Counters:
Philips Semiconductors
• Timer2 (16 bit) with (8 bit) Pre-scaler (has automatic reload) :
– Interval = [TP2H * 256 + TP2L] * [TP2PR +1] * 0.4883us
Watchdog Timer:
Philips Semiconductors
Advice: disable the Watchdog during
– IDLE or POWERDOWN mode
– ISP (otherwise: risk of incomplete programmed samples)
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Philips Semiconductors
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Philips Semiconductors
R1
00H 08..0FH Register-Bank1 R0
00..07H Register-Bank0
The RAM between 30H and FFH is not allocated for any special area or
functions . The Program Status Word is accessible as an SFR PSW , located
at address D0H.
Direct :
MOV direct,A Move Accu to direct byte 2 6
ANL direct,#data AND immediate data to direct byte 3 12
MOV direct,direct Move direct byte to direct byte 3 12
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Philips Semiconductors
– Display : read & convert to RGB 74FFH
RD(B)S Data 1.25K
7000H
6FFFH
• Auxiliary RAM (except Display RAM) is Display RAM
TXT/CC/RDS/RDBS
20K
2000H
– Not initialised at Power-On-Reset 1FFFH
Auxilary RAM 4/8K
0000H
– Maintained in Power Saving modes
All Xdata – except the Display-RAM – can be used to maintain data during
standby-mode of the TV (even when a short reset occurs). Please note that
this Xdata is NOT cleared, so software must do that after reset.
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Display RAM:
Philips Semiconductors
• Teletext page area = 10K
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Philips Semiconductors
- a NEW page header is acquired
- the erase bit C4 is set
Embedded Flash-ROM:
Philips Semiconductors
• Programmable ROM:
- industrially via Parallel programming (14 pins needed)
- via serial ISP (In-System-Programming) (High-speed I2C-bus)
Upper 32KB
8000H
7FFFH
ROMBK2/1/0
Common 32KB ROMBK<2:0> 0 to 32K 32K to 64K
Philips Semiconductors
0000H 000 Common Bank0
001 Common Bank1
010 Common Bank2
011 Common Bank3 res.
• Extension above 64KB by 100 Common Bank4 res.
ROM-bank switching (via SFR, 101 Reserved Reserved
110 Reserved Reserved
supported by Keil C51 compiler) 111 Reserved Reserved
I2C-bus: +3.3V
3k3
3k3
TV chassis
processor
80c51
PC SCL
TV
I2C 10E
SDA HW-I2C
interface 10E ISP
FLASH SSD
WISP, 470E
WIC32 470E Other I2C slaves
Philips Semiconductors
• I2C can be disconnected from outside-world. Internally it connects:
– TextControlGraphics µ-processor
– TV processor
– Digital Sound processor
– ISP (In-circuit Serial Programming) of FLASH memory blocks
The duty cycle of the I2C-bus SCL clock output can be selected according
“STANDARD” of “FAST” mode by bit F/S in SFR FSBIR.
The maximum clock speed is set:
- in F/S mode via SFR FSBIR<4:0>
- in Hs mode via SFR HSBIR<4:0>
3k3
3k3
3k3
3k3
TV chassis
processor
80c51
PC SCL
of alignment-data,
TV
IC2 10E
SDA HW-I2C
interface 10E
put Eeprom on a ISP
FLASH SSD
470E
“split-bus”, using 470E Other I2C slaves
software I2C (on any pair of free I/O pins)
– Keep this safety-bus very short
– Factory alignment data can be copied from HW to SW-bus, via a “software-
Philips Semiconductors
bridge” (= µC acts as I2C-slave on HW-bus and as I2C-Master on SW-bus)
The I2C-bus lines SDA & SCL will normally be quite long in a TV chassis.
Series resistors must be added to protect the connected IC’s against energy
pick-up, during flash-over of the picture tube or static discharges.
A split-bus with very short connection between µC and Eeprom minimizes the
chance that alignment data is destroyed by high-energy spikes.
GTV Function:
LibCoMa switch RI2C_SPLIT_BUS
ri2c_2ndBusAddresses
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Philips Semiconductors
• Enable Remote Control Processor (RCP)
• Initialize other I2C-bus slave devices
The first action after RESET should always be the definition of I/O pins like
Power-On/Off, Volume and Mute.
The micro processor communicates with the TV processor part via a standard
I2C-bus protocol (Slave WRITE address 8AH). To eliminate the risk that other
I2C-bus devices can disturb the communication to the TV processor part, we
advice to disconnect the external I2C-bus pins during each of these
transmissions.
In System Programming:
Philips Semiconductors
programming SW called “WISP” 2 1.365MHz 9
3 1.024MHz 12
4 819kHz 15
• Several I2C-bus speed-modes: 5 688kHz 18
– Normal (< 100kHz, rugged communication protocol) 6 585kHz 21
: : :
– Fast (< 400kHz, careful with capacitive bus-load) 31 128kHz 96
– High-speed (up to 2 MHz, adapted I2C-protocol)
ISP programming:
220E
220E
3k3
3k3
slaves
470E Low IN,MAX = 0.8V
Max. High IN,MIN = 2.0V
2.048MHz FLASH
PC
I2C ISP LowOUT,MAX = 0.4V
Picasso /
Hercules
USB
Hs-I2C SCL HighOUT,MIN = VddE - 0.4V
80c51
10E 10E
interface SDA
10E 10E
WISP
Programmer TV chassis
Philips Semiconductors
– “Single-Master” or “TraCII”, via Centronics parallel port (Normal / Fast mode)
– “TraCII-XL”, via rugged USB-port (Normal / FAST / High-speed mode)
In System Programming:
Open Flash-lock
Philips Semiconductors
Write Flash Write pages of 256 bytes
error
Verify Flash Read CRC checksum
OK
Power-On-Reset Hard-reset to resume normal mode
Always check the internal I2C-bus is coupled & not blocked, prior to opening
the Flash-lock. While the flash-lock is open, the 8051 core is forced to execute
“NOP” instructions (= SW effectively standing still)
I2C-addresses:
Philips Semiconductors
– Free programmable by SW in SFR S1CON.
– Hardware can only be given ONE slave address
– Used by “Work-Bench” I2C-bus software
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RXD
TXD
Philips Semiconductors
1 Timer1 overflow rate
start-bit=0, 8 data-bits (LSB first), stop-bit=1
11-bit transmitted by TxD or received by RxD: 1/32 or 1/64 of µC
2
start-bit=0, 8 data-bits (LSB first), a 9th data-bit, stop-bit=1 clock
3 Same as Mode-2 Timer1 overflow rate
Philips Semiconductors
• Most protocols have a special start-bit timing:
- RC-5 use bi-phase modulation, no real start-bit
- RC-6 is 2x faster than RC-5, with start-bit
Bit-decoding is done by software and the filters are programmable over a wide
range. Therefore this RCP is compliant with all known commercial infra-red
RC-protocols.
GTV Function:
rbsc_GetRemoteKey
LibCoMa settings for RC5 and NEC protocol. Also any other High/Low
time modulated protocol can be configured using LibCoMa
(RBSC_REMOTECONTROL_RCP_XXX)
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Example:
RC5 bi-phase (at INT pin) :
command 53DEC
Not-enlargedbit=1/0
Togglebit=1/0
C5
C4
C3
C1
C0
S4
S3
S2
S1
S0
C2
Command repetition =
64x2tp= 113.78ms
address
code
bits
bits
6 Control
5 System
Philips Semiconductors
Japan code (at INT pin) :
Start-bit 0 1 0 0 1 1 0 0 1 0 0
8tp 4tp tp tp tp 3tp
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Phase 1:
IF INT goes high again before Cntr has reached AL
High
Low Period
THEN the LOW period is too short => exit Period
ELSE count µC clocks in Cntr until it reaches AL, then reset Cntr
Phase 2: AH BH
IF INT does NOT go high before Cntr reaches AH
THEN the LOW period is too long => exit
ELSE copy Cntr value into result register RA and reset Cntr RA RB
Phase 3:
IF INT goes low again before Cntr has reached BL SW programs limiting values:
Philips Semiconductors
THEN the HIGH period is too short => exit AL = minimal LOW time 75%
ELSE count µC clocks in Cntr until it reaches BL, then reset Cntr AH = maximal LOW time minus AL 125%
BL = minimal HIGH time 75%
Phase 4:
BH = maximal HIGH time minus BL 125%
IF INT does NOT go low before Cntr reaches BH
THEN the HIGH period is too long => exit End results in output registers:
ELSE copy Cntr value into result register RB and reset Cntr RA = LOW time minus AL
generate an interrupt to wake the micro RB = HIGH time minus BL
if micro can react within AL, then interrupt-latency = zero
RCP-Implementation:
CASE State OF
Edge/Level
Write-only 1: IF (PosEdge AND Cntr<AL)
state TCON THEN State:=5 {Low pulse too short}
PosEdge CDIV ELSE IF PosEdge
Spike filter
DAT
2: IF NOT(Cntr<AH)
NegEdge AH 2 Int0 THEN State:=5 {Low pulse too long}
3 DRCP ELSE IF PosEdge
BL
THEN RA:=Cntr; Cntr:=0; State:=3
BH 4
3: IF (NegEdge AND Cntr<BL)
THEN State:=5 {High pulse too short}
SFR
Logic
24.576 12.288 Comparator < THEN Cntr:=0; State:=4
MHz MHz 1 4: IF NOT(Cntr<BH)
:2 (CDIV+1) Counter Cntr THEN RB:=Cntr; State:=5 {High pulse too long}
ELSE IF NegEdge
Read-only THEN RB:=Cntr; NFP:=1; State:=6
CDIV = ClockDIVider RA 5: IF (NFP=1)
Philips Semiconductors
Mux
• Suitable to measure 1.5 bit “Data-Clean” time after a string (added: “RB:=Cntr”, State 4)
Data capture:
Philips Semiconductors
- Supports eXtended Data Services (XDS)
- Supports Violence Chip transmissions
- Processing in software
Closed Captioning data is transmitted at a much lower data rate than teletext
(only 2 bytes in line 21 at 525 or 25 at 625 line transmissions). CC data
processing is simply done in software during the Vertical Blanking Interval
(VBI).
Philips Semiconductors
Double Window mode (50% compressed video + a TXT/CC panel)
• Scan Velocity Modulation (separate for video and for TXT/CC)
The OSD is internally inserted in the RGB path of the video processor.
It automatically tracks to the brightness setting of the main picture, but it is not
affected by saturation or contrast control. For optimal readability, the OSD
contrast can be given an offset.
In general the OSD will use the CC-type of display, with its extra features. The
TXT type of display is maintained for easier display of Teletext pages. Display
mode TXT and CC can not be used simultaneous within ONE page
(but is possible in 2-page mode).
Philips Semiconductors
• Fringing (shadow) in both TXT and CC Display Modes
• Italics, Under-line, Over-line and Scrolling
available in CC Display Mode
The number of TV scan lines per display row can be set to 10,13,16 or 18 and
is independent of the character size being used.
In 525 line display mode (60Hz) the value of 10 is automatically changed into 9
lines per row.
According CC standard EIA608B max. 80% of visible screen may be used for
CC. At 60Hz with 525 lines this is: [525/2 - 23] * 0.8 = 192 lines. Using 12x13
character fonts this allows max. 14 lines of CC.
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Philips Semiconductors
(Dynamically Re-definable Characters)
Joined Characters:
Compose a 24 x 16 Compose a 24 x 20
character from two
Philips Semiconductors
character from four
12 x 16 characters 12 x 10 characters
Double width
Double height
Philips Semiconductors
double width
Philips Semiconductors
Contrast reduction local yes yes
DRCS 64 global 64 global
Character matrix HxV 12x 9/10/13/16 12x 9/10/13/16/18,
16x16/18
Rows x Columns 25 x 40 16 x 48
Displayable characters 1000 624
4-colour characters 32 32
What is TeleteXT:
Philips Semiconductors
Skip section about TXT
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Philips Semiconductors
• Auto-detect & forced acquisition modes on lines 7..17 (VBI), or full field
• 37 bytes/line, 32 bytes of which are stored in rows 0-23 of page memory
• Capable of acquiring packets X/0/0, X/0/1-24, X/T/1-24, X/0/26/X, X/T/26/X,
X/0/27/0 4/0/30/X and 4/T/30/X.
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Philips Semiconductors
(625 line sync, 64µs period)
• 28 data bits (bi-phase decoded) stored as 7x5-bit words (4 data bits plus bi-
phase error flag) in row 25 of page memory
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Philips Semiconductors
lines 1..32 (525 line sync, 63.56µs period), in either or both fields (default line
21)
• Stored as transmitted (i.e. odd parity encoded) in two registers,
ccdata1<7:0> and ccdata2<7:0>
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TXT levels:
Philips Semiconductors
• Level 2.5 (hardly transmitted → not in Hercules)
This is row 23
– Extended language range Next Page Prev Page Other Page Index
– Non-spacing attributes
– Increased colour palette with re-definable colours
– Enhanced graphics, e.g. DRCs + side panels
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VBI
Visible
Philips Semiconductors
TV picture
Field fly-back
(retrace)
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Next Page Prev Page Other Page Index
X/25 rarely transmitted, not decoded
Page related Extension Packets X/26 / 0..15 special characters
for Level 1.5 (“Ghost-Rows”) X/27 / 0..15 Fastext links
X/28 / 0..15 not decoded
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Philips Semiconductors
- Page attributes: Subtitle / NewsFlash / Erase- / Update-Page /
/ Interrupted-Sequence / Serial- / Parallel-Transmission /
/ Inhibit-Display / Language-Control / Suppress Header
• Columns 8..31 contain 24 bytes of header information
(broadcaster, page number, date etc.)
• Columns 32..39 normally contain the time (HH:MM:SS in 8 bytes)
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Philips Semiconductors
• Serial (spacing) attributes: Foreground / background colour / Boxing /
Text size (Double height/width/size) / Flashing /
Conceal / Text- / Block-graphics
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• Without Fastext, row 24 can be used for alternative page navigation (e.g.
Philips Semiconductors
“Favourite Pages” mode)
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• Downwards compatibility, e.g. :
Older decoders that can not decode packet 26 information, will display
the normal body packet information: e.g. ‘a’ instead of ‘ã’
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- Data field (7 bits)
Examples: Row address group & Mode 00100B : “Set Active Position”
Column address group & Mode 01111B :“Character from the G2 set”
• Max.16 Packet 26’s per display page (=208 triplets), using the
“designation code” (= data byte used as Packet 26 address extender)
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• Defines the page that the Fastext colour keys should access:
– Links 0..3 correspond to Red,
Red Green,
Green Yellow and Cyan
Philips Semiconductors
– Link 4 is the ‘pre-capture’ link (“start-page” or “Magenta”, usually ignored)
– Link 5 is used for the Index (White) key
• Link Control byte can disable some or all of the links
• Transmitted using 8:4 Hamming encoding
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Philips Semiconductors
• Universal Time information
• Broadcasting network identification
– Format 2: (DC=2 or 3), Service Data includes:
• Initial display page number
• Programme identification
• PDC Information (Programme Delivery Control)
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Elements of a Magazine
Philips Semiconductors
and number of sub-pages
Elements of the Service
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Packet Transmission:
• Packets 1..24 may be transmitted in any order and multiple times per
page (a method most often used for subtitle pages)
Philips Semiconductors
• Page is opened: when a header for a particular page arrives
Page is closed: only when another header packet arrives
(in parallel mode: when page-header in same Magazine arrives)
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• All pages except those with attribute “interrupted sequence”
(used by pages that are transmitted frequently & therefore
out-of-sequence so that they are quickly accessible)
– Parallel Transmission:
• All pages in the same magazine as the one being searched for except
those with attribute “interrupted sequence”
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Teletext Time:
Philips Semiconductors
• Parallel transmissions:
– Only from page headers in same magazine as current display page.
Time may vary between magazines, as different magazines may be
provided by different sources (National / Local)
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Page Numbering:
Page Subcodes:
Philips Semiconductors
• All pages have a subcode 0..3F7FH (no subcode uses value 0)
• BCD subcode numbers are used for displayable sub-pages
• Subcodes 0..79H can be stored individually by page gathering
applications such as Multi Page Teletext
• Subcodes > 79H will overwrite subcode 0 (according WST Teletext standard)
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TOP Transmission:
Philips Semiconductors
Row 24 should show: next / previous page, next block, next group
• Block + group pages have names, transmitted on Additional Information
Table pages (AITs, whose HEX page numbers are in BTT info)
• To improve TOP navigation, broadcasters can transmit a “Hitlist”
in the BTT, to be compiled & displayed by TXT application SW
E.g: List of today’s most interesting pages → internet style “What’s new”
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Philips Semiconductors
Skip section about CC
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Line 21 Services:
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– XDS = 1 stream of transmission related info (
( eXtended Data Services includes “Content Advisory info”, often called “Vchip”)
Philips Semiconductors
• Odd / even field identifies streams that use same control codes:
– Field-0: CC1 / CC2 / T1 / T2
– Field-1: CC3 / CC4 / T3 / T4 / XDS
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01H Time of day
02H Capture ID
07H Miscellaneous information 03H Data Location
04H Local Time Zone
40H Channel Number
01H Weather Code
09H Public service information
02H Weather Message
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Philips Semiconductors
• First control byte determines CC1/CC3 and CC2/CC4:
– In field-0: CC1 or CC2
– In field-1: CC3 or CC4
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CC1 CC2
Byte 1: CC Stream Type Code Byte 2: CC control action
CC3 CC4
11H 19H Special Character Codes: E.g: ® , ™ , â
allows display of non-ASCII
characters
11H 19H Mid Row Codes: 20H / 21H - White / Underline
set/change foreground colour, 22H / 23H - Green / Underline
underline or italics 24H / 25H - Blue / Underline
26H / 27H - Cyan / Underline
28H / 29H - Red / Underline
Philips Semiconductors
2AH / 2BH - Yellow / Underline
2CH / 2DH - Magenta / Underline
2EH / 2FH Italics / Underline
17H 1FH Miscellaneous Position: 21H Tab offset 1 column
add tab offsets to data position 22H Tab offset 2 columns
( 1 tab = 4 spaces ) 23H Tab offset 3 columns
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29H Resume Direct Caption (Pain On)
2AH Text Restart (Clear Memory)
2BH Resume Text Display
2CH Erase Displayed Memory
2DH Carriage Return (New Line)
2EH Erase Non-displayed Memory
2FH End Of Captions (Flip memories)
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Philips Semiconductors
z=0/1 Indent 0 / Indent 0 underlined
z=2/3 Indent 4 / + underlined
z=4/5 Indent 8 / + underlined
z=6/7 Indent 12 / + underlined
z=8/9 Indent 16 / + underlined
z=A/B Indent 20 / + underlined
z=C/D Indent 24 / + underlined
z=E/F Indent 28 / + underlined
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Philips Semiconductors
– one line of the display to be used for OSD (CC1..4 or T1..4 modes)
RDS / RBDS:
Philips Semiconductors
– Bi-Phase-Shift-Keying demodulation & clock recovery
– RDS / RBDS block detection
– Error detection & correction
– Fast block synchronization & “flywheel”
– RDS/RDBS data & status info available in SFR registers
– Interrupt to synchronise RDS-processing SW with new RDS data
GTV Function:
prds_EnableRDSDecoding
prds_GetMS, prds_GetMSStatus
prds_GetPI, prds_GetPIStatus
prds_GetPS, prds_GetPSStatus
prds_GetPTY, prds_GetPTYStatus
prds_GetPTYN, prds_GetPTYNStatus
prds_GetRT, prds_GetRTStatus
prds_GetTP, prds_GetTPStatus
prds_GetTA, prds_GetTAStatus
prds_GetHours, prds_GetMinutes, prds_GetTimeStatus
prds_GetDay, prds_GetMonth, prds_GetYear, prds_GetDateStatus
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restore 4:3 aspect ratio
4:3 transmission as
displayed on a 16:9 tube
The video ADC writes into a line-memory (sample frequency = 27MHz), while
the display reads back from another line-memory (alternating).
The scaling mode is set in SFR Video_process DW_PA:
Note:
When line-compression is not needed, we advice to switch-off the digital
interface (DINT=0).
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P101
Philips Semiconductors
TXT TXT
----------------------- ----------------------- -----------------------
Panel A Panel B
OSD OSD OSD / CC
PHILIPS PHILIPS NO OVERLAY
Double Window:
Function enabled by SFR : DW_PA<1:0> of Video_process reg. = ‘01’
Show Video / TXT, Video / CC, compressed video
Two Page:
Function enabled by via MMR (87FF): Two_Page Configuration register.
Show TXT / TXT on 2 panels side-by-side
?? Twin page
CC-CC
not possible ?
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Philips Semiconductors
(output only) (input only)
PxCFGA<y> = 1 PxCFGA<y> = 0 PxCFGA<y> = 1 PxCFGA<y> = 0
PxCFGB<y> = 1 PxCFGB<y> = 0 PxCFGB<y> = 0 PxCFGB<y> = 1
The 4 different modes of operation for the pins of Port 0,1,2,3 are selected by
SFRs P0CFGA/B, P1CFGA/B, P2CFGA/B, P3CFGA/B.
“Push-pull” should only be used with adequate EMI-stoppers.
“Quasi-bi-directional” is used during (fast) IC-factory testing. Here the active
pull-up is on during one clock cycle (81.3ns), to obtain fast rising edges.
The “Open-Drain” output configuration is 5V tolerant, so if the U.O.C. has to
interface with 5V logic, this is the configuration that should be used.
The “High-Impedance” configuration can also be used during standby mode, to
reduce current consumption. “High-Impedance” is also 5V tolerant, but it has
no output possibility.
GTV Function:
rbsc_ConfigPort, rbsc_ConfigPin
rbsc_SetPin
rbsc_SetMLPin
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Philips Semiconductors
(see Notes Pages below …)
The following I/O port operations read the port latches (not on port pins)
ANL logical AND, e.g: ANL P1,A
ORL logical OR, e.g: ORL P2,A
XRL logical EXOR, e.g: XRL P3,A
JBC jump if bit=1 & clear, e.g: JBC P1.1,label
JB/JNB jump if bit=1/bit=0, e.g: JB P2.0,label
CPL invert bit, e.g: CPL P3.3
INC/DEC inc/decrement port, e.g: INC P1
DJNZ decr. & jump if not zero e.g: DJNZ P1,label
MOV Px.y,C move carry to bit
CLR Px.y clear bit
SET Px.y set bit
Some are “Read-Modify-Write” instructions (ANL,ORL…), that read the port-
latches, do their operation & write the new byte back to the latches. This avoids
possible mis-interpretation of the voltage level at the pin.
I/O ports:
Timer 0
Timer 1
UART
INT 0
INT 1
INT 2
BIT 6 BIT 8 BIT
I/O SCL SDA I2C
PWM PWM ADC
Philips Semiconductors
106 102 97 128 127 98 99 107 126 108 109 111 112 123 115 120
The I2C-bus peripheral is also used for communication between the micro
processor core, stereo sound decoder and the video processor part (efficient in
silicon area, low radiation). For multiple (split) I2C-busses, simply use 2 I/O pins
to implement SW-driven I2C (e.g. for safety of EEPROM with alignment
settings).
Port P2.0 can be switched as 14-bit PWM for Voltage Synthesis Tuning
(SFR register TDACH.bit7=1 enables TPWM on port 2.0).
All other pins on Port 2 can be switched as 6-bit PWM.
The SW-ADC can select one out of four Port3.x pins via SFR register SAD
GTV Function:
rbsc_SetTDAC
rbsc_ConfigPort, rbsc_ConfigPin
rbsc_SetPin
rbsc_SetMLPin
rbsc_GetADC
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Successive ADC0
Philips Semiconductors
ADC1
Approximation ADC2
+
DAC ADC3 VHI
8 bit
- ‘0’ for input voltage ≤ DAC
SFR: SADB<7:0> static Int1
SADAC
DC compare mode
The output of the comparator can be coupled to Interrupt 1. This is useful e.g.
to generate a wake-up signal when a local keyboard switch is pressed.
Philips Semiconductors
6. Enable INT1 using the IE SFR.
7. Enter Power-Down/Idle/Standby. (sleep until wake-up trigger)
8. Upon wake-up, restore SAD to conventional operating
mode by disabling the DC_COMP bit.
The DC-wake-up threshold level should correspond e.g. with a certain local-
keyboard switch in a resistor-divider network at 3.3VSTANDBY.
GTV Function:
LibCoMa setting: RBSC_KEYBOARDWAKEUPTHRESHOLD
rbsc_LocalKeyboard
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6 bit PWM-DACs:
Philips Semiconductors
+3V3 or +5V
10k
Analogue
PWMx 10K Voltage
D5..0
10.42µs
GTV Function:
rbsc_SetPWM0, rbsc_SetPWM1, rbsc_SetPWM2, rbsc_SetPWM3,
rbsc_SetPWM4, rbsc_SetPWM5, rbsc_SetPWM6
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Philips Semiconductors
TD 13..7
TD 6..0
The seven most significant bits TD <13:7> determine the basic HIGH period
between 0 and 20.83µs, with a resolution of 0.164 µs.
This allows fast settling of tuning voltage jumps, e.g. when changing channels.
The seven least significant bits TD <6:0> can extend 1 up to 128 of the basic
periods by 0.164µs.
Example:
if TD<6:0> = 01H then 1 in 128 periods will be extended by 0.164µs
if TD<6:0> = 03H then 3 in 128 periods will be extended.
– Emulator+Glue+adaptor+socket: WWW.HITEX.DE
Emul. Adaptor
Picasso
PR7306x
– High-speed I2C interface: WWW.TELOS.DE
– C-compiler, linker & debugger: WWW.KEIL.COM Cosmic
Philips Semiconductors
• Two bond-out emulator chips : Picasso (=µC) & Cosmic (=TVP)
– For emulator purposes, we don’t want to swap IC’s
– Emulator uses MAX. version of Picasso & Cosmic bond-outs
– These can be configured to act as lower specified versions
(via I2C & SFR registers)
The Hitex-MX51 emulator box emulates Program ROM. The 80c51 core
executes its own program plus the monitor SW of the debugger system (while
halted).
Emulator box
Typical evaluation set-up:
HITEX
Emul. Adaptor
“Glue”
• Distribution through partners:
PR7306x
PHERC-A1
I2C
QFP128
Picasso
– Emulation, I2C, Compiler, support
QFP128
Cosmic flexfoils
WISP QFP128
I2C-bus I2C
interface Display
Philips Semiconductors
WIC32
tuner
Demo board
The emulator-adaptor panel holds two generic bond-out IC’s. Together these
can be configured to emulate all Hercules versions.
All direct components are on the panel, only the less critical signals are
connected via a flexfoil-cable to the QFP128 contra-socket (target).
The emulator-adaptor panel can run without a target connected (+3.3V, +5V,
+8V supplies needed).
Via the Hs-I2C programmer, the character ROM and some configuration data
must be programmed into the Picasso bond-out.
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+5V
3V3
+3.3Vstb
+3.3V from target
Which Vdd goes where ?
DecDig
80C51 core followers metry
+1.8VddCore 117 1.8V
D0..7 &
Emulation RAM / ROM
IntD
+3.3VSTANDBY
FlashProm
Latch
AD0..7 IF,
IrefO 2.5V 14
ALE +3.3VddA Audio
A0 V1V8Se video
+2.5V ref
..17 A8..17 ClkoP+N +3.3VSTBY
P_TmSel +3.3V
PSEN 88
SifInP+N +Vp1 for Geo from
RD
VrefAd
connector
target
Philips Semiconductors
WR 16
Snd1,2outL+R +3.3VddA I2C+Hdrive
MCM interface
Computer
SndInL,RP+N 47
EA +Vp2 for IF&sw +5V
Csi,H,VdispI
BndSel Sda,Scl2Out+In +Vp3 for RGB 82
Y,U,Vout+In 69
+Vdd for Comb
YuvRef
GLUE-board CorB,ScavTxt 45 +8V
+Vp8 for Scart
R,G,B,Vds
Picasso Cosmic TARGET
• All µC-I/O lines use 3.3V (1.8V only internal) Philips Emulator-ADAPTOR board PR7306x
Philips Semiconductors
DCM_CHAR = Duty-cycle measurement for character FLASH
DCM_PROG = Duty-cycle measurement for program & PK26 FLASH
ACU_PROG = Address count-up for program & PK26 FLASH
ISA_VIREF_PROG = Output sense amplifier (ISA) & 3.3V supply for program & PK26 FLASH
VPEX_PROG = +11V for program & PK26 FLASH
VNEX_PROG = -5.0V for program & PK26 FLASH
OVP = Overrule protection
Supply lines:
VddA = +3.3V standby supply, always present. Used to make 1.8V intern during sleep modes.
VddC = +1.8V, used by 8051 core outside sleep modes (limits internal dissipation)
VddP = +3.3V standby, supplies all I/O, MCM-interface & BondOut pins
On the emulator, it is preferred to use the Picasso Xtal Clock for all, because the
“DCXO” has internal, tunable Capacitors (= low PPM with simple Xtal).
Especially during NICAM decoding, this clock is carefully phase-adapted to the
incoming NICAM signal.
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Resource
CC TXT 100 ACI Sound Video Tuning Fn
page
Platform
Philips Semiconductors
Drivers
Hardware
Resource
• Change Management
Philips Semiconductors
• Access of device drivers via generic driver Device drivers
• Map generic driver API to device specific API Hardware
• Contains the run-time device configuration
• Register access
• Monitor hardware changes
• Implements functionality
Philips Semiconductors
In/Out
Author:
Philips Semiconductors - Business Line Mainstream Tv Solutions
E.C.P. Arnold
TV System Design - Eindhoven,
The Netherlands
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Philips Semiconductors
• Clear ALL items in start-up phase, everybody involved
should be aware of the chosen design method
• Define ground structure for whole TV set
• Make first model and evaluate
First define (check) a ground structure for the whole TV set (including tube,
speakers, connectors, mains filter etc.). Pay special attention to the signal
transfer structure AND the return-currents for each signal.
Around IC’s, Guard Rings are recommended. Sometimes shielding is
required, that may be part of a Guard Ring.
Finally adapt the chosen structure for optimal application.
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Philips Semiconductors
• Guard Ring enables simple-but-effective optimization
– It’s inside is “isolated” from the environment
– A MUST for Single-layer PCB technology, model also applicable for
Multi-layer with reference ground plane
Disturbing Ground
Current: ID Single Connection ID
1/
2 ID
Philips Semiconductors
2. Ring shields capacitive coupling
3. Low pass filters to Ring, NO other tracks in guard area
4. Easier EMC experiments: marginal influence on the rest
5. Guard ring as large, hollow star ground for other circuits
6. Last rescue: shielding box (connected at many points to the Guard Ring)
With an ideal Guard Ring, a disturbing ground current can not flow under the
IC, only through the Ring.
The Guard Ring makes it possible to put the IC on its own, “clean” island.
With this construction your engineers can do trouble shooting in an effective
way: solve something WITHOUT introducing two new problems !
In areas where EMC qualifications are not mandatory by law, we still advice to
use the guard ring approach to obtain a good performance.
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Disturbing Current: ID B ID
∆ID
C ZLOCAL = IC pin
∆ID to local ground
impedance
Philips Semiconductors
7. Keep ZSERIES Ohmic (A, B, C) for predictable HF behavior
8. Stray capacitance over resistors = 0.5 .. 1 pF,
Parallel wires = 1pF/cm, Series Inductance = 10nH/cm
9. Ring length NOT equal to λ of expected radiation
For a predictable High Frequency behavior, it is best to try to keep the series
impedance's Ohmic. This is less simple than it looks, because all components
have parasitic properties.
If you expect strong fields with a certain frequency, the length of any loop in
the PCB should NOT be equal to that wavelength (antenna).
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Non-ideal Ring:
Disturbing Current: ID ID
∆ID
ZGUARD
∆ID ∆ID
Philips Semiconductors
10. ∆ID: voltage over ZGUARD: local currents ∆ID through IC
11. ZSERIES must be made as high as possible
12. Ring = 3 to 5mm wide for low Ohmic part of ZGUARD
The impedance of the Guard Ring itself can not be zero. Disturbance voltages
over the Guard Ring can cause unwanted currents ∆ID through signal tracks;
even local mesh currents. THIS is the main reason why EMC problems are so
hard to tackle.
Philips Semiconductors
• Connect the rings firmly to ground
• Put RF-blocking in every connection (choke, LPF or high impedance)
The Guard Ring applies also on a macro scale, for large PCB design.
Circuits should not influence each other, so we isolate each one within its
own, individual Guard Ring.
Philips Semiconductors
Important rules, step by step
• Put a ground plane under the IC, directly connecting ALL ground pins.
?? Untill
ES7.2D:
Ground references:
add 2x 6p8
125
121
101
1
95
capacitors 92
G 6
8 Digital ground-plane 89
u
• Low impedance a Xtal
12 Analogue-plane
between ground pins r
= ground plane d 81
R 18
“ground-plane”
i under IC,
Philips Semiconductors
• Single-sided PCB: n
VIF locally extended
g
extend ground-plane outside pinning
28
and connect via SIF 68
40
multiple tracks
CP
CC
CA
CA,LF
Philips Semiconductors
• Parallel ground wires = less inductance = better reference
• Extra coil in digital VDDCore ⇒ effective on-chip decoupling
Ground connections:
The voltage reference inside the IC is connected via several parallel bonding
wires. The resulting inductance is low enough to avoid ground-bounce by AC-
currents (all I/O pins would start radiating).
Supply, VDDPeripheral and VDDAnalogue:
Analogue circuitry needs good, external decoupling, both HF and LF.
Supply, VDDCore:
Digital circuitry produces wide-band noise. On-chip decoupling helps to short-
circuit this inside the IC. Don’t put an external capacitor CC direct at pin VDDC,
because this will route more of the digital noise outside the IC. Better
increase the series inductance with LC,EXT because:
LC,EXT limits extern AC currents, ALSO through ground connection !!
(= less ground-bounce by switching of core circuitry)
(Voltage model:
larger L in supply = less voltage over small L in ground)
The supply-bounce will of course increase, but pure digital circuitry is quite
immune for that (practice value: LC,EXT = 2.2 µH to 15µH).
PLLIF
disturbances. Any modulation
40
can be visible on the screen
IF-PLL
Philips Semiconductors
• First 390Ω at pin 41, loop filter
then 100nF to ground
Between the resistor and the capacitor, we have a good monitoring point of
the IF-PLL loop filter voltage. That’s why the capacitor is connected to ground
and not the resistor. Use only a high Ohmic probe, otherwise you may
influence the IF-PLL too much.
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SAW 24 LPF
25 41
0o
IF inputs IF AGC VCO IF-PLL
90o Loop Filter
28
V/I
IF Ground 40
Philips Semiconductors
• Pin 28 is ground for SAW filter pin 3 (to internal IF circuitry)
• The lF-PLL loop filter is connected as short as possible, with a
separate track to ground pin 40
• Pin 18 and 40 must have a short connection (via ground plane)
The Application Manual gives details which ground pins are used as
reference for certain circuits. In all cases it is best to connect ALL ground pins
to a ground plane under the IC.
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Philips Semiconductors
near pin 18
18
• Take care that NO digital currents 19 = SECPLL
20 = Bandgap
can flow via pin 18 (will disturb Bandgap grounding)
Static offset can be visible, mostly in B-Y. This can now be compensated via
bits SB01..0. (Secam B-Y Offset adjustment)
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Digital decoupling:
Philips Semiconductors
⇒ add series resistor to keep
decoupling local 18
The DecDig pin 14 decouples an internal voltage of 2.5V. This voltage can be
used to make a self-controlled 1.8V supply. Via software it is possible to
enable a feedback from three 1.8V supply inputs towards the DecDig 2.5V
output.
During standby mode of the video processor, the DecDig pin is pulled low (<
0.4V at max 1mA sink current).
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121
101
• Guard-Ring 1
95
around high 92
6
impedant 8 89
zone
12
Local
reference 81
• Single point 18
ground
grounding
Philips Semiconductors
must have
LOW
28
inductance ONE
40 68
connection
Low inductance
Guard Ring:
The IC-ground should be grounded via ONE point only, near the tuner and IF
path. When ALL currents are kept local, there will be hardly any current
through the connection towards the Guard Ring. Still it is important to give this
connection the lowest possible inductance, to avoid problems with flashes
(surges, discharge tests etc.).
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121
101
• Iblack return 1
95
needs 92
6
clean path 8 89
B
G
12 R
• Guard-Ring Ibl
81
must have 18
low
Philips Semiconductors
impedance
28 69
68
• Comb filter
40
VDDCOMB only to
pin 68,
12µA Iblack-return
no shared
currents
The RGB cable that goes to the CRT panel (picture tube) is always long and
will act as antenna for disturbances. The three RGB outputs can be equipped
with filters, but the ground connection can NOT. Therefore it is best to lead
this to the Guard Ring.
Make sure the Guard Ring is low Ohmic, otherwise ground currents can be
super-imposed on the small measurement currents (12uA) of the black
current stabilization loop (CCC). This can show as loop instability.
The Comb-Filter supply input pin 69 must be decoupled to ground pin 68.
Since this is quite noisy, we advice to route pin 68 only to the ground-plane.
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• Dominant for
VIF
sync performance
Philips Semiconductors
28
SIF
The two phase loops are very sensitive, to get a good sync performance. This
also means that the phi-1 and phi-2 components need a good, clean ground.
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Philips Semiconductors
to the IC 27 = Iref
28
SIF
The vertical ramp capacitor and the current reference resistor demand a
clean, separate grounding to pin 18. Disturbance on these reference
components can easily be visible as “line pairing” on the screen. The human
eye is very sensitive to this kind of effects (up to -60dB).
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Philips Semiconductors
• Neutralize parasitic coupling
28
to VIF by decoupling Vdrive SIF
A/B
pin 22+23 at pin 18
and use series resistors
The connecting wires to the vertical deflection coils are long. They can easily
pick up disturbances, so the outputs of the vertical amplifier should be
equipped with filter chokes plus capacitors.
The large output transistors have large capacitive coupling to the amplifier’s
substrate. So HF disturbance can “walk-through” the vertical amplifier, into
the vertical drive lines. These are located next to the SAW filter inputs, so
pins 22 & 23 need to be decoupled near the IC.
At the position where the vertical drive lines cross the Guard Ring, it is best to
put 1k Ohm series resistors. If the drive lines are long, it may be better to add
a second filter stage. Keep the tracks between series resistors and pins 22,23
short to minimise parasitic coupled “body” to the VIF lines.
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VIF
Philips Semiconductors
28
SIF
“Method 1”
The tuner output is normally 75 Ohm. After the SAW filter the impedance is
higher (2 kOhm), so it is logical to put the SAW filter as close as possible to
the One-Chip.
The SAW filter substrate pin 3 should be grounded to the One-Chip pin 28,
via a clean, separate path.
The tuner should be connected to the IC main ground pin 18. Try to minimize
the total loop surface of IF lines and ground connections.
Philips Semiconductors
• You can connect pin 28 to 28
the IC ground plane, but switch SIF
ONLY after EMC-
“Method 2”
validation was proven OK
Try to keep the total loop surface of IF lines and ground connections minimal.
A large “body” will pick-up more disturbance than a small one.
Method 2:
Switch able SAW filters are usually driven form an a-symmetrical tuner. SAW
pin 2 has to be switched to either pin 1 or pin 3. This means we can NOT use
the SAW filter as separator (see “Method 1”) between Guard-Ring and IF
ground pin 28.
The alternative is to route the ground all around the IF-area.
The vertical reference components can now be connected differently, but try
to keep the SAW filter substrate (pin 3) free from modulation.
Use as many parallel ground connections as possible.
Video SC
SAW:
PC-CC PC CC
IF:
Low Z
PC-CC PC CC No shared
Philips Semiconductors
currents
f
40
4.43
29.5
33.9
38.3
40.4
55.7
Injected 28
disturbance IF Gnd Sym- IF Gnd
metrical
IF inputs
Injected
disturbance
IF path: 40
1 75 2k 4 25
+
Z13 Z23 Z43 Z53
Tuner
“Method 1” 3 28
UOCIII
1 ground connection: make use of Common-Mode rejection
Philips Semiconductors
+
+ “Method 2”
Method 1:
We advice to connect the main ground pin 18 to the tuner. Keep this ground a
bit close to the IF leads to minimize the loop area for magnetic coupling.
Method 1 clearly shows that currents, injected at the tuner metal housing will
NOT flow through the SAW filter grounding.
When the IF tracks are symmetrical, we can now use the Common-Mode
rejection of the SAW filter to “isolate” the tuner from the IC.
Method 2:
It is difficult obtain perfect symmetry. When the SAW filter performance is
critical, the tuner output amplifier should have the same ground reference as
the IF input amplifier. BUT: by connecting the ground via the SAW filter, ALL
other IC currents will ALSO flow through this path. To avoid IF disturbance, it
is best to route TWO ground tracks, next to the IF lines. Both ground tracks
must be connected:
- near the tuner,
- under the SAW filter, via its pin 3
- near the IC and to pins 28 and 18
Magnetic pick-up can be minimized by twisting the IF lines half ways, (SMD
jumper) between SAW filter and IF inputs (2kΩ) this can be very effective.
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Asymmetrical tuners: 40
1 75 2k 4 25
+
Z13 Z23 Z43 Z53
Tuner 3 28
Hercules
40
Philips Semiconductors
+
A 24
25
B
+ Switch
28
Single ended “asymmetrical” tuners should be connected to the SAW filter via
a symmetrical pair of IF tracks, routed close together.
For optimal filtering, SAW pin 1 should be IF-input and pin 2 ground.
For applications with a switchable SAW filter, a grounding near the IF path is
even more important. Usually an a-symmetrical tuner is used, to minimize the
switching components.
The switch is in the IF signal path: it either short-circuits filter “A” or “B”.
It is obvious that the return-ground from SAW to tuner has to be routed close
to the IF track.
Just like in “Method-2” on the previous slide, it is best to embed IF, SAW and
the complete switching circuitry between ground tracks.
Remarks:
- If the (capacitive) load of SAW plus switch is high (>12pF), an
amplifier/buffer is necessary in the IF signal.
- The command line of the switch should have a blocking impedance
for IF (& HF) frequencies, near the SAW filter. A transistor is NOT a
blocking impedance so a base resistor (47k) should be added.
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VR >3V
IF1 A
A Band switch
2 diode BA782
Switch B 5
IF2 high
3
+5V
• Minimal parasitic capacitances on Tuner
IF >3mA
tuner IF output = less components
R2
L1
• Enough reverse voltage to have
Philips Semiconductors
B
low capacitance of switch diode low
R3
R2
L1
C2
The Tuner IF output stage can usually drive up to 20pF capacitive load. With
two switch able filters (VIF+SIF SAW) plus wiring you can easily exceed this
capability. Therefore a coil L1 to ground is added, that will annihilate the
capacitive load and give a more “Ohmic” impedance.
Coil L1 now allow us to put DC-switching voltages on the IF-line without
adding capacitive load to it (parasitic capacitances of components).
Coil L1 is permanently AC-grounded via capacitor C1.
Note:
Although the switching transistor could be directly driven from an I/O port, we
add a second transistor + high Ohmic base resistor. This avoids EMC
injection into the SAW filter grounding.
Make sure that the +5V has a series choke plus proper decoupling (C2) to the
IF ground. The series choke has to block EMC injection via the supply.
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• In first layout:
provision to split
121
101
125
1
ground-planes 95
into digital and 92
6
analogue part 8
“ground-plane” 89
under and B
⇒ Solve cross- Xtal
12 outside pinning
G
R
talk issues in Ibl
chassis 81
18 Guard-Ring around
⇒ Re-connect high-impedant zone
Philips Semiconductors
after evaluation
VIF
28
PLLIF
• Connect 28 to SIF 40 68
ground-plane
after validation Single Point
Grounding
It is best to start a new layout with the ground plane and the Guard Ring.
During the layout phase, e.g. series resistors can be used to jump over the
Guard Ring. In this way the copper area, spent for better grounding can be
“hidden” under the components. Thus minimizing the extra PCB area for the
Guard Ring approach
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Local Ground-
Ground strip under
Ground
plane
parasitic parallel capacitance
R
Philips Semiconductors
to minimise the parasitic
capacitive coupling to long lines
Even with double layer material a ground plane under the IC is still necessary.
This assures that all ground pins share the same reference-potential. No
currents should ever flow into one ground-pin, through the IC and then out via
another ground-pin.During flashes (=high dI/dt) this might pull certain parts of
the silicon below zero and cause malfunction.
Keep layer3 as
Layer2 = “GND” un-interrupted
ground layer / shield
Philips Semiconductors
Layer3 = GND
5 V Power
Plane
Layer4 = Signal
Gnd3
Ferrite Ferrite
Bead 5V Bead 3V3
Philips Semiconductors
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Philips Semiconductors
ü5- Single-point grounding near IF (or symmetrical around IF tracks)
Pure digital circuitry like a micro-core - with On-Chip decoupling - can handle
quite some supply bounce. Use this property to limit radiation:
put a coil in the core supply BEFORE decoupling it.
Reserve a small capacitor directly on the pin, but do not mount this unless the
supply bounce is too high. For C18 process the max Vdd-peak = 2.4V.
The IF part is the most delicate one. Therefore we give it the best possible
ground reference.
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Summary of grounding:
Philips Semiconductors
– pin 110 to pin 121
– pin 124 to pin 125
– pin 82 to pin 81
– pin 69 to pin 68
– pin 14 to pin 12
– pin 15,16,17,19,20 and pin 22,23 and pin 26,27 to pin 18
• Keep digital currents away from DECBG decoupling pin 20 to pin 18
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Philips Semiconductors
- Evaluate IC, Hard- and Soft-ware
- Have a realistic reference TV
- Small-Signal “Plug-In” allows quick comparison between
various IC concepts (e.g. UOCII versus UOCIII Hercules)
Test results are significant for customer implementations, because the USB
layout is as “realistic” as possible. The Plug-in module hardly affects system
performance, especially not when the connectors are skipped and the Plug-in
is directly soldered onto the USB chassis.
Audio
GreenChipTM
Filter
Vertical
TDA8357
Driver
Mains
SAW
East-West
Transistor
Philips Semiconductors
Tuner LOT / FBT
Line
Transistor
If you start building a receiver, you always start with the large components.
The rest of the PCB is for Vertical, Audio and Power Supply.
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Audio
GreenChipTM
Filter
Vertical
TDA8357
Driver
Low CRT Mains
Impedance Supply
structure SAW IC
CRT
East-West
Transistor
Philips Semiconductors
Tuner LOT / FBT
Line
Transistor
The ground strip at the rear side is used to short-circuit radiation, picked up
between antenna cable and mains power cord (safety caps).
For HF disturbances, the mains filter and the SMPS transformer are easily
bypassed. To avoid unwanted coupling to the UOC, the central “back-bone” in
the ground pattern can be used as a barrier. Suppression filters at the
secondary side of the SMPS can be grounded to this structure.
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100E 100E
100n Line
75E
100p Impedance
68p Sparc gap
Inside IC Termination
circuits are
DC-coupled
Example: video input with DC-clamp
Philips Semiconductors
• Advice for first layout: (minimise risk)
reserve 68pF from each (audio &) video input to IC-ground (close to IC)
– Reduces risk of cross-talk (HF-pick-up, video-to-video, video-to-audio etc.)
– After test phase evaluation some capacitors may be deleted
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Flash precautions:
EHT
spark gaps
C1
D1
Video
D2 Amp.
V R2 R1
Cathodes
Aquadag
FBT/LOT
C2
Focus
Grid-1
Grid-2
Philips Semiconductors
IC H
Filament
RGB
R4
+8V
R5
C3
CRT
Supply
3V + 47k
1k
High
High
Config -
Sw 47k High
1 Mid
Mid 47k
47k Mid
Out +
Low
Low 47k
0.5V - 47k Low
Philips Semiconductors
3-level Open collector
decoder output buffers
• Less lines needed for switch functions
• 3-levels by switching between Open-Drain and Push-Pull
• SW can change I/O configuration per pin, at any moment
3k3
3k3
3k3
Px.x Lo 4k7
I
Mid III
Px.x Hi
4k7
IV
47k 4k7
5V compatible, 4mA
sink 4k7
Philips Semiconductors
• Only one transistor for +5 Volt tuner band switching
The band-switch inputs of a VST tuner usually have internal pull down
resistors of 4.7kOhm. With 5V tuner types, a band-switch is activated when
the input pin is above 4.5V. This specification can not be met by a micro
controller that is running at 3.3V. But since the digital UOC outputs are 5V
tolerant, we can add pull-up resistors of 3.3kOhm to +8V. Together with the
4.7kOhm pull-down this gives a “high” level of 5V.
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+8
CC PC CC PC CC PC
4k7
1k8
SC 1 L1
1 1
4
IF 4.43 38.9 4
IF1 4.43 38.9 4
VIF1 +8V 2 4.43 5
VIF1
1k8
5 5 33.9 38.9
IF2 VIF2 VIF2
1k8
4k7
/ 1336
UV1316
3 K3953M / 53D
2 2
3.58 3.58
10k
10k
3 3 K72xx
1k8
SC
38.9 = K7252M Euro 1 5.5 .. 6.5
SC 4
SW 38.0 = K72xxM China 1 5
SIF1
45.75= K72xxM USA 5.5 .. 6.5 4
5
SIF1 SIF2
10k
10k
2 L1 : 40.4
SIF2
Philips Semiconductors
2 4.5 3 K9656?D
3 K96xx
38.9 = K7257M+K9653D Euro 1 4
38.0 = K7262M+K9655D China 8MHz 5
2 36.15
3 X6966M
Global Traveler:
LS LS • NTSC-M-N,
Philips Semiconductors
Y/CVBS Micro controller
C 32 .. 192K ROM
1 .. 2K RAM +115V
Teletext +3.3V De-
Closed Captioning TEA1507 Gauss
Stby
On Screen Display GreenChip SMPS
Keyb RDS/RDBS
Stereo processing 24.576MHz
I2C
PCA8521 I2C-2 PCF85116
RC-5 Transmitter IR 2Kb EEPROM
EA99009
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10k
Comp
VGUARD RCOMP
Comp 9
ZCOMP B
VOUTA i COIL
i COM + ½i VERT
700
1 InA LDEFL
650 IDRIVEA < 560 7
600 1n 2k7 + RDAMP
D VFEEDBACK
IDRIVEA,B (µA)
A
400 i COM - ½i VERT
IDRIVEB 1n 2 InB
RMEAS
Philips Semiconductors
200
< 560
150
2k2
2k2
100 RCON 4
00H 1FH 3FH C
VA 5 Gnd VOUTB
TDA10xxx
TDA8357/59
The improved vertical amplifiers TDA8357 & TDA8359 (2 & 3A) have:
• Higher LVD-MOS IC process voltage 68V (was 60V for bipolar 8351)
• Better SOAR because DMOS has no secondary breakdown
• Lower dissipation and lower scan voltage (e.g. +13V , was +16V)
• Improved reliability: homogenous heat distribution across the device
• Reduced dissipation at end of flyback (add zenerdiode + resistor)
The required input biasing plus the conversion from current into voltage is
done via two fixed resistors RCON of 2.2kΩ. The gain of the vertical amplifier
can be selected by RMEAS.
• Max. peak current (while VA = 3FH) out of IDRIVEA or B is :
ICOM+¼ IVERT,MAX = 400 + 300 = 700µA
• Input voltage at pins 1 and 2 should remain below 1.6 Volt :
700µA x 2.2kΩ = 1.54 Volt
• Nominal (VA=1FH) differential voltage between InA,B or over RMEAS is:
950µA x 2.2kΩ = 2.1 Volt
• RCOMP must be calculated (see data sheet), voltage of ZCOMP=VP.
• IDRIVE pins max. output voltage = 2.5V ⇒ series resistors < 560E
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Horizontal Deflection:
Philips Semiconductors
secondary
voltages
100
8 TDA8359
Guard
VGUARD ↑ 3.60V and ↓ 3.45V
Philips Semiconductors
•
10k
• All EHT & beam current via pull-up
• Anti-ringing filter close to FBT (large currents)
• EHT compensation fast, average BCL is slow
• High-impedance = EMI-blocking in long connection line
The transistor-integrator for BCL gives a “fast-attack” and “slow-decay” for too
high beam current. Further it enables sharing ONE (long) line over the PCB
with the EHT compensation input.
The vertical guard pulse should be connected to the VGUARD input. Make sure
that the (long) VGUARD line is sufficiently “blocked” The vertical pulse should go
>3.60V and return <3.45V before video-line 17.
Make sure the > 4µ7 capacitor is directly connected at the BCL pin (no
resistor in between), otherwise the Peak-White-Limiter can start oscillating
(typical rhythm of 2 µs periods, see Peak-White-Limiter function).
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BCL voltage:
Philips Semiconductors
2.8
BCL below 0.8V :
1.7
Blank RGB outputs
0.8
• Reducing CON & BRI limits max. beam current (e.g. 1.5mA)
When the Beam Current increases, the voltage on pin BCL decreases. As the
BCL voltage drops below 2.8V V, first the CONTRAST will be reduced (no
loss of visible video).
If this is not enough to limit the Beam Current, the BCL voltage can drop
further. Below 2.4 V (bit CBS=1) or 1.7V (CBS=0), also the BRIGHTNESS
will be reduced. This can push the low-intensity part of the video below black-
level.
Below 0.8 V the RGB outputs are forced to blanking level (= slightly below
“black” level).
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Vtune [Volt]
Steepness
28
[MHz/Volt]
X
R1
= 7
[MHz/V]
Steepness
R2
3.5 0
0 Tuning [Volt] 30 0 Duty Cycle [%] 100 0 Duty Cycle [%] 100
850 850
Philips Semiconductors
Frequency
Frequency
[MHz]
[MHz]
We achieve this by using a “non-linear” integrator for the 14-bit tuning PWM
DAC. By selecting different charge and discharge time constant, we can
modify the translation from duty-cycle to voltage. When we multiply this with
the tuner steepness characteristic, the maximum steepness reduces
(28MHz/V) and the minimum increases (7MHz/V). Important is, that the
steepness variation reduces from 10 to a factor 4.
End result:
- more linear translation from duty-cycle to frequency
- more constant tuning resolution (better than 50kHz/step)
- no need to compensate tuning curve in software
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FIF
FRF
SAW U.O.C
IF in
PC SC FIF
50 .. 850MHz
Tuner SC PC IF
HF Osc
Osc
AGC AGC out
AGC
FRF+FIF
Philips Semiconductors
• IF-PLL can only “see” what
comes through the SAW
• Tuning up makes AGC react first
on PC
An off-air antenna signal FRF is mixed in the tuner with a local oscillator
(FRF+FIF) to a fixed Intermediate Frequency FIF. The value of FIF depends on
the market area (local laws, EMC relaxations) :
- Japan = 58.75MHz
- America & other NTSC countries = 45.75MHz
- China = 38.0MHz
- All others = 38.9MHz
The IF signal is filtered by a Surface-Acoustic-Wave filter, that passes only
the desired channel bandwidth around FIF (selectivity). The filter should
always be close to the U.O.C., because the SAW is the only frequency-
selective component in the whole IF path.
In the U.O.C. the IF signal is first “gain-controlled” (IF-AGC), then mixed with
an IF oscillator to “base-band” video. The audio carrier is removed in a sound
trap. The amplitude of the resulting CVBS signal is used to close the loop for
the tuner AGC (and IF-AGC). This gives a constant CVBS signal at variable
antenna levels (FRF).
Search-tuning can best be done in upward direction, so that the AGC loops
can settle on the Picture Carrier (see next slide).
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Philips Semiconductors
• For weak transmitters the catching range is only 1 MHz
- Conclusion: coarse tuning step size < 1 MHz (advice: 800kHz)
• Stepping high to low gives AGC jump + locking on SC
• Stepping low to high gives earliest locking on PC
When searching for a weak transmitter signal, the SAW filter attenuation
above FIF will limit the catching range to about 1MHz. The software search-
tuning algorithm should take care that tuning “steps” are always smaller than
this worst-case 1MHz.
Search tuning can best be done from low to high RF frequency. For search-
tuning-down, the IF-PLL will lock on the Sound Carrier. Just before the
Picture Carrier enters the SAW filter, it falls in the “neighbour” sound channel
trap of the SAW filter (-60dB). This will cause large jumps in the AGC.
Software should allow extra delay time to let this stabilize, before evaluating
Sync Lock and AFC information.
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Search-tuning speed:
Philips Semiconductors
(850-50)MHz / 0.8MHz x 30ms = 30s (no signals, no AGC jumps)
plus ~ 30 stations x 0.8s = 24s
• Avoid “large-signal” jump behaviour, keep it smooth
• Tuner AGC 10x slower than IF AGC (unless i-AGC can be used)
SL.AND.LOCK.AND.SID 4
AFC
Philips Semiconductors
SL=1 should not fail for longer than 300kHz
3. Read-out AFC (2-complement notation) and jump exact to center
Check IVWF=1 (needs >7 frames) else skip unwanted signal
4. Store in Eeprom, upon first recall: determine standard,
Auto-following, re-store in Eeprom (TV & tuner are warm)
SL.AND.LOCK.AND.SID 4
AFC
Philips Semiconductors
SL=1 should not fail for longer than 300kHz
3. Read-out AFC (2-complement notation) and jump exact to center
Check IVWF=1 (needs >7 frames) else skip unwanted signal
Check CD3..0=1,0,1,0 (=SECAM) else skip false lock
4. Store in Eeprom, upon first recall: determine standard,
Auto-following, re-store in Eeprom (TV & tuner are warm)
During a SECAM-L search, the system can sometimes give false lock on
Negative-modulated transmitters. Sensitivity for this is reduced by STM=1
plus an additional check for SECAM colour ident.
Make sure that before checking IVWF=1, the synchronisation has had at least
7 frames times stable signal (e.g. 160ms).
After IVWF=1 you can immediately demand that chroma should have
detected SECAM too (takes about 40ms).
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Program switching:
Long post-Mute
Automatic
Following
Station found, Start
Change sound & colour acq.
Horizontal-sync
SL tuning
Picture
stable
Philips Semiconductors
Vertical-sync IVW/F
Switch-On IF-calibration only
IF PLL calibration IFLF during channel-change
Audio pre-mute (soft) should be effective 40ms (~25Hz) before changing the
tuning. This avoid plops during program or source switching.
Video blanking (RBL=1) is postponed to the latest possible moment, to keep
the visible transition short. <300ms is experienced as “immediate response”
where as >350ms gives a “sticky” feeling of the remote control. If it takes
>350ms to lock on the new station, we advice to remove the picture blanking
(RBL=0). RBL-blanking is internally synchronised to the vertical-retrace. As
alternative SW can use a black OSD screen to blank the video. This has the
advantage that possible OSD will not blink.
As soon as SL=1 is found, the speed-up for vertical catching must be
disabled (NCIN=0), otherwise bits IVW and IVWF will not work.
Automatic following (AFC) should begin immediately after SL=1, to cancel
temperature effects in the tuning system.
Switch-On IF calibration (IFLH=0) after video blanking. Release it (IFLH=1)
after SL=1 and before un-blanking the video.
Fast settling of the AVL (auto-volume-leveling) after changing channel or
source, is achieved by setting AVLM=1 during the audio Mute period.
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minimal current
+
when HIGH
Output-B
Philips Semiconductors
• Always maintain 3.3VSTBY (needed for I/O pins & necessary for infrared receiver)
• Determine best output level for each I/O pin (advice to design for “low”)
• Carefully determine SW delays between switching power
circuits (take-over-time, avoid glitches …)
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Philips Semiconductors
• Expected life-time for Eeprom with 105 erase/write cycles:
– Average 10 refresh-overwrites per hour
– Average 3 hours per day = (105 / (10*3)) / 356 = 9.13 years
• After RESET, software reloads the backup-copy from Eeprom and the
TV continues as it was before
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III
UOC “Hercules”
Philips Semiconductors
Philips Semiconductors - BL Mainstream Tv Solutions