Embedded Processors

Nombres non entiers

signe exposant mantisse

 En base 2.
N = +- mantisse . 2 +-exposant
( les +- peuvent être obtenus soit signe et module ou complément à 2. )
 N= 1,1011001 x 2 -10011 => N = (1.20 +1.2-1 +1.2-3 +1.2-4+1.2-7 ).2-19
 Le nombre de digits dans la mantisse est appelé précision.

 Calcul en virgule flottant

Multiplication : m1.b e1 * m2 .b e2  m1.m2 .b ( e1 e2 )

Addition : m1.b e1  m2 .b e2  m1.b ( e1 e2 ) .b e2  m2 .b e2

 (m1.b ( e1 e2 )  m2 ).b e2 Si e2 > e1

Représentation en virgule flottante

Il existe des standards, comme la norme IEEE 754.

• La mantisse vaut toujours 1,xxxx et on ne stocke que xxxx

• L’exposant est biaisée afin qu’il soit toujours positif.

Biais = 2 (nombre de bit pour l’exposant biaisé -1)

Exposant biaisé = exposant réel + biais
En simple précision (float, 32 bits) s=1 bits e=8 bits m= 23bits
e = E + 127 et m = (M - 1)* 223 E et M exposant Mantisse non normalisés
Simple précision (b=2): (-1)S * (1 + M ) * 2(e-127)

En double précision (float, 64 bits) s=1 bits e=11 bits m= 52bits

double précision (b=2): (-1)S * (1 + M ) * 2(e-1023)

1
Exemple ce conversion
Exercice 1
Coder X= -54.625 en utilisant le mécanisme IEEE 754

Exercice 2
Coder X = +11,25 en utilisant le mécanisme IEEE 754

Exercice 3
Coder −118,625 en utilisant le mécanisme IEEE 754.

MULTIPLEXEUR 2 VERS 1
 Un opérateur booléen ternaire (c?a:b) en langage C
( simple exemple dans l’immédiat, puis primitive de base pour les BDD )

 Aussi appelé sélecteur défini par :

MUX(c , a, b ) = a si c = 1 c : Commande
MUX(c , a, b ) = b si c = 0 a et b : données multiplexées

c C : bus

A 3
a 1 S=A si c=3
= a si c = 1 B 2 S
S S=B si c=2
= b si c = 0
b 0 C 1 S =C si c=1
D 0 S =D si c=0

S = MUX(c,a,b) Extensions numériques

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Mémoire élémentaire

 Bascule synchrone : bascule D

Symbole Européen Explications

• Entrées :
➢ .........................................................................
D : état à mémoriser (Data)
D Q
➢ CLK : horloge de synchronisation
.........................................................................

/Q • Sorties :
CLK
➢ Q : sortie principale
.........................................................................
➢ /Q : sortie complémentée
.........................................................................

Table de vérité Modes de fonctionnement

CLK D Q(n) /Q(n)

0 X Q(n-1) /Q(n-1) État mémoire

1 X Q(n-1) /Q(n-1) État mémoire
 0 0 1 Mémorisation d'un état 0
 1 1 0 Mémorisation d'un état 1
6

2
Mémoire élémentaire
Déterminer tous
les fronts actifs de
 Bascule D : un exemple l'horloge
Déterminer les états sur D
pour tous les fronts
CLK

Q
Déterminez l'état des
sorties

/
Q

REGISTRES SIMPLES

REGISTRE A DÉCALAGE BIDIRECTIONNEL

Registre à décalage
si S=0, hold
si S=2, load
si S=1, Shift Left ( <<1 )
si S=3, Shift Right ( >>1 )

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 BANC DE REGISTRES
Exemple: 8 registres 32 bits

En sortie :
2 multiplexeurs
8 vers 1
Décodeur 1 parmi 8 un numériques (32 bits)
seul signal load à 1,
les autres à 0

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EXEMPLE D’ALU PUREMENT LOGIQUE

UAL : Unité Arithmétique et Logique

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BANC DE REGISTRES + ALU :

UN CHEMIN DE DONNÉES À TOUT FAIRE
Commande de l’ALU
Opération demandée
Etat de sortie

Commande du bancs
de registres

Piloter les signaux de L’algorithme prend

Dérouler un la forme
algorithme commande a chaque
pas du temps d’une séquence
d’instructions

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4
 MÉMOIRES

Memory 64Kb Memory 4Gb

Address 16bits Address 32bits

1 byte
0xFFFF 1 byte
216-1= 65535
232-1= 4294967295 0xFFFFFFFF

…
…
Continue : Data
…
0 0x0000

0 0x000000000

Adresses
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ES102
LECTURES & ECRITURES EN MÉMOIRE CM 10

https://www.youtube.com/watch?v=YrbVML_jO98
https://www.youtube.com/watch?v=te5Xe3TgPC4

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CHEMIN DE DONNEES 32 BITS + MEMOIRES

Commande de l’ALU
Opération demandée
Etat de sortie

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5
 CHEMIN DE DONNEES 32 BITS + MEMOIRES

RI: Registre d’Instruction

r: reg
d: dest.
s: source
t: source/dest.
Op: Code operatoire 32
Donnée écrite
Unité de Mémoire de
control
Valeur immédiate données
6 0
Registres Adresse
…….
1
RI Op rs rt rd ALU
lu2 Donnée lue
5
lu2 lu1
lu1
0 32
écrire
0 écrit 1
1

UAL: Unité Arithmétique et Logique

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CHEMIN DE DONNEES 32 BITS + MEMOIRES

PC: Registre d’adresse d’instruction (Program Counter )

PC
adresse -----------

Mémoire
d’instructions
4
0
+ 0
1
1
adresse 32
Instruction lue Donnée écrite

Mémoire de
Unité de 32
control
Valeur immédiate données
6 0
Registres Adresse
1
RI Op rs rt rd ……. ALU
lu2 Donnée lue
5
lu2 lu1
RI: Registre
d’Instruction lu1
r: reg
0 32
écrire
d: dest. 0 1
écrit
s: source 1
t: source/dest.
Op: Code UAL: Unité Arithmétique et Logique 17
operatoire

TYPES D’INSTRUCTION
 Opération sur les données :
– addition, soustraction, multiplication
– opérations logiques + versions immédiates
(valeur d’un opérande
– décalages, tournant ou pas dans instruction au lieu
 Transferts de données : d’être dans registre)
– de registre en registre ex : addi Rx Rx 1
incrémentation
– de registre vers mémoire (écriture, store) du contenu de Rx
de mémoire vers registre (lecture, load)
 Gestion de séquencement :
– branchements inconditionnels et conditionnels (jump, branch)
– appel et retour de sous-programme (call, return)

Total de ≈ 50 instructions = > code opératoire sur 6 bits

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 DEROULEMENT D’UNE INSTRUCTION
Exemple : addition des contenus des registres Rx et Ry et chargement
du résultat dans Rz
1. Chargement de l’instruction notée add Rz Rx Ry en langage
assembleur, de la mémoire vers le registre d’instruction (RI)
2. Décodage de l’instruction :
 Reconnaissance de l’instruction «add» dans le RI, dont le format
comporte 3 numéros de registres
 Numéros x et y pour sélection en lecture des registres Rx et Ry
 Numéro z pour sélection en écriture du registre Rz
3. Exécution de l’instruction
 Sélection en lecture de Rx et Ry et aiguillage vers ALU
 Configuration ALU pour addition
 Aiguillage du résultat vers Rz, autorisé en écriture

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CHEMIN DE DONNEES 32 BITS + MEMOIRES

PC: Registre d’adresse d’instruction (Program Counter ) PC = PC + 4 (Octets)
add $t0, $s1, $s2 ( $t0 = $s1 + $s2)
PC addi $t0, $s1, 7 ( $t0 = $s1 + 7 )
adresse ----------- lw $t0, 24($s1) ( $t0 <-- [$s1 + 24 ]
sw $t0, 24($s1) ( $t0  [$s1 + 24 ]
Mémoire j Loop
d’instructions beq $s1, $s2, -5 (Si $s1 = $s2 alors
4
0
+ 0 pc =pc -20)
1
1
adresse 32
Instruction lue Donnée écrite

Mémoire de
Unité de 32
control
Valeur immédiate données
6 0
Registres Adresse
1
RI Op rs rt rd ……. ALU
lu2 Donnée lue
5
lu2 lu1
RI: Registre
d’Instruction lu1
r: reg
0 32
écrire
d: dest. 0 1
écrit
s: source 1
t: source/dest.
Op: Code UAL: Unité Arithmétique et Logique 20
operatoire

IF THEN ELSE
Compilateur C Code assembleur
.c .asm

Etiquette représentant
l’adresse de l’instruction

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SOUS-PROGRAMMES

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Hierarchy of Computation

Programming in Compiler/Assembler/
Problem Algorithms
High-Level Language Linker

Instruction Set Architecture (ISA) Binary

Target Machine
Micro-architecture
(one implementation)
System architecture
Functional units/
Building blocks

Gates Level
Design

Transistors Manufacturing
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Hierarchy of Computation

Programming in Compiler/Assembler/
Problem Algorithms
High-Level Language Linker

Instruction Set Architecture (ISA) Binary

Target Machine
Micro-architecture
(one implementation)
System architecture
Functional units/ Human Level
Building blocks
System Level

Gates Level RTL Level

Design Logic Level
Circuit Level
Transistors Manufacturing
Silicon Level
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8
 Hierarchy of Computation

Programming in Compiler/Assembler/
Problem Algorithms
High-Level Language Linker

Instruction Set Architecture (ISA) Binary

Target Machine
Micro-architecture
(one implementation)
System architecture
Functional units/ Human Level
Building blocks
Our Focus System Level

Gates Level RTL Level

Design Logic Level
Circuit Level
Transistors Manufacturing
Silicon Level
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Abstraction Layers

Application
Software

Compiler
Operating System
Assembler
Linker Loader Scheduler Device Drivers
Instruction Set Architecture (Interface SW/HW)
Processor Memory I/O System
Hardware

Datapath & Control Design

Digital Logic Design
Circuit Design
Physical (IC Layout) Design

 Abstraction hides implementation details between levels

 Helps us cope with enormous complexity
 ISA is at the interface between software and hardware
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Classes of Computers
 Desktop / Notebook Computers
 General purpose, variety of software
 Subject to cost/performance tradeoff
 Server Computers
 Network based
 High capacity, performance, reliability
 Range from small servers to building sized
 Embedded Computers
 Hidden as components of systems
 Stringent power/performance/cost constraints

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9
The Processor Market
Millions of Units

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Processor
General Concepts

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Address Space

Address space of a processor depends on its address

decoding mechanism
• size will depend on the number of address bit used

Depending on the processor design, there may be two types

of address space
• one is used by normal memory access
• another one is reserved for I/O peripheral registers
(control, status, and data)
• need extra control signal or special means of accessing
the alternate address space

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10
 Address Space

Refer to the range of address that can be accessed by the

processor determined by the number of address bit utilized in the
processor architecture.
Some processor families (e.g. ARM) utilize only one address space
for both memory and I/O devices
• i.e. everything is mapped in the same address space

0xFFFFFFFF
I/O Reg
I/O
I/O Reg

Processor
Data
Memory
Code
0x00000000

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Memory Mapped vs I/O Mapped

Some processor families have two address spaces.

E.g. For the x86 processor, memory and I/O devices can be
mapped in two different address spaces:
• memory address space and I/O address space

0xFFFF
0xFFFFFFFF
I/O Reg
Data
Code
Processor
Data
I/O Reg
0x0000 Code
0x00000000
I/O Address Memory
Space Address
Space

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Memory System Architectures

Two types of information are found in a typical program

code:
i) Instruction codes for execution
ii) Data that is used by the instruction codes

Two classes of memory system design to store

these informations:
i. von Neumann architecture
ii. Harvard architecture

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 von Neumann Architecture

The von Neumann architecture utilizes only one memory bus

for both instruction fetching and data access
• simplifies the hardware and
FFFFh
glue logic design Data
Table
• code and data located
in the same address space Data

Processor Code

Single path (bus) Data

for both Code &
Data Code
0000h

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Von Neumann Vs. Harvard Architecture (1/2)

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Von Neumann Vs. Harvard Architecture (2/2)

 Harvard can’t use self-modifying code.

 Harvard allows two simultaneous memory fetches.

 Most DSPs use Harvard architecture for streaming data:

 greater memory bandwidth;

 more predictable bandwidth.

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CISC Vs. RISC
CISC RISC
Rich instruction set Simple instruction set

• Emphasis on HW • Emphasis on SW / Compiler

• Simple SW, complex HW • Simple HW, complex SW
• Provide as many instructions as • Faster, smaller
needed • Provide most common instructions and
• Instructions range from simple to addressing modes
very complex • “Solve the common case fast”

MUL <addr1>, <addr2> LOAD R1, <addr1>

LOAD R2, <addr2>
MUL R2, R1
STORE R2, <addr1>
CISC Examples:
Intel Pentium 4 RISC Examples
AMD K5, K6, K7, Opteron MIPS R2000-R14000
Sun Sparc, UltraSPARC, Sunfire, HP PA-RISC,
IBM Power PC, ARM Processors 37

Extension of the RISC rules

 High code density, low power, and small die size
 Variable cycle execution
 Multiple load and store
 Improve code density, reduce Ifs, and reduces overall
power consumption
 Inline barrel shifter
 Conditional execution
 16-bit Thumb instruction set
 Enhance DSP instructions
 16X16 multiply, arithmetic saturation
 DSP-specific routines

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Design for Low Power Consumption

 Where does the power go?

• Switching power
The is the power dissipated by
charging and discharging the gate
output capacitance CL.
The energy per output transition is:

• Short-circuit power
• Leakage power.

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13
Low Power Circuit Design

 Minimize the power supply voltage

 Minimize the circuit activity

 Minimize the number of gates

 Minimize the clock frequency

Low-power Strategies

 Minimize Vdd

 Minimize off-chip activity

 Minimize on-chip activity.

 Exploit parallelism
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CPU performance equation

The Performance Equation
The performance equation analyzes execution time as a product of
three factors that are relatively independent of each other
Prog Excut time = IC x CPI x CT
 IC : instruction count , :can be reduced by adding more powerful
instructions to the instruction set. However, this can increase either
CPI or clock time, or both
 CPI : clocks per instruction : can be reduced by exploiting more
instruction-level parallelism. If they add more complex instructions it
often increases CPI.
 CT : clock time : depends on transistor speed and the complexity of
the work done in a single clock. Clock time can be reduced when
transistor sizes decrease ( heat will increase)

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UC Performance

Problem Statement
Suppose a program (or a program task) takes 1 billion instructions
to execute on a processor running at 2 GHz. Suppose also that
50% of the instructions execute in 3 clock cycles, 30% execute in 4
clock cycles, and 20% execute in 5 clock cycles. What is the
execution time for the program or task?

42

14
Solution :
instruction count = 109

The clock time =0.5×10-9 seconds

CPI = ( 50 x 3 + 30 x 4 + 20 x 5 ) /100 = 3,7

Then we have execution time = 1.0×109 × 3.7 × 0.5×10-9 sec = 1.85

sec.

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CPU performance Improvements

CPU performance Improvements can be achieved by :

 Increasing the clock frequency

 Simplify decoding and executing instructions (RISC)

 Execute multiple instructions "simultaneously" with:

 Temporal parallelism (pipeline)

 Spatial parallelism (superscalar, VLIW)

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instruction-level parallelism
A simple example
 Because steps 1 and 2 of the sequential operation are independent
of each other, a processor employing instruction-level parallelism can
run instructions 1.A. and 1.B. simultaneously and thereby reduce the
operation cycles to complete the operation by 33%.
 The last step must be executed sequentially in either case, however,
as it is dependent on the two prior steps.

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Thread-Level Parallelism
Thread-level parallelism (or TLP), involves executing individual task
threads delegated to the CPU simultaneously

A conceptual visualization of thread-level parallelism

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