VLSI DESIGN PROCESS

VLSI DESIGN PROCESS

VLSI DESIGN PROCESS
VLSI DESIGN PROCESS
VLSI DESIGN PROCESS
MOS
Transistor
 Field Effect Transistors
JFET MOSFET CMOS
 How a JFET transistor works?
When the gate is negative ,it repels
the electron in the N-channel. So
there is no way for electrons to flow
from source to drain.
When the negative voltage is
removed from Gate ,the
electrons can flow freely from
source to drain .so the transistor
is on.
 How a MOSFET Transistor works?

In MosFET, the Gate is insulated from p-channel or n-

channel. This prevents gate current from flowing, reducing
power usage.

When the Gate is positive voltage ,it allows

electrons to flow from drain to source .In this
case transistor is on.
Introduction to
CMOS VLSI
Design

Slide 10
 Introduction
Integrated circuits: many transistors on one
chip.
Very Large Scale Integration (VLSI): very
many
Complementary Metal Oxide Semiconductor
Fast, cheap, low power transistors
Today: How to build your own simple CMOS
chip
CMOS transistors
Building logic gates from transistors
Transistor layout and fabrication
Slide 11
MOS TRANSISTOR

Slide 12
MOS TRANSISTOR

Slide 13
MOS TRANSISTOR

Slide 14
Basic MOSFET Characteristics

Slide 15
 Basic MOSFET Characteristics
The circuit symbol for an n-channel MOSFET (nFET
or nMOS) is shown in Figure.
The MOSFET is a 4-terminal device with the
terminals named the gate, source, drain, and bulk.
The device voltages are shown in Figure. In general,
the gate acts as the control electrode.
The value of the gate-source voltage is used to
control the drain current that flows through the
device from drain to source. The actual value of is
determined by both source and the drain.

Slide 16
 nMOS Transistor

Four terminals: gate, source, drain, body

Gate – oxide – body stack looks like a capacitor
Gate and body are conductors
SiO2 (oxide) is a very good insulator
Called metal – oxide – semiconductor (MOS)
capacitor
Even though gate is
no longer made of metal
Slide 17
 nMOS Operation
Body is commonly tied to ground (0 V)
When the gate is at a low voltage:
P-type body is at low voltage
Source-body and drain-body diodes are
OFF
No current flows, transistor is OFF

Slide 18
 nMOS Operation Cont.
When the gate is at a high voltage:
Positive charge on gate of MOS capacitor
Negative charge attracted to body
Inverts a channel under gate to n-type
Now current can flow through n-type
silicon from source through channel to
drain, transistor is ON

Slide 19
 nmos enhancement transistor operation

Mode of operation depends on Vg, Vd, Vs

Vgs = Vg – Vs
Vgd = Vg – Vd
Vds = Vd – Vs = Vgs - Vgd
Source and drain are symmetric diffusion terminals
By convention, source is terminal at lower voltage
Hence Vds 0
nMOS body is grounded. First assume source is 0 too.
Three regions of operation
Cutoff
Linear
Saturation
Slide 20
 nMOS Cutoff
No channel
Ids = 0

Slide 21
 nMOS Linear
Channel forms
Current flows from d to s
e- from s to d
Ids increases with Vds
Similar to linear resistor

Slide 22
 nMOS Saturation
Channel pinches off
Ids independent of Vds
We say current saturates
Similar to current source

Slide 23
V-I characterstics of nmos transistor

Slide 24
 pMOS Transistor
Similar, but doping and voltages
reversed
Body tied to high voltage (VDD)
Gate low: transistor ON
Gate high: transistor OFF
Bubble indicates inverted behavior

Slide 25
 Power Supply Voltage
GND = 0 V
In 1980’s, VDD = 5V
VDD has decreased in modern
processes
High VDD would damage modern tiny
transistors
Lower VDD saves power
VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …
Slide 26
 Transistors as Switches
We can view MOS transistors as
electrically controlled switches
Voltage at gate controls path from
source to drain

Slide 27
V-I characterstics of pmos transistor

Slide 28
Vgs vs ids characterstics for nmos

Slide 29
Vgs vs ids characterstics for pmos

Slide 30
 Threshold Voltage

Threshold Voltage:The threshold voltage of a MOS Transistor

can be defined as the voltage applied between the gate and the
source of an MOS device below which the drain to source
current Ids effectively drops to zero.
The threshold voltage of a MOS transistor depends on the
number of parameters.
i)Gate conductor material
ii)Gate insulating material
iii)Gate insulation thickness(channel doping)
iv)Impurities at the silicon insulator interface
v)voltage between the source and the substrate.Vsb.
In addition the absolute value of threshold voltage decreases
with increase in tempature this is app -4 mv/oc for high
substrate doping and -2mv/oc for low substrate doping.

Slide 31
 Calculation of Ids ( MOS Device design equation)

The whole idea of a MOS transistor is to use a voltage on the

gate to induce a charge into the channel region between the
source and drain so that current can flow under the influence of
the electric field created by the voltage applied between the
two.
Since the charge induced depends on the voltage applied to
the gate Vgs, then the current between the source and drain Ids
will depend Vgs and the voltage applied between the source
and drain, Vds.

The transit time is given as:

The velocity is then defined as:

where μ is the electron/hole mobility

and Eds is the electric field applied across the source and
drain

The electric field is given as the voltage over the channel

length,

All this can be used to define the transit time in the source
drain region,

As stated before charge is induced in the channel due to gate

voltage Vgs Slide 33
The voltage drop along the channel though is linear with
distance x from the source (due to the IR drop in the channel).
Assuming then
that the device is unsaturated, the average voltage drop along
the channel will be,

Since there is a threshold voltage (Vt) required to invert the

charge under the gate, this means that the effective gate
voltage is,

Given that charge per unit area is Eg εins εo

The induced charge in the channel is then,

where Eg is the average E field gate to channel, εins is the

relative permittivity of the gate insulator, εo is the
Slide 34
permittivity of free space, W is the width of the gate and L
The average electric field Eg (from the gate to the channel) can be
defined in terms of the voltage drop across the insulating oxide and
its thickness;

So the induced charge can be defined as,

and the drain source current therefore defined as,

Slide 35
This equation can also be written as (Linear region)

Cox is the capacitance per unit

where area of the oxide
Saturation begins when Vds = Vgs – Vt since the IR drop in the
channel now equals the effective gate to channel voltage at the
drain and the current remains fairly constant as Vds increases
further. Therefore,

These expressions of current are valid for both depletion and

enhancement mode devices . Slide 36
 nMOS I-V Summary

Shockley 1st order transistor models

= K W/L is called device transconductance
Vdsat =Vgs - Vt

Slide 37
 Body effect

The body effect describes the changes in the threshold

voltage by the change in VSB, the source-bulk voltage. Since
the body influences the threshold voltage (when it is not tied to
the source), it can be thought of as a second gate, and is
sometimes referred to as the "back gate"; the body effect is
sometimes called the "back-gate effect".[1]
For an enhancement mode, n-mos MOSFET body effect upon
threshold voltage is computed according to the Shichman-
Hodges model (accurate for very old technology) using the
following equation.

Slide 38
 Body effect
where VTN is the threshold voltage when substrate
bias is present, VSB is the source-to-body substrate
bias, 2φF is the surface potential, and VTO is
threshold voltage for zero substrate bias, is the body
effect parameter, tox is oxide thickness, εox is oxide
permitivity, εsi is the permitivity of silicon, NA is a
doping concentration, q is the charge of an electron.

Slide 39
 CMOS Inverter Cross-section
Typically use p-type substrate for
nMOS transistors
Requires n-well for body of pMOS
transistors

Slide 40
 DC Response
of CMOS inverter
 DC Response
DC Response: Vout vs. Vin for a gate
Ex: Inverter
When Vin = 0 -> Vout = VDD
When Vin = VDD -> Vout = 0
In between, Vout depends on
transistor size and current
By KCL, must settle such that
Idsn = |Idsp|
We could solve equations
But graphical solution gives more insight

Slide 42
 Transistor Operation
Current depends on region of transistor
behavior
For what Vin and Vout are nMOS and
pMOS in
Cutoff?
Linear?
Saturation?

Slide 43
 nMOS Operation
Cutoff Linear Saturated
Vgsn < Vgsn > Vgsn >

Vdsn < Vdsn >

Slide 44
 nMOS Operation
Cutoff Linear Saturated
Vgsn < Vtn Vgsn > Vtn Vgsn > Vtn

Vdsn < Vgsn – Vtn Vdsn > Vgsn – Vtn

Slide 45
 nMOS Operation
Cutoff Linear Saturated
Vgsn < Vtn Vgsn > Vtn Vgsn > Vtn

Vdsn < Vgsn – Vtn Vdsn > Vgsn – Vtn

Vgsn = Vin
Vdsn = Vout

Slide 46
 nMOS Operation
Cutoff Linear Saturated
Vgsn < Vtn Vgsn > Vtn Vgsn > Vtn
Vin < Vtn Vin > Vtn Vin > Vtn
Vdsn < Vgsn – Vtn Vdsn > Vgsn – Vtn
Vout < Vin - Vtn Vout > Vin - Vtn

Vgsn = Vin
Vdsn = Vout

Slide 47
 pMOS Operation
Cutoff Linear Saturated
Vgsp > Vgsp < Vgsp <

Vdsp > Vdsp <

Slide 48
 PMOS Operation
Cutoff Linear Saturated
Vgsp > Vtp Vgsp < Vtp Vgsp < Vtp
Vin > VDD + Vtp Vin < VDD + Vtp Vin < VDD + Vtp
Vdsp > Vgsp – Vtp Vdsp < Vgsp – Vtp
Vout > Vin - Vtp Vout < Vin - Vtp
Vgsp = Vin - VDD
Vdsp = Vout - VDD
Vtp < 0

Slide 49
 pMOS Operation
Cutoff Linear Saturated
Vgsp > Vtp Vgsp < Vtp Vgsp < Vtp

Vdsp > Vgsp – Vtp Vdsp < Vgsp – Vtp

Slide 50
 pMOS Operation
Cutoff Linear Saturated
Vgsp > Vtp Vgsp < Vtp Vgsp < Vtp

Vdsp > Vgsp – Vtp Vdsp < Vgsp – Vtp

Vgsp = Vin - VDD Vtp < 0

Vdsp = Vout - VDD

Slide 51
 I-V Characteristics

Make pMOS is wider than nMOS such

that n = p

Slide 52
Current vs. Vout, Vin

Slide 53
 Load Line Analysis

For a given Vin:

Plot Idsn, Idsp vs. Vout
Vout must be where |currents| are equal in

Slide 54
 Load Line Analysis
Vin = 0

Slide 55
 Load Line Analysis
Vin = 0.2VDD

Slide 56
 Load Line Analysis
Vin = 0.4VDD

Slide 57
 Load Line Analysis
Vin = 0.6VDD

Slide 58
 Load Line Analysis
Vin = 0.8VDD

Slide 59
 Load Line Analysis
Vin = VDD

Slide 60
Load Line Summary

Slide 61
 DC Transfer Curve
Transcribe points onto Vin vs. Vout plot

Slide 62
 Operating Regions
Revisit transistor operating regions
Region nMOS pMOS
A
B
C
D
E

Slide 63
 Operating Regions
Revisit transistor operating regions
Region nMOS pMOS
A Cutoff Linear
B Saturation Linear
C Saturation Saturation
D Linear Saturation
E Linear Cutoff

Slide 64
 Beta Ratio

If p
/ n
1, switching point will move from VDD/2
Called skewed gate
Other gates: collapse into equivalent inverter

Slide 65
 Noise Margins
How much noise can a gate input see before it does not
recognize the input?

Slide 66
 Logic Levels
To maximize noise margins, select
logic levels at

Slide 67
 Logic Levels

To maximize noise margins, select

logic levels at
unity gain point of DC transfer
characteristic

Slide 68
 Noise Margins
Noise Margins As mentioned earlier, digital circuits are robust
to noise. The degree of robustness is quantised as noise
margins. Noise margins allow us to estimate the allowable
values at the input of an inverter for which the output can still
be correctly resolved.
To estimate the noise margins we need to first calculate 4
important points for the static (transfer) characteristics of
the inverter.
1. VIL
2. VIH
3. VOL
4. VOH
Slide 69
 Noise Margin Definitions...
VIL and VIH are the two points on the input
axis where the small-signal gain of the
transfer function is at unity. These are
chosen as the defining points for the
forbidden or transition region of operation of
the circuit.

Slide 70
 Noise Margin Definitions...

If the circuit is operated in the high impedance

region, then any random noise picked up at the input
of the circuit would get amplified at the output and
give an erroneous result.
VOL and VOH are the outputs of the inverter when
the inputs are ‘1’ and ‘0’ respectively. Arranging
everything on a common axis, we have,

Slide 71
 Noise Margin Definitions...

The Noise Margins are therefore very clearly

defined by
1. NMH = VOH − VIH
2. NML = VIL − VOL

Slide 72
CMOS Inverter

Slide 73
 CMOS Inverter

A Y
0
1

Slide 74
 CMOS Inverter

A Y
0
1 0

Slide 75
 CMOS Inverter

A Y
0 1
1 0

Slide 76
 CMOS NAND Gate
A B Y
0 0
0 1
1 0
1 1

Slide 77
 CMOS NAND Gate
A B Y
0 0 1
0 1
1 0
1 1

Slide 78
 CMOS NAND Gate
A B Y
0 0 1
0 1 1
1 0
1 1

Slide 79
 CMOS NAND Gate
A B Y
0 0 1
0 1 1
1 0 1
1 1

Slide 80
 CMOS NAND Gate
A B Y
0 0 1
0 1 1
1 0 1
1 1 0

Slide 81
 CMOS NOR Gate
A B Y
0 0 1
0 1 0
1 0 0
1 1 0

Slide 82
 3-input NAND Gate

Y pulls low if ALL inputs are 1

Y pulls high if ANY input is 0

Slide 83
 Compound Gates

Compound gates can do any inverting function

Ex:

Slide 84
Example: O3AI

Slide 85
 Signal Strength

Strength of signal
How close it approximates ideal voltage source
VDD and GND rails are strongest 1 and 0
nMOS pass strong 0
But degraded or weak 1
pMOS pass strong 1
But degraded or weak 0
Thus nMOS are best for pull-down network

Slide 86
CHANNE LENGTH MODULATION
Subthreshold Conduction
 Inverters
Vd
Basic requirement for
d
producing a complete range of
Logic circuits
R

1 0 Vo

0 1

Vs
s
 Vd
d Basic Inverter: Transistor with
source
connected to ground and a load
R Pull- resistor
Up
Vo connected from the drain to the
Output is taken from the drain and
positive
control
Supply rail
input connected between gate and
Resistors
ground are not easily formed in
Vin silicon
Pull
Down they occupy too much area
Transistors can be used as the pull-up
Vs device
s
PMOS STATIC LOAD
Depletion mode pull up
 CMOS Inverter
Ideally there is no static power
dissipation.
When input is fully is high or fully low, no
current path between VDD and GND
exists (the output is usually tied to the
gate of another MOS transistor which has
a very high input impedance).
Power is dissipated as "In" transitions
from 0→1 and 1 → 0 and a momentary
current path exists between Vdd and
GND.
Power is also dissipated in the charging
and discharging of gate capacitances.
 CMOS Properties
Full rail-to-rail swing
Symmetrical VTC
Propagation delay function of load
capacitance and resistance of transistors
No static power dissipation (ignoring
leakage current)
Direct path current during switching
 Pass Transistors
Transistors can be used as switches
The switching characteristics of a MOS transistor
that can be used as a switch which gives degraded
output is called Pass Transistors

Slide 97
 The nMOS & pMOS pass transistor
Vdd (signal
Vdd (signal input)
input)
5V Sourc
nMO 0V
charges to pMO
e
S V -V (bad 1) charges to
dd th nMOS S Vdd (good 1)

discharges to discharges to
5V 0V pMO |Vth pMOS| (bad 0
nMO GND (good 0)
SSourc S
GNDe(signal input) GND (signal input)

N channel pass Tx P channel pass Tx

passes a bad passes a

1
passes a bad 0 a
passes
 CMOS Buffer Gate

X Z
VDD
L L Logic
H H Symbol

Truth Circuit
Table Diagram

CMOS Buffer converts Logic LOW input

Voltage to 0 Volt and Logic HIGH input Z
voltage to 5.0 Volt (Regenerating weak
digital signals) Buffer gives higher X
current drive and hence increased Fan-
out. (Note: Circuit is two CMOS inverters
in Cascade)
 Three State Buffer

EN
OU VDD
A T

Logic
EN A Nmos Pmos OUT
Symbol EN
L L off off Hi-Z Pmos
L H off off Hi-Z OUT
H L on off L
H H off on H A
Nmos

Truth Circuit
Table Diagram
*Hi-Z = High Impedance state
(No connection to H or L
(floating))
 Transmission Gates

Pass transistors produce degraded outputs

Transmission gates pass both 0 and 1 well
TG can be used as switch which gives
complete voltage level. It is a parallel
connection of nmos and pmos transistor

Slide 101
 Transmission Gate
A transmission gate is an electronic
element. It is a good non-mechanical relay,
built with CMOS technology. Sometimes
known as an analog gate, analogue switch or
electronic relay depending on its use. It is
made by the parallel combination of an
nMOS and a pMOS transistor with the input
at the gate of one transistor being
complementary to the input at the gate of the
other.

Slide 102
Transmission Gate

Slide 103
 Transmission Gate
operation:
The operation can also be understood this way: when the gate
input to the nMOS transistor is '0',and the complementary '1' is
gate input to the pMOS, both are turned off. However when
gate input to the nMOS is '1' and its complementary '0' is the
gate input to the pMOS, both are turned on and passes any
signal '1' or '0' equally well without degradation. The use of
transmission gates eliminates the undesirable threshold
voltage effects which give rise to loss of logic levels in pass
transistors.
The above logic was invented as a solution to problems of
earlier cmos logics.It provides with a less no. of transistors
needed for the implementation of a particular logic.
Slide 104
 Transmission Gate Mux
Nonrestoring mux uses two
transmission gates
Only 4 transistors

Slide 105
CMOS TRANSMISSION GATE

Slide 106
 Compare behaviour of CMOS TG with nMOS & pMOS pass gate

Gate
outputs

Logic level CMOS nMOS pMOS

TG pass TX pass TX
0 0 0 (good) |Vth pMOS| (bad)
1 1 Vdd-Vth nMOS 1 (good)
(bad)
 TG as a tristate buffer
Inverting tristate buffer : just add inverter

Other TG, tristate buffer electrical s

symbols :
ASB
010
111
A (Vin B (Vout
X0Z ) )

s s s
A B A B
A B s
s s
Logic circuit implementation using cmos TG

Slide 109
 Logic circuit implementation using CMOS
TG

A C Xnor
001
010
100
111

Xnor Truth
Table
4:1 Mux using TG

Slide 111
Capacitance estimation
Diffusion capacitance
Gate capacitance
Gate capacitance
Diffusion capacitance
Diffusion capacitance
Diffusion capacitance
mos capacitance
Resistance estimation
capacitance example
capacitance example
Wire Resistance
 Sheet resistance

Rs is then the sheet resistance. Because it is multiplied

by a dimensionless quantity, the units are ohms. The
term ohms/square is sometimes (but not universally)
used because it gives the resistance in ohms of current
passing from one side of a square region to the
opposite side, regardless of the size of the square. For
a square, L = W. Therefore, R = Rs for any size square.
Typical sheet resistance values for materials
are very well characterized
Layer Rs (Ohm / Sq)
Aluminium 0.03
N Diffusion 10 – 50
Silicide 2–4
Polysilicon 15 - 100
N-transistor Channel 104

P-transistor Channel 2.5 x 104

Typical Sheet Resistances for 5µm

Technology
Contact resistance
Capacitance
 N-type Minimum Feature
Polysilico Device
L
n
N-
diffusion

2 W
λ

2
λ

R = 1sq x Rs = Rs = 104
Ώ
 Polysilico W=
n 8λ

L=
2λ

N-
diffusion
R = Z Rs
R = (L/W) *
Rs
R = 4 104 Ώ
Area Capacitance of Layers
Conducting layers are separated from each other
by insulators (typically SiO2)
This may constitute a parallel plate capacitor, C =
є0єox A / D (farads)
D = thickness of oxide, A = area,
єox = 4 F/µm2
Area capacitance given in pF/µm2

Standard unit for a technology node is the gate -

channel capacitance of the minimum sized
transistor (2λ x 2λ), given as �Cg
This is a ‘technology specific’ value
 CMOS Inverter Delay
Pull-down delay = Rpd x 2 �Cg
Pull-up delay = Rpu x 2�Cg
Asymmetry in rise and fall due to resistance difference
between pull-up and pull-down (factor of 2.5) (due to
motilities of carriers)
Delay through a pair of inverters is 2 τ (fall time) + 5 τ
(rise time)
Delay through a pair of CMOS inverters is therefore 7 τ
Asymmetry can be improved by reducing resistance of
pull - up
Reduce resistance of pull - up by increasing channel
width
( typically by a factor of 2.5)
 CMOS Power Dissipation
Power dissipation in CMOS circuits comes from
two components i.e. Ptotal = Pstatic + Pdynamic
Static dissipation due to:
subthreshold conduction through OFF transistors
tunneling current through gate oxide
leakage through reverse-biased diodes
contention current in ratioed circuits
Dynamic dissipation due to:
charging and discharging of load capacitances
short circuit current while both PMOS and NMOS
networks are partially ON
Ratioed circuits (e.g. pseudo NMOS) have more
static dissipation.
 Dynamic Power Dissipation
Dynamic power is required to charge and discharge
load capacitances when transistors switch.
One cycle involves a rising and falling output.
On rising output, charge Q = CVDD is required
On falling output, charge is dumped to GND
This repeats Tfsw times over an interval of T
 Power and Energy
Power is drawn from a voltage source attached to
the VDD pin(s) of a chip.

Instantaneous Power:

Energy:

Average Power:
Dynamic Power Cont.
 Activity Factor
Suppose the system clock frequency = f
Let fsw = af, where a = activity factor
If the signal is a clock, a = 1
If the signal switches once per cycle, a = ½
Dynamic gates:
Switch either 0 or 2 times per cycle, a = ½
Static gates:
Depends on design, but typically a = 0.1

Dynamic power:
 Short Circuit Current
When transistors switch, both nMOS and pMOS
networks may be momentarily ON at once
Leads to a blip of “short circuit” current.
< 10% of dynamic power if rise/fall times are
comparable for input and output
 Low Power Design
Reduce dynamic power
: clock gating, sleep mode
C: small transistors (esp. on clock), short wires
VDD: lowest suitable voltage
f: lowest suitable frequency
Reduce static power
Selectively use ratioed circuits
Selectively use low Vt devices
Leakage reduction:
stacked devices, body bias, low temperature
Switching characterstics
Switching characterstics
Fall time
Rise time
CMOS Inverter Rise and Fall Time
Estimation
Tf ~ 3CL / βVDD
Τr ~ 3CL / βvdd
So, τ r/ τf = βn/βp
Given that (due to mobilities) βn = 2.5 βp, rise time is
slower by a factor of 2.5 when using minimum
dimensions of n and p transistors