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Once this data is known, corrective actions can be taken in order to ensure that every load is supplied
with power that is within the acceptable limits of operation. Such actions can include the calculation of:
A properly built load flow model of the system, lays a solid foundation for other important studies such
as short circuit, motor starting, harmonic and transient stability. The load flow model constitutes the
basic network information and the initial steady-state condition which these studies rely upon.
Notes:
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Page LF.1
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master
`~å~Ç~= AC Load Flow Analysis
P − jQ
I=
V∗
When a load of rated “P” (kW), “Q” (kVAR) and “V” (Voltage) is entered, the program calculates the
equivalent current “I” and defines the load as a constant draw of “I” (Amps).
Notes:
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Page LF.2
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master
`~å~Ç~= AC Load Flow Analysis
V2
Z=
P − jQ
P = Load Active Power (kW)
Q = Load Reactive Power (kVAR)
V = Load Rated Voltage
Z = Load equivalent constant Impedance
When a load of a rated “P” (kW), “Q” (kVAR) and “V” (Voltage) is entered, the program calculates the
equivalent impedance “Z” and defines the load as a constant shunt impedance of “Z” (Ohms).
Notes:
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Page LF.3
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master
`~å~Ç~= AC Load Flow Analysis
The Swing bus is the only bus at which the power is not specified. Net power flows cannot be fixed in
advance at every generating bus, since the network power losses are not known until the study has
been completed. The Swing bus is therefore defined based solely on voltage and angle, leaving the
rest of the variables (kW & kVAR, including system losses) free to adjust (SWING) to the requirements
of the network. In other words, Active and Reactive Power are the unknown variables of the Swing
bus.
In light of the above, a Load Flow Analysis is not mathematically feasible (by computer, by hand, or
otherwise) without the presence of a Swing bus or busses in the network. The Swing bus designation is
bestowed upon the stiffest busses in the network, traditionally Power Company or Utility busses.
The table below summarizes the critical variables for each type of bus:
Notes:
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Page LF.4
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master
`~å~Ç~= AC Load Flow Analysis
Step 1.
Proceed to open
the file EDM7.axd”
Step 2.
Run a Load Flow Connectivity
Error Check”, and correct any
problems as required.
Notes:
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Page LF.5
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master
`~å~Ç~= AC Load Flow Analysis
Notes:
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Page LF.6
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master
`~å~Ç~= AC Load Flow Analysis
Generator Model
Generator Full
Rating in kVA.
Generator Type.
Generator Load
Flow set-points.
Notes:
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Page LF.7
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master
`~å~Ç~= AC Load Flow Analysis
Utility Model
Calculated SC
Short Circuit Levels. Impedance values.
Notes:
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Page LF.8
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master
`~å~Ç~= AC Load Flow Analysis
4.1 Running the Load Flow & the Load Flow Options Screen
Step 1.
Invoke the Load Flow
program by selecting either
of these commands.
Step 2.
Select the scenario to be
analyzed.
Step 3.
Select the calculation
method.
Step 4.
Verify the “Scenario” to
be studied (Normal).
Step 5.
Select the rest of the
options.
Refer to steps
6a & 6b in the
next page.
Step 6.
Select “OK”.
Notes:
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Page LF.9
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master
`~å~Ç~= AC Load Flow Analysis
Step 6a.
Fine-tune the
advanced options as
needed.
Step 7.
Here the program is letting the user know that there is a
dead island caused by the “Normal” scenario configuration.
This scenario calls for BKR-2 to be opened, which isolates
the generator from the system. Select “Yes” to initiate the Step 6b.
analysis. Select “OK”.
Notes:
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Page LF.10
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master
`~å~Ç~= AC Load Flow Analysis
Step 1.
Verify that the analysis
has converged.
Step 2.
To view the results, select the
desired output format from the
“Results” menu.
Select “TD LoadFlow Format 1”
Step 3.
Select the desired
report sections and
options to be displayed.
Step 4.
Select “OK”.
Notes:
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Page LF.11
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master
`~å~Ç~= AC Load Flow Analysis
Notes:
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Page LF.12
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master
`~å~Ç~= AC Load Flow Analysis
Step 1.
Open the file named
“EDM8.axd”.
Step 2.
Model this load as a
“Constant kVA” load.
Notes:
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Page LF.13
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master
`~å~Ç~= AC Load Flow Analysis
Step 3.
Run the load flow analysis,
and verify that in this case
it does NOT converge.
Step 4.
View the report. The results, which in cases of non-
convergence ARE NOT TO BE RELIED UPON, seem to indicate
that the losses are too great. The system is not able to supply
750 kVA to the load.
Notes:
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Page LF.14
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master
`~å~Ç~= AC Load Flow Analysis
Step 1.
Open the file named
“EDM8.axd”.
Step 2. Step 3.
Model this load as a Run the load flow analysis, and
“Constant Impedance” verify that in this case it DOES
load. converge.
Notes:
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Page LF.15
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master
`~å~Ç~= AC Load Flow Analysis
Step 4.
View the report. The results confirm that due to the high
losses in the transformer and the line, the system is only able
to supply 484.5 kVA to the load.
Notes:
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Page LF.16
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master
`~å~Ç~= AC Load Flow Analysis
- Select the transformer(s) with adjustable taps that will be used as voltage control transformers.
- Select the bus or busses at which static reactive compensation is to be considered.
- Select the voltage control generators by defining them as PV units. PQ generators cannot regulate
voltage.
Step 1.
Open the file named
“EDM7.axd”.
Notes:
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Page LF.17
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master
`~å~Ç~= AC Load Flow Analysis
Step 2.
Define the settings for all
the potential voltage control
means desired.
Notes:
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Page LF.18
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master
`~å~Ç~= AC Load Flow Analysis
Step 3.
Following the guidelines explained in
previous sections of this manual, run
a Load Flow Analysis using scenario
No.1 (Co-Generation).
Step 4.
Produce a report that includes the
“Bus Voltage” results and a voltage
violation summary for all busses
outside a ±10% voltage tolerance.
The screen-capture shown here is a
partial view of the report showing
the voltage violation report
Notes:
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Page LF.19
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master
`~å~Ç~= AC Load Flow Analysis
Step 1. Step 2.
Select “Voltage Control”. Complete the “Voltage
Control Limits” section as
indicated here.
Step 3.
Select “Transformer Tap
Adjustments” as a means of
control. Press “OK”.
Step 4.
Select “OK”.
Notes:
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Page LF.20
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master
`~å~Ç~= AC Load Flow Analysis
Step 5.
Review the results and select
“Done” to exit.
Step 6.
Select “No’ for now. This
option will be explained later.
Notes:
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Page LF.21
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master
`~å~Ç~= AC Load Flow Analysis
Step 1. Step 2.
Select “Voltage Control”. Complete the “Voltage
Control Limits” section as
indicated here.
Step 3.
Select “Capacitor/Inductor...”
as a means of control. Press
“OK”
Step 4.
Select “OK”.
Notes:
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Page LF.22
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master
`~å~Ç~= AC Load Flow Analysis
Step 5.
Review the results and select
“Done” to exit.
Step 6.
Select “No’ for now. This
option will be explained later.
Notes:
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Page LF.23
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master
`~å~Ç~= AC Load Flow Analysis
Step 1. Step 2.
Select “Voltage Control”. Complete the “Voltage
Control Limits” section as
indicated here.
Step 3.
Select “Transformer…” and “Generator…”
as combined means of control. Press “OK”
Step 4.
Select “OK”.
Notes:
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Page LF.24
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master
`~å~Ç~= AC Load Flow Analysis
Step 5.
Review the results and select
“Done” to exit.
Step 6.
Select “Yes’ to test the results.
Step 7.
Select OK to acknowledge.
Notes:
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Page LF.25
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master
`~å~Ç~= AC Load Flow Analysis
Step 8.
Select “Yes” and verify
convergence.
Step 9.
The solution proves to be
effective as indicated here.
Notes:
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Page LF.26
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master
`~å~Ç~= AC Load Flow Analysis
Step 10.
Select “Exit”.
Step 11.
Select “Yes”.
Step 12.
Save the file under a different
name, if you wish to avoid over-
writing the original one. Press
“Save”.
Notes:
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Page LF.27
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master
`~å~Ç~= AC Load Flow Analysis
Step 1.
Run a Load Flow analysis
on the subject file.
Step 2. Step 3.
Select “Xfr Sizing”. Enter the “Design Margin” in
%, and select “OK”.
Notes:
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Page LF.28
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master
`~å~Ç~= AC Load Flow Analysis
Step 2.
Select “ON”.
Step 1.
Click here to select the
“Back Annotation” tool.
Step 3.
Select the desired components
from the “AC Load Flow” section.
Step 4.
Select “OK”.
Notes:
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Page LF.29
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master
`~å~Ç~= AC Load Flow Analysis
Notes:
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Page LF.30
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master
`~å~Ç~= AC Load Flow Analysis
Step 1.
Proceed to open the
file “EDM9.axd”
Note:
These three static loads will
be entered as unbalanced
loads.
Step 2.
Run a Load Flow Connectivity
Error Check”, and correct any
problems as required.
Notes:
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Page LF.31
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master
`~å~Ç~= AC Load Flow Analysis
Step 2.
Select the
Step 1. “Visibility” tab.
Click here to invoke the
“Master File Editor”.
Step 3.
Check the “View Unbalanced
Load Flow Fields” option.
Step 4.
Select “OK”.
Notes:
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Page LF.32
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master
`~å~Ç~= AC Load Flow Analysis
Step 1.
Double click on each of the static
loads fed from bus J#1066, and edit
the Unbalanced Load Flow conditions
as indicated in steps 2 & 3.
Step 2.
Select the “Unbalanced Load
Flow” tab.
Step 3.
Enter a per-phase distribution
as indicated here. Assume the
same percentile values for all
three static loads.
Notes:
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Page LF.33
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master
`~å~Ç~= AC Load Flow Analysis
Step 2.
Select “Run”.
Step 1.
Select “AC 3-Phase
Unbalanced”.
Step 3.
Select “Continue”.
Step 4.
Select the desired options
and press “OK”.
Step 5.
Allow the program to adjust the
tolerance by selecting “Yes”.
Notes:
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Page LF.34
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master
`~å~Ç~= AC Load Flow Analysis
Step 6.
Verify that the calculation
has converged and select
“View Results”.
Notes:
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Page LF.35
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master
`~å~Ç~= AC Load Flow Analysis
Step 1.
Proceed to open the
file “EDM10.axd”
Note:
These four loads will be
entered as cycling loads.
Step 2.
Run a Load Flow Connectivity
Error Check”, and correct any
problems as required.
Notes:
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Page LF.36
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master
`~å~Ç~= AC Load Flow Analysis
Step 2.
Select the “Visibility” tab.
Step 3.
Check the “View Voltage Profile
Fields” option.
Step 4.
Select the “Time Periods” tab.
Step 5.
Define the “Load-Cycling”
time periods. Select “OK”.
Notes:
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Page LF.37
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master
`~å~Ç~= AC Load Flow Analysis
Notes:
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Page LF.38
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master
`~å~Ç~= AC Load Flow Analysis
Step 2.
Select “Run”.
Step 1.
Select “AC
Step 3. Voltage Profile”.
Define the “Load Flow
Options”, and select
“OK”.
Step 4.
Verify convergence for all
periods, and select “Done”.
Step 5.
To view the results, select
“Results”.
Notes:
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Page LF.39
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master
`~å~Ç~= AC Load Flow Analysis
Step 3.
Select “OK”
to return.
Step 1.
Select the bus to
view, by clicking
on it once.
Step 2.
View and edit the graphs.
When done press “Exit”.
Notes:
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Page LF.40
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master
`~å~Ç~= AC Load Flow Analysis
Step 2.
Select Electrical One Line
Single-Phase.axd”, and press
“OK”.
Step 1.
Click here to create a
new job-file.
Step 3.
Name the file, and
select “Open”. Step 4.
De-select the password
requirement, and press
“OK”.
Notes:
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Page LF.41
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master
`~å~Ç~= AC Load Flow Analysis
Step 5.
Following the same guidelines outlined in the
“Main User Interface” section of this manual,
proceed to build the required single-phase
network.
Notes:
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Page LF.42
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master
`~å~Ç~= AC Load Flow Analysis
Step 2.
Run a load-flow
connectivity error check.
Step 3.
Invoke the AC Load-Flow
Analysis program.
Step 1.
Proceed to open the
single-phase file named
“EDM6.axd”.
Step 3.
The AC Load Flow Analysis program is designed to analyze both
Exercise single and three-phase systems. To continue, simply repeat the
same steps explained in section 4.0 of this manual.
Notes:
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Page LF.43
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master
`~å~Ç~= AC Load Flow Analysis
Using the File “EDM7X.axd”, shown in the above picture, complete the following questionnaire:
5. List the transformers loaded beyond 100% of their capacity: F:______ T:______
F:______ T:______
Notes:
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Page LF.44
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master
`~å~Ç~= AC Load Flow Analysis
F:______ T:______
Size 1:___________kVA
Size 2:___________kVA
Size 3:___________kVA
7. Design a Power Factor Correction Capacitor Bank (as shown in the figure) that will improve the
overall system power factor to a value of 92%.
Once the required kVA has been calculated, enter the value into the network and re-run the Load
Flow Analysis to confirm the results.
8. Calculate suitable transformer Tap Settings that will maintain system voltages within a ±10%
tolerance at all busses. Assume the following:
All Transformers:
Notes:
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Page LF.45
©2002 EDSA Micro Corp. / PQ Logic Corp.