INTRODUCTION

JAYARAM COLLEGE OF ENGINEERING & TECHNOLOGY
Pagalavadi, Trichirappalli – 621014.
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGG
BONAFIDE CERTIFICATE
Certified that this the bonafide record of practicals done Mr/Ms……………………………… of
VI sem III year Of Electronics and Communication Engineering Branch during the year 2009-
2010 in the following lab course
Course code :………………………………….
Course name :…………………………………
Reg .no :
Pagalavadi
Date:……………………….. H.O.D STAFF IN CHARGE
Submitted for the Anna university Practical Examination held on ………………….
EXTERNAL EXAMINER INTERNAL EXAMINER

INDEX
SERI MAR
DATE NAME OF THE EXPERIMENT PAGE NO. SIGN
AL KS
NO.
INTRODUCTION
STUDY OF SIMULATION USING VERILOG

1 MODULE AND SCHEMATIC PROCESS
STUDY OF SYNTHESIS TOOL

2
STUDY OF PLACE AND ROUTE AND

BACK ANNOTATION
3
HALF ADDER USING VERILOG AND

SCHEMATIC MODULE
4.A
FULL ADDER USING VERILOG MODULE

4.B
FULL SUBTRACTOR USING VERILOG

AND SCHEMATIC MODULE
4.C
MULTIPLEXER USING VERILOG AND

4.D
SCHEMATIC MODULE
DEMULTIPLEXER USING VERILOGHDL

4.E
D-FLIP FLOP USING VERILOG AND

4.F
SCHEMATIC MODULE
J.K FLIP FLOP USING VERILOG

MODULE
4.G
ENCODER USING VERILOG AND

4.H
SCHEMATIC MODULE
4.I SERIAL IN SERIAL OUT SHIFT REGISTER
SERIAL IN PARALLEL OUT SHIFT

4.J
REGISTER
INTRODUCTION
STUDY OF SIMULATION USING TOOLS
Introduction to EDA
The acronym for EDA-electronics design automation tools.
The digital designers found very difficult to design complex circuits and to verify that
working properly or not in a short time period. So they some computer aided tool(CAD) to
EDA tools.
Types of EDA tools in VLSI field are:
1. Simulation tool
2. Synthesis
What is simulation?
General definition:
The process of imitating a real phenomenon with a set of mathematical formulas.

Advanced computer programs can simulate weather conditions, chemical reactions, atomic
reactions, even biological processes. In theory, any phenomena that can be reduced to
mathematical data and equations can be simulated on a computer. In practice, however,
simulation is extremely difficult because most natural phenomena are subject to an almost
infinite number influences. One of the the tricks to developing useful simulations,
therefore, is to determine which are the most important factors. In addition to imitating
processes to see how they behave under different conditions, simulations are also used to
test new theories. After creating a theory of causal relationships in the form of a computer
program. If the program then behaves in the same way as the real process, there is a good
chance that the proposed relationships are correct.
Technical definition:
Simulating a chip design through software programs that use models to replicate how a
device will perform in terms of timing and results.The various tools available in market for
simulation, which supports VHDL(very high speed integrated circuits hardware description
language) and verilog HDL(verification logic hardware description language) are:
1. Verilog-XL
2. NCverilog
3. Modelsim
4. Mpsim
5. Active HDL
Out of this modelsim from the company mentor graphics is the most popular simulator, it
has got very good debugger, it supports systemC, verilog, VHDL and system verilog.
STUDY OF SYSNTHESIS USING TOOLS
What is synthesis?
The process by which a designer is able to fully automate the contents of an IC design.
Today’s chip designs have millions of switches. An engineer cannot possibly design all of
these gates with pencil and paper. Companies such as synopsys, Xilinx, cadence create
software tolls, for synthesis, that fully automate the creation of these switches—making
possible the design of semiconductors.
Types of synthesis tool:
The various tools available in market for synthesis, which supports VHDL(very high speed
integrated circuits hardware description language) and verilog HDL(verification logic
hardware description language)are:
1. Xilinx project navigator-xilinx inc
2. Altera max plus-altera inc
3. Design compiler-cadence
4. Leonardo spectrum-mentor graphics
Out of this project navigator(ISE) from the company Xilinx is the most popular synthesis
tool, which supports systemc, verilog, VHDL and system verilog.So in our discussion we
will be using, project navigator(ISE) version:6.1i.
Introduction to project navigator(ISE)
Integrated software environment(ISE) is the Xilinx design software suite.
ISE can be used by a full spectrum of designers, from the first time CPLD designer to the
experienced ASIC designer transitioning to FPGA.
HDL(VHDL, verilog HDL)
Schematic design files
NGC/NGO
State machines
Ip cores
HDL sources may be synthesized using the Xilinx synthesis technology(XST). The Xilinx
implementation tools continue the process into a placed and routed FPGA or fitted CPLD,
and finally produce a bit stream for your device configuration.
Synthesis?
Converting higher level of abstraction to lower level of abstraction
Higher level-HDL language
Lower level-Equivalent gate level implementation of HDL language
PLACE, ROUTE AND BACK ANNOTATION FOR FPGA
Definition:
Place and route
1. Placement is a task of placing the logical blocks to the adjacent block to minimize
the area of the chip size.
2. Routing the task of connecting the logical blocks with the wires.
Back annotation:
As synthesis technology evolved, cooperation between synthesis and place and route
(P&R) operations became bidirectional, although still sequential. In place-optimization
(IPO) techniques emerged. Logic synthesis produced a netlist that was placed and routed.
Then results from the P&R were back annotated, in the synthesis tool, in an effort to fix
timing violations. The tools use the gate level netlist produced by logic synthesis and the
delays extracted from P&R. using various algorithms, like replicating registers with high
fanout, and logic restricting, the tool optimizes the design’s critical path in order to achieve
timing convergence. The modified netlist is then sent to P&R again and iterated upon.
The approach is also used in physical optimizations for FPGA today. This method can be
very time consuming because placeand route of a complex FPGA takes hours. Worse yet,
convergence is typically an issue. Each new netlist requires a new P&R run ending up with
a new set of timing violations. Performing several iterations is not only costly, but does not
guarantee converge. Using incremental placement, where only the changed portion of the
design is reprocessed, may not fix the problem because of the complex dependencies
generated when trying to optimize only a portion only a portion of the fixed routing
channels available on the FPGA.
STUDY OF SIMULATION USING VERILOG MODULE
AIM:
To study the simulation process using XILINX ISE 9.Li tool
THEORY:
The Simulator environment must maintain information about various design units
involved in simulation such as location of libraries . If the verilog HDL analyzer returns
errors relating to the absence of key libraries it is most likely a result of the lack of
definition of the physical location of the logical libraries.
PROCEDURE
 Intialize the Xilinx ISE 9.li simulator by double clicking the icon on the
desktop.
 In the design summary window go to New project through the File menu.
 Enter the Project Name In the New project wizard and then click Next.
 In the New project wizard select the following specifications.

Project category  ALL
Family spartan2 (select required family)
Device XC2S150(select required device)
Package PQ208 (select required package)
Speed -6
Top level source type HDL
System tool XST(VHDL/Verilog)
Program language Verilog (select required language)

 After selecting the required specifications click Next and select New source.
 In the New source wizard select Verilog module and enter the File name
and then click Next.
 Set the input and output variable to be used and then click Next
 The Summary of the New source wizard is displayed ,conform the displayed
details by clicking finish icon.
 Then click Next consecutively until the coding screen appears

 Enter the project coding in the appropriate place.
 Then go to the Synthesis XST and double click the check syntax . It checks for error
and displays the result.
 Go to the source and select synthesis /implementation .Here right click the
mouse and select New Source
 Here select the TEST BENCH WAVEFORM and enter the file name and then click
next.
 Then click finish

 Then initial Timing and clock Wizard window is open .Here either select
Combinational (or internal clock ) for without giving clock input or select Single
Clock for giving clock input and then select finish.
 Then give the inputs through wave selection and save it.
 After that go to the Source and select Behavioural Simulation.

 Then go to Process and open the XILINX ISE simulator.
 Double click the simulate Behavioural Module in XILINX ISE simulator Which
displays the Output Waveform.
STUDY OF SIMULATION USING SCHEMATIC PROCESS
STEP 1: Follow steps 1 to 5 as same in VERILOG MODULE procedure.

STEP 2: As like in step 6 in VERILOG MODULE process, in the New Source Wizard
select Schematic and enter the File Name thin click Next.
STEP 3: Your New Source Wizard summary is shown and select Finish and conform
Yes
STEP 4: Then click Next and again click Next, finally select Finish
STEP 5: Select Symbol design in source menu

STEP 6: In these Logic for logic gates or we select required for design and put the symbol
in Design Summary.
STEP 7: Select Wire for connecting purpose as like here.

STEP 8: Select I/O Marker for input/output buffer as like below.
STEP 9: Double click on each I/O Marker & assign the name like a,b (or) any required
STEP 10: Save the Design Summary.
STEP 11: Go to Source.
STEP 12: Go to Design Utilities and double click the Check Design Rules for completed
successfully.
STEP 13: Follow steps 12 to 22 as same in VERILOG MODULE procedure.
RESULT:
Thus the simulation of VERILOG MODULE and SCHEMATIC PROCESS

was studied.
STUDY OF SYNTHESIS TOOL

AIM:
To study she synthesis process using XILINX ISE 9.1i tool.
THEORY:
Synthesis is an automatic method of converting a higher level abstraction to a lower

level abstraction. The synthesis tool convert register transfer level (RTL) description to
gate level net lists. This gate level net lists consist of inter connected gate level macro
cells. These gate level net lists can be optimized for area, speed, power, etc.
The analyzed design is synthesized to a library of components, typically gates, latch or

flip-flops. Hierarchical designs are synthesized in bottom up fashion, that is lower level
components are synthesized before higher level components. Once the design is
synthesized we have a gate level net list. This gate level net list can be simulated. Delay
for individual components are available as part of the description of the component
libraries. Timing accurate simulation is not possible at this point because the actual timing
characteristics are determined by the physical placement of design within the FPGA chip.
However, the functional simulation that is possible at this point is quite a bit more accurate
then simulation based on user specified delays.
For the above XOR gate model explained in experiment No 1, the next step is change
source for as Synthesis/Implementation. After run the synthesis in process window that is
shown in below figures. Then XOR gate model is converted to net list file. To convert
RTL to gates, four steps typically occurs below.
PROCEDURE:
STEP 1: Follow the steps as seen previous process like either simulation procedure or
Schematic procedure. Then select Synthesis\Implementation in the

Source.
STEP 2: Then double click the Synthesis-XST in the process.
STEP 3: Then double click the Check Syntax for completed successfully and also
double
click the View Synthesis Report for more details.

STEP 4: Go to View RTL Schematic in Synthesis-XST in the process.
STEP 5: Then double click View RTL Schematic for schematic representation of
our
project.
STEP 6: Then double click inside the schematic representation of our project we get
like below
RESULT:
Thus the SYNTHESIS PROCESS was studied.

STUDY OF PLACE AND ROUTE & BACK ANNOTION
AIM:
Place and Route and Back annotation for FPGAs.
THEORY:
For above XOR module, we have a gate-level net list the next step is to map this
design on to the FPGA. The primitive hardware elements are available in XILINX
xc3s500e chip, namely lookup tables and positive-edge-triggered flip-flop are organized as
a two dimensional array of CLBs. The net list from synthesize is composed of gate,
latches, and flip-flop. It’s necessary to assign CLB to net list primitives. This is the
process mapping a design. For example gates will be assigned to lookup table as illustrated
below.
PROCEDURE:
STEP 1: Follow the steps as seen previous process like either Simulation Procedure
or
Schematic Procedure. Then double click the Implement Design in Process.

STEP 2: In the Implement Design select Place and Route.
STEP 3: In the Place and Route select View/Edit Placed Design (Floor Planner)
and double click it.
STEP 4: In the Place and Route select View/Edit Route Design (FPGA Editor).
STEP 5: The maximize picture for XOR gate FPGA Editor is shown below.
RESULT:
Thus the PLACE AND ROUTE & BACK ANNOTATION for FPGAs was
studied.
PROGRAM FOR HALF ADDER USING VERILOG MODULE

AIM:
To design a Half adder circuit using verilog module in XILINX ISE 9.1i tool.
CODING:
module add(a, b, s, c);

input a;
input b;
output s;
output c;
reg s,c;
always@(a,b)
begin
if(a==1'b0&&b==1'b0)
begin
s=1'b0;
c=1'b0;
end
else if(a==1'b0&&b==1'b1)
begin
s=1'b1;
c=1'b0;
end
else if(a==1'b1&&b==1'b0)
begin
s=1'b1;
c=1'b0;
end
else
begin
s=1'b0;
c=1'b1;
end
end
endmodule
=================================================================
========
* Final Report *
=================================================================
========
Final Results
RTL Top Level Output File Name : add.ngr
Top Level Output File Name : add
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs :4
Cell Usage :
# BELS :2
# LUT2 :2
# IO Buffers :4
# IBUF :2
# OBUF :2
=================================================================
========
Device utilization summary:
---------------------------
Selected Device : 2s150pq208-6
Number of Slices: 1 out of 1728 0%

Number of 4 input LUTs: 2 out of 3456 0%
Number of IOs: 4
Number of bonded IOBs: 4 out of 140 2%
.
PROGRAM FOR HALF ADDER USING SCHEMATIC MODULE
RESULT:
Thus the Half Adder was designed and its output was verified.
PROGRAM FOR FULL ADDER USING VERILOG MODULE
AIM:
To design a full adder circuit using verilog module and schematic in XILINX ISE 9.1i tool.
CODING:
module fa(a, b, ci, s, c);
input a;
input b;
input ci;
output s;
output c;
wire s,c;
assign s=(a^b)^ci;
assign c=(a&b)|(a&ci)|(b&ci);
endmodule
Final Report:
Final Results
RTL Top Level Output File Name : fa.ngr
Top Level Output File Name : fa
Output Format : NGC
Keep Hierarchy : NO
Design Statistics
# IOs :5
Cell Usage :
# BELS :2
# LUT3 :2
# IO Buffers :5
# IBUF :3
# OBUF :2
Number of IOs: 5
RESULT:
Thus the Program for Full Adder was completed successfully.

PROGRAM FOR FULL SUBTRACTOR USING VERILOG MODULE
AIM:
To design a full subtractor using verilog module in XILINX ISE 9.1i tool.
CODING:
module fs(a, b, bi, d, bo);
input a;
input b;
input bi;
output d;
output bo;
wire d,bo,a1;
assign d=(a^b)^bi;
assign a1=!a;
assign bo=(a1&b)|(a1&bi)|(b&bi);
endmodule
Final Report:
Final Results
RTL Top Level Output File Name : fs.ngr
Top Level Output File Name : fs
Output Format : NGC
Keep Hierarchy : NO
Design Statistics
# IOs :5
Cell Usage :
# BELS :2
# LUT3 :2
# IO Buffers :5
# IBUF :3
# OBUF :2
Number of IOs: 5
PROGRAM FOR FULL SUBTRACTOR USING SCHEMATIC

RESULT:
Thus the Full Subtractor was designed and its output was verified.
PROGRAM FOR MULTIPLEXER USING VERILOG MODULE
AIM:
To design a Multiplexer circuit using verilog module in XILINX ISE 9.1i tool.
CODING:
module mu(y,i0, i1, i2, i3, s1, s0);
input i0;
input i1;
input i2;
input i3;
input s1;
input s0;
output y;
wire s1b,s0b,d,e,f,g;
not1 l1(s0b,s0);
not1 l2(s1b,s1);
and1 l3(d,i0,s1b,s0b);
and1 l4(e,i1,s1b,s0);
and1 l5(f,i2,s1,s0b);
and1 l6(g,i3,s1,s0);
or1 l7(y,d,e,f,g);
endmodule
module not1(b,a);
input a;
output b;
assign b=!a;
endmodule
module and1(d1,a1,b1,c1);
input a1,b1,c1;
output d1;
assign d1=(a1&b1)&c1;
endmodule
module or1(e2,a2,b2,c2,d2);
input a2,b2,c2,d2;
output e2;
assign e2=(a2|b2)|(c2|d2);
endmodule
=======================================================================
==
* Final Report *
=======================================================================
==
Final Results
RTL Top Level Output File Name : mu.ngr
Top Level Output File Name : mu
Output Format : NGC
Keep Hierarchy : NO
Design Statistics
# IOs :7
Cell Usage :
# BELS :3
# LUT3 :2
# MUXF5 :1
# IO Buffers :7
# IBUF :6
# OBUF :1
=======================================================================
==
---------------------------
Number of IOs: 7

PROGRAM FOR MULTIPLEXER USING SCHEMATIC
RESULT:
Thus the Multiplexer was designed and its output was verified.
PROGRAM FOR DEMULTIPLEXER USING VERILOG MODULE

AIM:
To design a Demultiplexer circuit using verilog module and schematic inXILINX ISE 9.1i
tool.
CODING:
module demux(x, s1, s0, y0, y1, y2, y3);
input x;
input s1;
input s0;
output y0;
output y1;
output y2;
output y3;
//wire x,s1,s0;
reg y0,y1,y2,y3;
always @(x or s1 or s0)
//initial
begin
if(s1==1'b0&&s0==1'b0)
begin
y0=x;
y1=1'b0; y2=1'b0; y3=1'b0;
end
else if(s1==1'b0&&s0==1'b1)
begin
y1=x;
y0=1'b0; y2=1'b0; y3=1'b0;

end
else if(s1==1'b1&&s0==1'b0)
begin
y2=x;
y0=1'b0; y1=1'b0; y3=1'b0;
end
else //if (s1==1'b1&&s0==1'b1)
begin
y3=x;
y0=1'b0; y2=1'b0; y1=1'b0;
end
end
endmodule
=================================================================
========
* Final Report *
=================================================================
========
Final Results
RTL Top Level Output File Name : demux.ngr
Top Level Output File Name : demux
Output Format : NGC
Keep Hierarchy : NO
Design Statistics
# IOs :7
Cell Usage :
# BELS :4
# LUT3 :4
# IO Buffers :7
# IBUF :3
# OBUF :4
=================================================================
========
---------------------------
Number of IOs: 7
RESULT:
Thus the Program for Demultiplexer was completed successfully.

PROGRAM FOR D-FLIP FLOP USING VERILOG MODULE
AIM:
To design a D-Flip Flop using Verlog Module and Schematic Module in XILINX
ISE 9.1i tool.
CODING:
module DF(D, C, Q, QB);
input D;
input C;
inout Q;
inout QB;
wire db,y1,y2;
assign db = ~D;
assign y1 = ~(D&C);
assign y2 = ~(db&C);
assign Q = ~(y1&QB);
assign QB = ~(y2&Q);
endmodule
=================================================================
========
* Final Report *
=================================================================
========
Final Results
RTL Top Level Output File Name : DF.ngr
Top Level Output File Name : DF
Output Format : NGC
Keep Hierarchy : NO
Design Statistics
# IOs :4
Cell Usage :
# BELS :2
# INV :1
# LUT3 :1
# IO Buffers :4
# IBUF :2
# OBUF :2
=================================================================
========
---------------------------
Selected Device : 3s250epq208-5
Number of IOs: 4
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=================================================================
========
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE

REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
No clock signals found in this design
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -5
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 6.816ns
Timing Detail:
--------------All values displayed in nanoseconds (ns)

=================================================================
========
Timing constraint: Default path analysis
Total number of paths / destination ports: 4 / 2
-------------------------------------------------------------------------
Delay: 6.816ns (Levels of Logic = 4)
Source: C (PAD)
Destination: QB (PAD)
Data Path: C to QB
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 1 1.106 0.509 C_IBUF (C_IBUF)
LUT3:I0->O 3 0.612 0.451 Q1 (Q_OBUF)
INV:I->O 1 0.612 0.357 QB1_INV_0 (QB_OBUF)
OBUF:I->O 3.169 QB_OBUF (QB)
----------------------------------------
Total 6.816ns (5.499ns logic, 1.317ns route)
(80.7% logic, 19.3% route)
=================================================================
========
CPU : 11.42 / 14.25 s | Elapsed : 12.00 / 14.00
-->
Total memory usage is 148788 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 1 ( 0 filtered)
Number of infos : 0 ( 0 filtered)

PROGRAM FOR D-FLIP FLOP USING SCHEMATIC MODULE
RESULT:
Thus the D-Flip Flop was designed and its output was verified.
PROGRAM FOR JKFLIP-FLOP USING VERILOG MODULE
AIM:
To design a JK Flip-flop using verilog module in XILINX ISE 9.1i tool.
CODING:
module jk(q,q1,j,k,clk);
output q,q1;
input j,k,clk;
reg q,q1;
always@(j,k,clk)
begin
if(j==1'b0&&k==1'b0)
begin
q=q;
q1=q1;
end
else if(j==1'b0&&k==1'b1)
begin
q=1'b0;
q1=1'b1;
end
else if(j==1'b1&&k==1'b0)
begin
q=1'b1;
q1=1'b0;
end
else
begin
q=q1;
q1=q;
end
end
endmodule
Final Report:
Final Results
RTL Top Level Output File Name : jk.ngr
Top Level Output File Name : jk
Output Format : NGC
Keep Hierarchy : NO
Design Statistics
# IOs :5
Cell Usage :
# BELS :3
# LUT2 :1
# LUT3 :2
# FlipFlops/Latches :2
# LD :2
# IO Buffers :4
# IBUF :2
# OBUF :2

Number of Slice Flip Flops: 2 out of 3456 0%
Number of IOs: 5
RESULT:
Thus the Program for JK Flip Flop was completed successfully.
PROGRAM FOR ENCODER USING VERILOG MODULE
AIM:
To design a Encoder using Verilog Module in XILINX ISE 9.1i tool.
CODING:
module ENCODER1(D0, D1, D2, D3, X, Y);
input D0;
input D1;
input D2;
input D3;
output X;
output Y;
assign X= D2 | D3;
assign Y= D1 | D3;
endmodule
=================================================================
========
* Final Report
*================================================================
=========
Final Results
RTL Top Level Output File Name : ENCODER1.ngr
Top Level Output File Name : ENCODER1
Output Format : NGC
Keep Hierarchy : NO
Design Statistics
# IOs :6
Cell Usage :
# BELS :2
# LUT2 :2
# IO Buffers :5
# IBUF :3
# OBUF :2
---------------------------
Selected Device : 3s250epq208-5
Number of IOs: 6
---------------------------
Partition Resource Summary:
No Partitions were found in this design.

=================================================================
========
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE

REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
No clock signals found in this design
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------Speed Grade: -5
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 5.753ns
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=================================================================
========
Timing constraint: Default path analysis
Total number of paths / destination ports: 4 / 2
-------------------------------------------------------------------------
Delay: 5.753ns (Levels of Logic = 3)
Source: D2 (PAD)
Destination: X (PAD)
Data Path: D2 to X
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 1 1.106 0.509 D2_IBUF (D2_IBUF)
LUT2:I0->O 1 0.612 0.357 X1 (X_OBUF)
OBUF:I->O 3.169 X_OBUF (X)
----------------------------------------
Total 5.753ns (4.887ns logic, 0.866ns route)
(84.9% logic, 15.1% route)
==========
CPU : 11.66 / 14.25 s | Elapsed : 12.00 / 14.00 s
-->
Total memory usage is 148788 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 1 ( 0 filtered)
Number of infos : 0 ( 0 filtered)

PROGRAM FOR ENCODER USING SCHEMATIC MODULE
RESULT:
Thus the Encoder was designed and its output was verified.
PROGRAM FOR SERIAL IN SERIAL OUT USING VERILOG MODULE
AIM:
To design a serial in serial out using verilog module in XILINX ISE 9.1i tool
CODING:
module siso(sout,clk,rst,sin);
output sout;
input clk,rst,sin;
reg [3:0]tmp;
reg sout;
always@(clk,rst,sin)
begin
if(rst)
tmp=4'b0000;
sout=tmp[3];
end
else
begin
tmp={tmp[2:0],sin};
sout=tmp[3];
end
end
endmodule
Final Report:
Final Results
RTL Top Level Output File Name : siso1.ngr
Top Level Output File Name : siso1
Output Format : NGC
Keep Hierarchy : NO
Design Statistics
# IOs :4
Cell Usage :
# BELS :1
# LUT2 :1
# IO Buffers :3
# IBUF :2
# OBUF :1


Number of IOs: 4
RESULT:
Thus the Program for Serial in Serial out was completed successfully.
PROGRAM FOR SERIAL IN PARALLEL OUT USING VERILOG MODULE
AIM:
To design a serial in parallel out using verilog module in XILINX ISE 9.1i tool
CODING:
module sipo1(pout,clk,rst,sin);
output [7:0]pout;
input clk,rst,sin;
reg [7:0]tmp;
reg pout;
always@(clk,rst,sin)
begin
if(rst)
tmp=8'b00000000;
else
begin
tmp={tmp[6:0],sin};
pout=tmp;
end
end
endmodule
Final Report:
Final Results
RTL Top Level Output File Name : sipo1.ngr
Top Level Output File Name : sipo1
Output Format : NGC
Keep Hierarchy : NO
Design Statistics
# IOs : 11
Cell Usage :
# BELS :1
# LUT2 :1
# LD_1 :8
# Clock Buffers :1
# BUFGP :1
# IO Buffers :9
# IBUF :1
# OBUF :8
Number of IOs: 11
IOB Flip Flops: 8
Number of GCLKs: 1 out of 4 25%
RESULT:
Thus the Program for Serial in parallel out was completed successfully.
PROGRAM FOR PARALLEL IN SERIAL OUT USING VERILOG MODULE
AIM:
To design a parallel in serial out using verilog module in XILINX ISE 9.1i tool
CODING:
module piso(sout,clk,rst,load,pin);
output sout;
input [7:0]pin;
input clk,rst,load;
reg [7:0]tmp;
reg sout;
always @(clk,rst,load)
begin
if(rst)
begin
tmp=8'b00000000;
end
else if(load)
begin
tmp=pin;
sout=tmp[7];
end
else
begin
tmp={tmp[6:0],1'b0};
sout=tmp[7];
end
end
endmodule
Final Report:
Final Results
RTL Top Level Output File Name : piso.ngr
Top Level Output File Name : piso
Output Format : NGC
Keep Hierarchy : NO
Design Statistics
# IOs : 12
Cell Usage :
# BELS :1
# LUT2 :1
# LD_1 :1
# Clock Buffers :1
# BUFGP :1
# IO Buffers :3
# IBUF :2
# OBUF :1

Number of IOs: 12
IOB Flip Flops: 1
RESULT:
Thus the Program for parallel in Serial out was completed successfully.
PROGRAM FOR PARALLEL IN PARALLEL OUT USING VERILOG MODULE
AIM:
To design a parallel in parallel out using verilog module in XILINX ISE 9.1i tool
CODING:
module pipo1(pout,clk,rst,load,pin);
output [7:0]pout;
input [7:0]pin;
input clk,rst,load;
reg [7:0]tmp;
reg [7:0]pout;
always @(clk,rst,load)
begin
if(rst)
pout=8'b00000000;
else if(load)
tmp=pin;
else
pout=tmp;
end
endmodule
Final Report:
Final Results
RTL Top Level Output File Name : pipo1.ngr
Top Level Output File Name : pipo1
Output Format : NGC
Keep Hierarchy : NO
Design Statistics
# IOs : 19
Cell Usage :
# FlipFlops/Latches : 16
# LDC_1 :8
# LDE_1 :8
# Clock Buffers :2
# BUFGP :2
# IO Buffers : 16
# IBUF :8
# OBUF :8


Number of IOs: 19
IOB Flip Flops: 16
RESULT:
Thus the Program for parallel in parallel out was completed successfully.
PROGRAM FOR RING COUNTER USING VERILOG MODULE
AIM:
To design a ring counter using verilog module
CODING:
module ring(count,clk,rst);
output [3:0]count;
input clk,rst;
reg [3:0]tmp;
reg [3:0]count;
always@(clk,rst)
begin
if(rst)
tmp=4'b1000;
else
begin
tmp={tmp[2:0],tmp[3]};
end
count=tmp;
end
endmodule
Final Report:
Final Results
RTL Top Level Output File Name : ring.ngr
Top Level Output File Name : ring
Output Format : NGC
Keep Hierarchy : NO
Design Statistics
# IOs :6
Cell Usage :
# BELS :2
# LUT2 :2
# IO Buffers :5
# IBUF :1
# OBUF :4

Number of IOs: 6
RESULT:
Thus the Program for Ring counter was completed successfully.
PROGRAM FOR UP/DOWN COUNTER USING VERILOG MODULE
AIM:
To design an up/down counter using verilog module
CODING:
module up(count,clk,rst,en);
output [7:0]count;
input clk,rst,en;
reg [7:0]count;
always@(clk,rst,en)
begin
if(rst)
count=8'b00000000;
else if (en)
count=count+1;
else
count=count-1;
end
endmodule
Final Report:
Final Results
RTL Top Level Output File Name : up.ngr
Top Level Output File Name : up
Output Format : NGC
Keep Hierarchy : NO
Design Statistics
# IOs : 11
Cell Usage :
# BELS : 15
# GND :1
# LUT2 :1
# LUT4 : 10
# MUXF5 :3
# IO Buffers : 10
# IBUF :2
# OBUF :8


Number of IOs: 11
RESULT:
Thus the Program for UP/DOWN counter was completed successfully.
PROGRAM FOR SERIAL AND PARALLEL ADDER/SUBTRACTOR
AIM:
Design and Simulation of pipelined Serial and Parallel Adder and Subtractor to
add/subtract 8 number of size, 12 bits each in 2’s complement.
SOFTWARE AND HARDWARE REQUIREMENTS:
Simulation & Synthesis Tool : Xilinx Project Navigator 9.1
SPARTAN II Kit, JTAG Cable, Power Cord
5.1 Parallel Adder
THEORY:
To add 8 numbers of 12 bit data through parallel each of 2’s complement.
For Example:
Force the Input as
In1=”000000001111”
In2=”000000000001”
In3=”000000000001”
In4=”000000000001”
In5=”000000000010”
In6=”000000000010”
In7=”000000000010”
In8=”000000000010”
Check the result
SUM=”000000011010”
CARRY=”000”
CODING:
Default inputs are assign to all the inputs in1 to in8. If user needs to force new inputs, apply
in Simulation and verify the results.
module PADD(SUM, CARRY);
output [11:0] SUM;
output [2:0] CARRY;
reg[11:0]SUM;
reg[2:0]CARRY;
//8 Inputs each of 12 Bits.
reg[11:0]in1=12'b000000001111;
reg[11:0]in2=12'b000000000001;
reg[11:0]in3=12'b000000000001;
reg[11:0]in4=12'b000000000001;
reg[11:0]in5=12'b000000000010;
reg[11:0]in6=12'b000000000010;
reg[11:0]in7=12'b000000000010;
reg[11:0]in8=12'b000000000010;
// Temporary Signals.
reg[12:0]temp=13'b1000000000000;
reg[15:0]temp1=16'b1000000000000000;
reg[11:0]a1,a2,a3,a4,a5,a6,a7,a8;
reg[14:0]c=15'b000000000000000;
reg[14:0]res=15'b000000000000000;
always@(temp,in1,in2,in3,in4,in5,in6,in7,in8,temp1,a1,a2,a3,a4,a5,a6,a7,
a8,res,c)
begin
a1<=temp-in1;
a2<=temp-in2;
a3<=temp-in3;
a4<=temp-in4;
a5<=temp-in5;
a6<=temp-in6;
a7<=temp-in7;
a8<=temp-in8;
//Adding all 2’s Complement data
c<=a1+a2+a3+a4+a5+a6+a7+a8;
res<=temp1-c;
SUM<=res[11:0];
CARRY<=res[14:12];
end
endmodule
5.2 Parallel Subtractor
THEORY:
To subtract 8 numbers of 12 bit data through parallel each of 2’s complement.
For Example:
Force the Input as
In1=”000000001111”
In2=”000000000001”
In3=”000000000001”
In4=”000000000001”
In5=”000000000010”
In6=”000000000010”
In7=”000000000010”
In8=”000000000010”
Check the result
RES=”000000000100”
SIGN=”000”
CODING:
module PSUB1(RES, SIGN);
output [14:0] RES;
output SIGN;
reg[14:0]RES;
reg SIGN;
reg[11:0]in1=12'b000000001111;
reg[11:0]in2=12'b000000000001;
reg[11:0]in3=12'b000000000001;
reg[11:0]in4=12'b000000000001;
reg[11:0]in5=12'b000000000010;
reg[11:0]in6=12'b000000000010;
reg[11:0]in7=12'b000000000010;
reg[11:0]in8=12'b000000000010;
reg[15:0]temp=16'b1000000000000000;
reg[16:0]temp1=17'b10000000000000000;
reg[14:0]STORE,P1;
reg[15:0]P2,RES1;
always@(temp,in1,in2,in3,in4,in5,in6,in7,in8,RES1,STORE,P1,P2)
begin
//Adding all 8 inputs except in1 and then take 2’s Complement data
STORE<=in2+in3+in4+in5+in6+in7+in8;
P1<=temp-STORE;
P2<=in1+P1;
if(P2[15]==1'b1)
begin
RES<=P2[14:0];
SIGN<=1'b0;
end
else
begin
RES1<=temp1-P2;
RES<=RES1[14:0];
SIGN<=1'b1;
end
end
endmodule
5.3 Serial Adder
THEORY:
To add 8 numbers of 12 bit data through serial each of 2’s complement.
For Example:
Force the Input as
In1=”000000001111”
In2=”000000000001”
In3=”000000000001”
In4=”000000000001”
In5=”000000000010”
In6=”000000000010”
In7=”000000000010”
In8=”000000000010”
Check the result
SUM=”000000011010”
CARRY=”000”
CODING:
module SADDER1(SUM, CARRY);
output [11:0] SUM;
output [2:0] CARRY;

reg[11:0]SUM;
reg[2:0]CARRY;
reg[11:0]in1=12'b000000001111;
reg[11:0]in2=12'b000000000001;
reg[11:0]in3=12'b000000000001;
reg[11:0]in4=12'b000000000001;
reg[11:0]in5=12'b000000000010;
reg[11:0]in6=12'b000000000010;
reg[11:0]in7=12'b000000000010;
reg[11:0]in8=12'b000000000010;
reg[12:0]a1,a2,a3,a4,a5,a6,a7,a8;
reg[12:0]temp=13'b1000000000000;
reg[15:0]temp1=16'b1000000000000000;
reg[11:0]car0=3'b000;
reg[14:0]c=15'b000000000000000;
reg[14:0]res=15'b000000000000000;
reg[3:0]bit0,bit1,bit2,bit3,bit4,bit5,bit6,bit7,bit8,bit9,bit10,
bit11,bit12;
always@(temp,in1,in2,in3,in4,in5,in6,in7,in8,a1,a1,a3,a4,a5,a6,a7,
a8,temp1,c,res,bit0,bit1,bit2,bit3,bit4,bit5,bit6,bit7,
bit8, bit9, bit10, bit11, bit12)
begin
// Converting Input data into 2’s complement data
a1<=temp-in1;
a2<=temp-in2;
a3<=temp-in3;
a4<=temp-in4;
a5<=temp-in5;
a6<=temp-in6;
a7<=temp-in7;
a8<=temp-in8;
// Adding 2’s complement data’s Serially
bit0<=a1[0]+a2[0]+a3[0]+a4[0]+a5[0]+a6[0]+a7[0]+a8[0];
bit1<=a1[1]+a2[1]+a3[1]+a4[1]+a5[1]+a6[1]+a7[1]+a8[1]+bit0[3:1];
bit2<=a1[2]+a2[2]+a3[2]+a4[2]+a5[2]+a6[2]+a7[2]+a8[2]+bit1[3:1];
bit3<=a1[3]+a2[3]+a3[3]+a4[3]+a5[3]+a6[3]+a7[3]+a8[3]+bit2[3:1];
bit4<=a1[4]+a2[4]+a3[4]+a4[4]+a5[4]+a6[4]+a7[4]+a8[4]+bit3[3:1];
bit5 <=a1[5]+a2[5]+a3[5]+a4[5]+a5[5]+a6[5]+a7[5]+a8[5]+bit4[3:1];
bit6<=a1[6]+a2[6]+a3[6]+a4[6]+a5[6]+a6[6]+a7[6]+a8[6]+bit5[3:1];
bit7<=a1[7]+a2[7]+a3[7]+a4[7]+a5[7]+a6[7]+a7[7]+a8[7]+bit6[3:1];
bit8<=a1[8]+a2[8]+a3[8]+a4[8]+a5[8]+a6[8]+a7[8]+a8[8]+bit7[3:1];
bit9<=a1[9]+a2[9]+a3[9]+a4[9]+a5[9]+a6[9]+a7[9]+a8[9]+bit8[3:1];
bit10<=a1[10]+a2[10]+a3[10]+a4[10]+a5[10]+a6[10]+a7[10]+a8[10]+
bit9[3:1]; bit11<=a1[11]+a2[11]+a3[11]+a4[11]+a5[11]+a6[11]+a7[11]+a8[11]+
bit10[3:1];
bit12<=a1[12]+a2[12]+a3[12]+a4[12]+a5[12]+a6[12]+a7[12]+a8[12]+
bit11[3:1];
// Converting carry and lower bits
c<={bit12,bit11[0],bit10[0],bit9[0],bit8[0],bit7[0],bit6[0],bit5[0],bit4[0],
bit3[0],bit2[0],bit1[0],bit0[0]};
// Again 2’s complement the added data to get original value
res<=temp1-c;
SUM<=res[11:0];
CARRY<=res[14:12];
end
endmodule
5. 4 Serial Subtractor
THEORY:
To subtract 8 numbers of 12 bit data through serial each of 2’s complement.
For Example:
Force the Input as
In1=”000000001111”
In2=”000000000001”
In3=”000000000001”
In4=”000000000001”
In5=”000000000010”
In6=”000000000010”
In7=”000000000010”
In8=”000000000010”
Check the result
SUM=”000000011010”
CARRY=”000”
CODING:
module ssub(res,sign);
output [14:0] res;
output sign;
reg[14:0] res;
reg sign;
reg[11:0]in1 = 12'b000000001111;
reg[11:0]in2 = 12'b000000000001;
reg[11:0]in3 = 12'b000000000001;
reg[11:0]in4 = 12'b000000000001;
reg[11:0]in5 = 12'b000000000010;
reg[11:0]in6 = 12'b000000000010;
reg[11:0]in7 = 12'b000000000010;
reg[11:0]in8 = 12'b000000000010;
reg[15:0]temp=16'b1000000000000000;
reg[16:0]temp1=17'b10000000000000000;
reg[3:0]bit0,bit1,bit2,bit3,bit4,bit5,bit6,bit7,bit8,bit9,bit10,bit11;
reg[1:0]bits0,bits1,bits2,bits3,bits4,bits5,bits6,bits7,bits8,bits9,
bits10,bits11,bits12,bits13,bits14;
reg[15:0]c,res1;
reg[14:0]store,p1;
always@(in1,in2,in3,in4,in5,in6,in7,in8,c,temp,res1,store,bit0,bit1,bit2,bit3,
bit4,bit5,bit6,bit7,bit8,bit9,bit10,bit11,p1,bits0,bits1,bits2,bits3,bits4,bits5,bits6,bits
7,bits8,bits9,bits10,bits11,bits12,bits13,bits14)
begin
// Adding data in2 to in8 srially
bit0<=in2[0]+in3[0]+in4[0]+in5[0]+in6[0]+in7[0]+in8[0];
bit1<=in2[1]+in3[1]+in4[1]+in5[1]+in6[1]+in7[1]+in8[1]+bit0[3:1];
bit11<=in2[11]+in3[11]+in4[11]+in5[11]+in6[11]+in7[11]+in8[11]+
bit10[3:1];
// Concatenate carry & lower Bits
store<={bit11,bit10[0],bit9[0],bit8[0],bit7[0],bit6[0],bit5[0],bit4[0],bit3[0],
bit2[0],bit1[0],bit0[0]};
p1<=temp-store;
// Adding data in1 & p1 serially
bits0<=in1[0]+p1[0];
bits1<=in1[1]+p1[1]+bits0[1];
bits2<=in1[2]+p1[2]+bits1[1];
bits3<=in1[3]+p1[3]+bits2[1];
bits4<=in1[4]+p1[4]+bits3[1];
bits5<=in1[5]+p1[5]+bits4[1];
bits6<=in1[6]+p1[6]+bits5[1];
bits7<=in1[7]+p1[7]+bits6[1];
bits8<=in1[8]+p1[8]+bits7[1];
bits9<=in1[9]+p1[9]+bits8[1];
bits10<=in1[10]+p1[10]+bits9[1];
bits11<=in1[11]+p1[11]+bits10[1];
bits12<=1'b0+p1[12]+bits11[1];
bits13<=1'b0+p1[13]+bits12[1];
bits14<=1'b0+p1[14]+bits13[1];
// Concatenate carry & lower Bits
c<={bits14,bits13[0],bits12[0],bits11[0],bits10[0],bits9[0],bits8[0],bits7[0],
bits6[0],bits5[0],bits4[0],bits3[0],bits2[0],bits1[0],bits0[0]};
if(c[15]==1'b1)begin
sign<=1'b0;
res<=c[14:0];
end
else begin
sign<=1'b1;
res1<=temp1-c;
res<=res1[14:0];
end
end
endmodule
RESULT:
Thus the parallel and serial, adder and subtractor was designed and its
output was verified.
DESIGN OF TRAFFIC LIGHT CONTROLLER
AIM:
The Project aims at designing a Traffic Light Controller designed for Spartan II
FPGA target device.
Simulation & Synthesis Tool : Xilinx Project Navigator 9.1
SPARTAN II Kit, JTAG Cable, Power Cord
DESCRIPTION:
Here in this project we attempt to control the traffic according to a predefined sequence,
which operates as follows:
• According to the flow chart the signaling scheme starts with North Side initially.
• In North Side the Green light glows for 20-3 seconds (this counter operation is
performed by Down Counter) at that time the remaining sides will be in Red.
• When the counter reaches 3,the Green light in North side turns off and Yellow turns
on for a period of 3 seconds (2-0).
• Then the sequence is shifted to South, East and west sides, where the same
operation as mentioned above are performed.
• For Display the counter values we are using Seven segment (Common Cathode)
Led’s.
ADVANTAGE:
 No need for manpower to monitor traffic.
 Efficiency in monitoring improves.
CODING:
a) Traffic Light Controller Light

//Coding For Traffic Light Controller Design
module traffic (y1,y2,n_g,n_y,n_r,s_g,s_y,s_r,e_g,e_y,e_r,w_g,w_y,w_r,clk,rst);
//Input and Output Port Declarations
output [7:0]y1,y2; //Outputs to Seven Segment LED
output n_g,n_y,n_r; //Output For North Side
output s_g,s_y,s_r; //Output For South Side
output e_g,e_y,e_r; //Output For East Side
output w_g,w_y,w_r; //Output For West Side
input clk;
input rst;
reg n_g,n_y,n_r;
reg s_g,s_y,s_r;
reg e_g,e_y,e_r;
reg w_g,w_y,w_r;
reg [7:0]y1,y2;
wire [7:0]count_out;
integer j;
assign count_out =j;
parameter
ng=4'b0000,ny=4'b0001,nrsg=4'b0010,sy=4'b0011,sreg=4'b0100,ey=4'b0101,erwg=4'b011
0,wy=4'b0111,wrng=4'b1000;
reg [3:0]ps,ns;
//Sequential Logic To chane the States
always @ (posedge clk or negedge rst)
begin
if(rst==1'b0)
j <= 20;
else
begin
if(j !=0)
j <= j-1;
else
j <= 20;
end
end
always @(posedge clk or negedge rst)
begin
if(rst==1'b0)
ps <= ng;
else
ps <= ns;
end
always @(ps or j)
begin
case (ps)
ng:
begin
if((j <= 20)&&(j>3)) //for north Green
ns <= ng;
else
begin
if(j==3)
ns <= ny;
end
end
ny:
begin
if((j<3) && (j>0)) //for north yellow
ns <= ny;
else
begin
if(j==0)
ns<=nrsg;
end
end
nrsg:
begin
if((j <= 20)&&(j>3)) //for north red and south green
ns <= nrsg;
else
begin
if(j==3)
ns <= sy;
end
end
sy:
begin
if((j<3) && (j>0)) //for south yellow
ns <= sy;
else
begin
if(j==0)
ns<=sreg;
end
end
sreg:
begin
if((j <= 20)&&(j>3)) //for south red and east green
ns <= sreg;
else
begin
if(j==3)
ns <= ey;
end
end
ey:
begin
if((j<3) && (j>0)) //for east yellow
ns <= ey;
else
begin
if(j==0)
ns<=erwg;
end
end
erwg:
begin
if((j <= 20)&&(j>3)) //for east red and west green
ns <= erwg;
else
begin
if(j==3)
ns <= wy;
end
end
wy:
begin
if((j<3) && (j>0)) //for west yellow
ns <= wy;
else
begin
if(j==0)
ns<=ng; //State moves to North green
end
end
endcase
end
//Output Decoder
always @(ps)
begin
case (ps)
ng:
begin
n_g <= 1'b1;
n_y <= 1'b0;
n_r <= 1'b0;
s_g <= 1'b0;
s_y <= 1'b0;
s_r <= 1'b1;
e_g <= 1'b0;
e_y <= 1'b0;
e_r <= 1'b1;
w_g <= 1'b0;
w_y <= 1'b0;
w_r <= 1'b1;
end
ny:
begin
n_g <= 1'b0;
n_y <= 1'b1;
n_r <= 1'b0;
s_g <= 1'b0;
s_y <= 1'b0;
s_r <= 1'b1;
e_g <= 1'b0;
e_y <= 1'b0;
e_r <= 1'b1;

w_g <= 1'b0;
w_y <= 1'b0;
w_r <= 1'b1;
end
nrsg:
begin
n_g <= 1'b0;
n_y <= 1'b0;
n_r <= 1'b1;
s_g <= 1'b1;
s_y <= 1'b0;
s_r <= 1'b0;
e_g <= 1'b0;
e_y <= 1'b0;
e_r <= 1'b1;
w_g <= 1'b0;
w_y <= 1'b0;
w_r <= 1'b1;
end
sy:
begin
n_g <= 1'b0;
n_y <= 1'b0;
n_r <= 1'b1;
s_g <= 1'b0;
s_y <= 1'b1;

s_r <= 1'b0;
e_g <= 1'b0;
e_y <= 1'b0;
e_r <= 1'b1;
w_g <= 1'b0;
w_y <= 1'b0;
w_r <= 1'b1;
end
sreg:
begin
n_g <= 1'b0;
n_y <= 1'b0;
n_r <= 1'b1;
s_g <= 1'b0;
s_y <= 1'b0;
s_r <= 1'b1;
e_g <= 1'b1;
e_y <= 1'b0;
e_r <= 1'b0;
w_g <= 1'b0;
w_y <= 1'b0;
w_r <= 1'b1;
end
ey:
begin
n_g <= 1'b0;

n_y <= 1'b0;
n_r <= 1'b1;
s_g <= 1'b0;
s_y <= 1'b0;
s_r <= 1'b1;
e_g <= 1'b0;
e_y <= 1'b1;
e_r <= 1'b0;
w_g <= 1'b0;
w_y <= 1'b0;
w_r <= 1'b1;
end
erwg:
begin
n_g <= 1'b0;
n_y <= 1'b0;
n_r <= 1'b1;
s_g <= 1'b0;
s_y <= 1'b0;
s_r <= 1'b1;
e_g <= 1'b0;
e_y <= 1'b0;
e_r <= 1'b1;
w_g <= 1'b1;
w_y <= 1'b0;
w_r <= 1'b0;
end
wy:
begin
n_g <= 1'b0;
n_y <= 1'b0;
n_r <= 1'b1;
s_g <= 1'b0;
s_y <= 1'b0;
s_r <= 1'b1;
e_g <= 1'b0;
e_y <= 1'b0;
e_r <= 1'b1;
w_g <= 1'b0;
w_y <= 1'b1;
w_r <= 1'b0;
end
endcase
end
//Process to Convert Binary Value To Seven-Segment Value
always @(count_out)
begin
case(count_out)
8'b00000000: //00
begin
y1<=8'b01111110; //msb
y2<=8'b01111110; // lsb
//flag1=1'b0;
end
8'b00000001: //01
begin
y1<=8'b01111110;
y2<=8'b00110000;
end
8'b00000010: //02
begin
y1<=8'b01111110;
y2<=8'b01101101;
end
8'b00000011: //03
begin
y1 <= 8'b01111110;
y2 <= 8'b01111001;
end
8'b00000100: //04
begin
y1 <= 8'b01111110;
y2 <= 8'b00110011;
end
8'b00000101: //05
begin
y1 <= 8'b01111110;
y2 <= 8'b01011011;
end
8'b00000110: //06
begin
y1 <= 8'b01111110;
y2 <= 8'b01011111;
end
8'b00000111: //07
begin
y1 <= 8'b01111110;
y2 <= 8'b01110000;
end
8'b00001000: //08
begin
y1 <= 8'b01111110;
y2 <= 8'b01111111;
end
8'b00001001: //09
begin
y1 <= 8'b01111110;
y2 <= 8'b01111011;
end
8'b00001010: //10
begin
y1 <= 8'b00110000;
y2 <= 8'b01111110;
end
8'b00001011: //11
begin
y1<=8'b00110000;
y2<=8'b00110000;
end
8'b00001100: //12
begin
y1<=8'b00110000;
y2<=8'b01101101;
end
8'b00001101: // 13
begin
y1<=8'b00110000;
y2<=8'b01111001;
end
8'b00001110: //14
begin
y1<=8'b00110000;
y2<=8'b00110011;
end
8'b00001111: //15
begin
y1<=8'b00110000;
y2<=8'b01011011;
end
8'b00010000: //16
begin
y1<=8'b00110000;
y2<=8'b01011111;
end
8'b00010001: //17
begin
y1<=8'b00110000;
y2<=8'b01110000;
end
8'b00010010: //18
begin
y1<=8'b00110000;
y2<=8'b01111111;
end
8'b00010011: //19
begin
y1<=8'b00110000;
y2<=8'b01111011;
end
8'b00010100: //20
begin
y1<=8'b01101101;
y2<=8'b01111110;
end
endcase
end
endmodule
b)CLOCK DIVIDER
//Coding For Clock Divider
//Clock Divider Is used to reduce the clock frequency which is generated by Crystal
Oscillator present in the FPGA Board
module clock_div(clockoutput, clock,rst);
output clockoutput ;
input clock;
input rst;
reg div_2 ; //2^1
reg div_4 ; //2^2
reg div_8 ; //2^3
reg div_16; //2^4
reg div_32; //2^5
reg div_64; //2^6
reg div_128; //2^7
reg div_256; //2^8
reg div_512; //2^9
reg div_1024; //2^10
reg div_2048; //2^11
reg div_4096; //2^12
reg div_8192 ; //2^13
reg div_16384 ; //2^14
reg div_32768 ;//2^15
reg div_65536 ;//2^16

reg div_131072 ;//2^17
reg div_262144 ; //2^18
reg div_524288 ; //2^19
reg div_1048576; //2^20
reg div_2097152;//2^21
reg div_4194304; //2^22
always @(posedge clock or negedge rst)
if (!rst)
div_2 <= 1'b0;
else
div_2 <= ~ div_2;
always @(posedge div_2 or negedge rst)
if (!rst)
div_4 <= 1'b0;
else
div_4 <= ~ div_4;
if (!rst)
div_8 <= 1'b0;
else
div_8 <= ~ div_8;
if (!rst)
div_16 <= 1'b0;

else
div_16 <= ~ div_16;
if (!rst)
div_32 <= 1'b0;
else
div_32 <= ~ div_32;
if (!rst)
div_64 <= 1'b0;
else
div_64 <= ~ div_64;
if (!rst)
div_128 <= 1'b0;
else
div_128 <= ~ div_128;
if (!rst)
div_256 <= 1'b0;
else
div_256 <= ~ div_256;
if (!rst)
div_512 <= 1'b0;
else
div_512 <= ~ div_512;
if (!rst)
div_1024 <= 1'b0;
else
div_1024 <= ~ div_1024;
if (!rst)
div_2048 <= 1'b0;
else
div_2048 <= ~ div_2048;
if (!rst)
div_4096 <= 1'b0;
else
div_4096 <= ~ div_4096;
if (!rst)
div_8192 <= 1'b0;
else
div_8192 <= ~ div_8192;
if (!rst)
div_16384 <= 1'b0;
else
div_16384 <= ~ div_16384;
if (!rst)
div_32768 <= 1'b0;
else
div_32768 <= ~ div_32768;
if (!rst)
div_65536 <= 1'b0;
else
div_65536 <= ~ div_65536;
if (!rst)
div_131072 <= 1'b0;
else
div_131072<= ~ div_131072;
if (!rst)
div_262144 <= 1'b0;
else
div_262144<= ~ div_262144;

if (!rst)
div_524288 <= 1'b0;
else
div_524288<= ~ div_524288;
if (!rst)
div_1048576 <= 1'b0;
else
div_1048576<= ~ div_1048576;
if (!rst)
div_2097152<= 1'b0;
else
div_2097152<= ~ div_2097152;
if (!rst)
div_4194304 <= 1'b0;
else
div_4194304<= ~ div_4194304;
assign clockoutput = div_4194304;
endmodule
c)TOP LEVEL
//Combining Both Clock Divider and Traffic Light Controller Design in the Same Module
//TopModule For Traffic
module top_traffic(led1,led2,n_g,n_y,n_r, s_g,s_y,s_r,e_g,
e_y,e_r,w_g,w_y,w_r, clk1,rst1);
output [7:0]led1,led2;
output n_g,n_y,n_r;
output s_g,s_y,s_r;
output e_g,e_y,e_r;
output w_g,w_y,w_r;
input clk1;
input rst1;
wire sys_clk;
traffic t1(.y1(led1),.y2(led2),.n_g(n_g),.n_y(n_y),.n_r(n_r),.s_g(s_g),
.s_y(s_y),.s_r(s_r),.e_g(e_g),.e_y(e_y),.e_r(e_r),.w_g(w_g),
.w_y(w_y),.w_r(w_r),.clk(sys_clk),.rst(rst1));
clock_div d1(.clockoutput(sys_clk), .clock(clk1),.rst(rst1));
endmodule
RESULT:
Henceforth, we have designed Traffic Light Controller in Verilog Using both

Simulation and Synthesis tools.
STUDY OF FPGA BOARD
FPGA Design Flow
The FPGA based Design Flow is extensively used in today’s world due to its following
advantages – short design time, easy to market etc. FPGA based Design Flow allows one to
implement his/her VLSI design in a very short duration, cater to customer needs and make
last minute changes.
The FPGA based Design Flow is as shown below:-
1. Design Entry
2. Synthesis
3. Simulation
4. Implementation
5. Programming
FPGA DEVELOPMENT ENVIRONMENT
Fig. – FPGA DESIGN FLOW

1. Design Entry
User can enter the design by writing the descriptions of any digital system using
HDL (Hardware Description Language), which can be written in two Languages
such as: -
a. VHDL (Very High Speed Integrated Circuit HDL)

b. Verilog HDL
2. Synthesis
Synthesis is the process, which converts HDL CODE into Gate level circuit in the
form of NET LIST. This process is Target Technology dependent hence user must
select proper Device, Family, Part Number and Speed Grade. Also user may select
Synthesis Settings like Clock Frequency, Optimization for Speed or Area.
3. Simulation
Simulation, user can verify the functionality of his design by applying various
input signal combination and observing the output results. The simulation is
performed on gate level Netlist.
4. Implementation
Implementation is the process in which the design is passed through various stages
by TRANSLATE, MAPPING, TIME ANALYSIS and BIT STREAM. For locking
input and output signal to particular pins of the device, user must write UCF (User
Constraint File) before implementation and guide the same file to implementation
tool through the option set control files. Output of implementation is .bit file which
has to be converted into PROM file i.e .HEX file.
5. Programming
This is the process by which user can physically download the architecture from
computer to target device using programming cable. Use FPGA/CPLD
Development Platform to Download the Data to the FPGA trainer. Use only the
cable, which is supplied along with the kit.
GETTING STARTED WITH FPGA TRAINER KIT
This Chapter of the manual is on Hardware and Software requirement specifications to get
started with the FPGA trainer Kit.
The kit has the following Deliverables:

1. FPGA Kit in a box containing inbuilt units
 XILINX XC2S150 FPGA Development Platform
 4 x 3 Keypad
 Power Supply
2. Accessories
 Programming Cable
 Power Cord
 40 Pin FRC Cable
 FPGA Trainer Kit User Manual
 FPGA/CPLD Development platform Installation CD consisting of the following:

-
- PGA/CPLD Development platform for programming the FPGA device.

- Sample Programs
- Kit Testing Programs
- PDF files for Data Sheet of Spartan II FPGA, ADC0804, DAC 0808
- XILINX Webpack
3. Hardware and Software Requirements
Hardware Component : IBM-compatible Pentium Class Machine
Monitor : Colour
Operating System : Windows 2000 or Windows XP
CD Drive : CD drive on system for Installation (or portable CD Drive)
Ports : Serial Port to program the device
System Memory : Minimum 256 MB
Simulation Tool : ISE Simulator or any other simulator
Synthesis Tool : XILINX Alliance, Foundation series or XILINX WebPack

Programming Tool : FPGA/CPLD Development Platform.
4. Software Installation Procedure
 Insert the Installation CD in the CD drive.
The installation automatically starts when the CD is inserted. Otherwise,

select the CD drive from windows and invoke the setup.exe
After the software is installed, message “Installation Completed” is displayed.
 The FPGA/CPLD Development platform software is installed in

C:\ Program Files\ FPGA\CPLD Development Platform.
INTRODUCTION TO FPGA TRAINER KIT
FEATURES
 XC2S150 -5 PQ208C XILINX SPARTAN II Device with 208 Pins.

 On board 15.000 MHz Oscillator
 16 Digital Input With LED Indication
 16 Digital Output With LED Indication
 2 x 16 LCD Display
 4 x 3 Keypad
 40 I/O's of the device are available for user in standard Header for external use
 On Board Power supply
 32KB External Memory Interface
POWER SUPPLY
The FPGA trainer has on board power supply with the following specifications :-
Input : ~ 230 V , 50 Hz
Output : + 5V DC, -5V (with EMI Filter)
The Input Power supply should be from UPS.

Done LED 16 x 2 LCD Display
Serial Communication
Port
Power on LED
External 32KB Memory
Programming Port
SPARTAN II FPGA XILINX CPLD
15 MHz Onboard
External BERG Oscillator

Micro
ADC Controller
DAC
16 Output LEDs
16 Input LEDs
Input DIP Switch
Micro Controller
Reset Button
FPGA Reset Program Reset
Fig. 3 - DETAIL VIEW OF SPARTAN II FPGA DEVELOPMENT PLATFORM
PROGRAMMING CABLE
For downloading the design from PC, a 9 pin D Type connector (P2) is provided on board.
The trainer kit can be connected to PC's serial port with the supplied cable having 9 pin D
Type connector on both sides.
LEDs
 POWER-ON LED is used for Power Supply Indication.

 DONE LED is used to indicate successful configuration.
 Sixteen LEDs [IN1 to IN16] indicates the input.
 Sixteen LEDs [OP 1 to OP16] indicates FPGA output conditions.
LCD DISPLAYS
 16 x 2 LCD Display
DIP SWITCHES
Input DIP Switch
Two 8 – way DIP switches are provided for the user to give the digital inputs to the FPGA.
IN1 to IN8 represent single 8 – way DIP switch and IN9 to IN16 represents another 8 – way
DIP switch. Logic Levels applied to the FPGA can be seen on the LEDs as given below.
Logic 1 => GLOW
Logic 0 => OFF
Clock DIP Switch
The DIP switch S1 is provided to enable the clock to the FPGA. At most the Oscillator X2
can supply clock to 2 FPGA Clock Pins.
Fig. 3.1 - S1 Clock Switch
PRECAUTIONS
Precautions to be followed while using the Trainer Kit
 Verify the POWER ON LED status after applying power to the trainer kit.
 Connect the 9 pin D connector to the trainer kit. Use the Programming cable
supplied with the kit.
 Before implementation, it is necessary to lock the pins in the user constraint file
(UCF) as per the trainer kit hardware.
 While generating the PROM file Disable the Swap bit option.
 For downloading the .hex file use the Sands FPGA/CPLD Development Platform
software provided with our trainer kit.
 Do not touch any device while in power on or power off condition.
 No user serviceable parts are provided with the trainer kit.
PIN ASSIGNMENT - HEADER / JUMPER SETTINGS
HEADER
Details of BERG JP7
Fig. 6.1 BERG JP7
OUTPUTS
Details of 16 x 2 LCD Displays
Data Signals FPGA PIN No.

Data 0 P90
Data 1 P94
Data 2 P95
Data 3 P96
Data 4 P97
Data 5 P98
Data 6 P99
Data 7 P100
Control Signals FPGA PIN No.
E P89
WR/RE P88
RS P87
Details of External (32 KB) Memory Interface

Addres FPGA Pin FPGA Pin
Data
s Number Number
A0 P110 D0 P139
A1 P111 D1 P140
A2 P112 D2 P141
A3 P113 D3 P148
A4 P114 D4 P149
A5 P120 D5 P150
A6 P121 D6 P151
A7 P122 D7 P152
A8 P123
A9 P125 CONTROL SIGNALS
A10 P127
Control FPGA Pin
A11 P133
Signals Number
A12 P134 RE P109
A13 P136 WE P102
A14 P138 CS P101
Details of Keypad

Row 1 P57
Row 2 P58
Row 3 P59
Row 4 P49
Col 1 P48
Col 2 P47
Col 3 P46
Details of Serial Port

TX P132
RX P129
Details of Dedicated Input / Output Pins
Dedicated Input Pins Dedicated Output Pins
Identificatio FPGA Pin FPGA Pin

Identification
n Number Number
IN1 P3 OP1 P23
IN2 P4 OP2 P24
IN3 P5 OP3 P27
IN4 P6 OP4 P29
IN5 P7 OP5 P30
IN6 P8 OP6 P31
IN7 P9 OP7 P33
IN8 P10 OP8 P34
IN9 P14 OP9 P35
IN10 P15 OP10 P36
IN11 P16 OP11 P37
IN12 P17 OP12 P41
IN13 P18 OP13 P42
IN14 P20 OP14 P43
IN15 P21 OP15 P44
IN16 P22 OP16 P45
Details of S1
Figure 6.2 – SWITCH S1
Pins to be used for Microcontroller Interface
Data FPGA Pin

Signals Number
Data 0 P108
Data 1 P115
Data 2 P119
Data 3 P126
Data 4 P135
Data 5 P142
Data 6 P146
Data 7 P153
Pins to be used for ADC Interface

Data 0 P73
Data 1 P74
Data 2 P75
Data 3 P81
Data 4 P82
Data 5 P83
Data 6 P84
Data 7 P87
CE P147
RD P62
WR P63
Pins to be used for DAC Interface

Data 0 P23
Data 1 P24
Data 2 P27
Data 3 P29
Data 4 P30
Data 5 P31
Data 6 P33
Data 7 P34
CS P61
Settings for Multiplexed DAC & OP1 to OP8
Settings for OP16 to OP8 Settings for DAC
FPGA/CPLD Development Platform
INTRODUCTION
Our windows based software is used to configure the FPGA trainer kit. This is also
used to program any digital circuits in the FPGA, which is built using the HDL’s
(Hardware Description Language) such as VHDL (Very High Speed Integrated
Circuits Hardware Description Language) and/or Verilog. Our software configures
the FPGA device and checks only the functionality of the same. Supports
microcontroller interface and an FPGA serial communication. This avoids costly
downloading cables and software. The GUI is user friendly and aimed to avoid
overheads.
MENU DETAILS
The menu options are:
1. File
2. Edit
3. View
4. Operations
5. Functions
6. Output
7. Window
8. Help
The below figure shows the main window
Features of FPGA/CPLD Development Platform
a. Configuration using serial port, which avoids costly

downloading cables.
b. Hardware functional verification using microcontroller
Serial Communication between the FPGA Kit and the PC
The menu, which helps to start the process is output menu.
The Serial port communication is established by choosing the cable auto connect
submenu in the output menu.
The cable auto connect automatically searches for the target device if the device is
available it will allow you to program it.
RESULT:
Thus the study of FPGA board was completed.
TESTING ON BOARD LED’s AND SWITCHES USING VERILOG
AIM:
To Write a Verilog Code to test on board Led’s and Input DIP Switches in FPGA board.
HARDWARE REQUIREMENTS
• SPARTAN II Kit
• RS232 Serial Cable
• Power Cord
PROGRAM
//Program To Check On-Board LED's and Input DIP Switches Using Verilog Code
// SPARTAN II KIT has 16 Input DIP Switches and 16-Output LED's
//Port Declarations
module led(op1,op2,op3,op4,op5,op6,op7,op8,op9, op10,op11,op12,op13,
op14,op15, op16,ip1,ip2,ip3,ip4,ip5,ip6, ip7,ip8,ip9,
ip10,ip11,ip12,ip13,ip14,ip15,ip16);
//Specifying Input And Output Ports
output op1,op2,op3,op4,op5,op6,op7,op8,op9;
output op10,op11,op12,op13,op14,op15,op16;
input ip1,ip2,ip3,ip4,ip5,ip6,ip7,ip8,ip9;
input ip10,ip11,ip12,ip13,ip14,ip15,ip16;
//assigning the functions
assign op1 = ip1;
assign op2 = ip2;
assign op3 = ip3;
assign op4 = ip4;
assign op5 = ip5;
assign op6 = ip6;
assign op7 = ip7;

assign op8 = ip8;
assign op9 = ip9;
assign op10 = ip10;
assign op11 = ip11;
assign op12 = ip12;
assign op13 = ip13;
assign op14 = ip14;
assign op15 = ip15;
assign op16 = ip16;
endmodule
EXECUTION
a) Write the above Verilog code first in the simulation tool (ISE Simulation) as per the
steps in study of simulation process.
b) Synthesize the above code using the Synthesis tool (Xilinx Project Navigator) and
generate the .Hex File as per the steps discussed in the Study of synthesis.
c) Connect the 3-pin power cord and the communication cable to the Spartan II board and
switch ON the power supply.
d) Generate bit file and download that file into FPGA board.
EXPECTED RESULT
Inputs IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 IN9 IN10 IN11 IN12 IN13 IN14 IN15 1N16
Identificatio OF OF
n ON ON F ON F ON OFF OFF ON ON ON OFF ON ON OFF ON
OP OP OP OP OP OP1 OP1 OP1 OP1
Outputs OP1 2 3 4 5 6 OP7 OP8 OP9 0 1 2 3 OP14 OP15 OP16
Identificatio OF OF
n ON ON F ON F ON OFF OFF ON ON ON OFF ON ON OFF ON
RESULT:
Thus the coding for checking the on board Led’s and Input DIP
Switches have been implemented in Verilog and tested using
SPARTAN II Kit.
TESTING OF TRAFFIC LIGHT CONTROLLER ON SPARTAN II FPGA BOARD
AIM:
The Project aims in testing the Traffic Light Controller design for Spartan II FPGA
target device using expansion card provided. The required algorithm was implemented in
the FPGA and the computations are done according to the requirements.

FPGA/CPLD Platform.
SPARTAN II Kit, JTAG Cable, Power Cord.
Traffic Light Controller Add-On Card.
EXECUTION:
a) Connect the 3-pin power cord and the communication cable to the Spartan II board and
b) Connect the Traffic Light Add-On Card to the 40 pin External berg present in the
FPGA trainer kit through FRC.
c) Go to the FPGA/CPLD Platform and initialize the serial port settings and download the
Hex file of Traffic Light Controller generated using Synthesis tool to the FPGA as per the
steps discussed in the study of FPGA process EXERCISE 7.1.
d) Check whether the DONE Led of the Spartan II board glows high if not again redo the
downloading procedure.
e) After checking the DONE Led give the clock input (S1-1) to high.
g) Verify the Automated Control of Traffic Light on the expansion card as per the
description given in EXERCISE 6.
*Note: Please refer below for Pin Assignments of Expansion Card with Spartan II FPGA.
PIN ASSIGNMENTS:
clk1 = "p77" ;
e_g = "p194" ;
e_r = "p201" ;
e_y = "p199" ;
led1<0 = "p180" ;
led1<1 = "p179" ;
led1<2> = "p178" ;
led1<3> = "p176" ;
led1<4> = "p175" ;
led1<5> = "p174" ;
led1<6> = "p173" ;
led1<7>= "p181" ;
led2<0>= "p168" ;
led2<1> = "p167" ;
led2<2> = "p166" ;
led2<3> = "p165" ;
led2<4> = "p164" ;
led2<5> LOC = "p163" ;
led2<6> LOC = "p162" ;
led2<7> LOC = "p172" ;
n_g = "p187" ;
n_r = "p192" ;
n_y = "p189" ;
rst1 = "p60" ;
s_g = "p188" ;
s_r = "p193" ;
s_y = "p191" ;
w_g = "p195" ;
w_r = "p202" ;
w_y = "p200" ;
Note: The Variable names are the one used in the coding section.
RESULT:
Thus we have designed and verified the Traffic Light Controller design with the help of
EDA tools, Add On Cards and SANDS Spartan II FPGA board.
DESIGN OF REAL TIME CLOCK
AIM:
The Project aims at designing a Real Time Clock and to display Minutes and
Seconds based on 15MHz quartz crystal designed for Spartan II FPGA target device and
tested the output using Interface card provided.
Simulation & Synthesis Tool : Xilinx Project Navigator 9.1SPARTAN II Kit,
JTAG Cable, Power Cord, Real Time Clock Add-On Card.
DESCRIPTION:
Provides hours, minutes and seconds based on 15 MHz quartz crystal
Additional Features of Real Time Clock

 Provides year, month, day, weekday, hours, minutes and seconds based on
 32.768 kHz quartz crystal
 Century flag
 Wide operating supply voltage range: 1.0 to 5.5 V
 Low back-up current; typical 0.25 A at VDD = 3.0 V and
Temp = 25 C
 400 kHz two-wire I2C-bus interface (at VDD = 1.8 to 5.5 V)

 Programmable clock output for peripheral devices: 32.768 kHz, 1024 Hz,
 32 Hz and 1 Hz
 Alarm and timer functions
 Voltage-low detector
 Integrated oscillator capacitor
 Internal power-on reset
 I2C-bus slave address: read A3H; write A2H
 Open drain interrupt pin.
APPLICATIONS:
 Mobile telephones
 Portable instruments
 Fax machines
 Battery powered products.
PROGRAM:
A) RTC CONTROLLER
// RTC controller
module rtc_controller(start,rst,minutes,hours);
input start,rst;
output [7:0]minutes;
output [7:0]hours;
integer i,j,k;
reg f1,f2;
wire [7:0]minutes;
wire [7:0]hours;
assign minutes=i; // “i”(secs counter) is assigned to minutes in order // to check the

output faster. (actual assignment value “j”)
assign hours=j; // “j”(mintues counter) is assigned to hours in order // to check the
output faster. (actual assignment value “k”)
always@(posedge start or negedge rst)

begin
if (rst==1'b0)
begin
i<=0;
end
else
begin
if (i!=59)
begin
i<=i+1;
f1<=1'b0;
end
else
begin
i<=0;
f1<=1'b1;
end
end
end
always@(posedge f1 or negedge rst)

begin
if(!rst)
j<=0;
else
begin
if (j!=59)
begin
j<=j+1;
f2<=1'b0;
end
else
begin
j<=0;
f2<=1'b1;
end
end
end

begin
if(!rst)
k<=0;
else
begin
if (k!=23)
begin
k<=k+1;
end
else
begin
k<=0;
end
end
end
endmodule
B) BINARY TO SEVEN SEGMENT
// Binary to seven segment for MINUTES conversion
module sevmin112(y1,y2,ip);
output [7:0]y1,y2;
input [7:0]ip;
reg [7:0]y1,y2;
always@(ip)
begin
case(ip)
8'b00000000: //00
begin
y1<=8'b01111110; //msb
y2<=8'b01111110; // lsb
//flag1=1'b0;
end
8'b00000001: //01
begin
y1<=8'b01111110;
y2<=8'b00110000;
end
8'b00000010: //02
begin
y1<=8'b01111110;
y2<=8'b01101101;
end
8'b00000011: //03
begin
y1 <= 8'b01111110;
y2 <= 8'b01111001;
end
8'b00000100: //04
begin
y1 <= 8'b01111110;
y2 <= 8'b00110011;
end
8'b00000101: //05
begin
y1 <= 8'b01111110;
y2 <= 8'b01011011;
end
8'b00000110: //06
begin
y1 <= 8'b01111110;
y2 <= 8'b01011111;
end
8'b00000111: //08
begin
y1 <= 8'b01111110;
y2 <= 8'b01110000;
end
8'b00001000: //08
begin
y1 <= 8'b01111110;
y2 <= 8'b01111111;
end
8'b00001001: //09
begin
y1 <= 8'b01111110;
y2 <= 8'b01111011;
end
8'b00001010: //10
begin
y1 <= 8'b00110000;
y2 <= 8'b01111110;
end
8'b00001011: //11
begin
y1<=8'b00110000;
y2<=8'b00110000;
end
8'b00001100: //12
begin
y1<=8'b00110000;
y2<=8'b01101101;
end
8'b00001101: // 13
begin
y1<=8'b00110000;
y2<=8'b01111001;
end
8'b00001110: //14
begin
y1<=8'b00110000;
y2<=8'b00110011;
end
8'b00001111: //15
begin
y1<=8'b00110000;
y2<=8'b01011011;
end
8'b00010000: //16
begin
y1<=8'b00110000;
y2<=8'b01011111;
end
8'b00010001: //18
begin
y1<=8'b00110000;
y2<=8'b01110000;
end
8'b00010010: //18
begin
y1<=8'b00110000;
y2<=8'b01111111;
end
8'b00010011: //19
begin
y1<=8'b00110000;
y2<=8'b01111011;
end
8'b00010100: //20
begin
y1<=8'b01101101;
y2<=8'b01111110;
end
8'b00010101: //21
begin
y1<=8'b01101101;
y2<=8'b00110000;
end
8'b00010110: //22
begin
y1<=8'b01101101;
y2<=8'b01101101;
end
8'b00010111: //23
begin
y1<=8'b01101101;
y2<=8'b01111001;
end
8'b00011000: //24
begin
y1<=8'b01101101;
y2<=8'b00110011;
end
8'b00011001: //25
begin
y1<=8'b01101101;
y2<=8'b01011011;
end
8'b00011010: //26
begin
y1<=8'b01101101;
y2<=8'b01011111;
end
8'b00011011: //28
begin
y1<=8'b01101101;
y2<=8'b01110000;
end
8'b00011100: //28
begin
y1<=8'b01101101;
y2<=8'b01111111;
end
8'b00011101: //29
begin
y1<=8'b01101101;
y2<=8'b01111011;
end
8'b00011110: //30
begin
y1<=8'b01111001;
y2<=8'b01111110;
end
8'b00011111: //31
begin
y1<=8'b01111001;
y2<=8'b00110000;
end
8'b00100000: //32
begin
y1<=8'b01111001;
y2<=8'b01101101;
end
8'b00100001: //33
begin
y1<=8'b01111001;
y2<=8'b01111001;
end
8'b00100010: //34
begin
y1<=8'b01111001;
y2<=8'b00110011;
end
8'b00100011: //35
begin
y1<=8'b01111001;
y2<=8'b01011011;
end
8'b00100100: //36
begin
y1<=8'b01111001;
y2<=8'b01011111;
end
8'b00100101: //38
begin
y1<=8'b01111001;
y2<=8'b01110000;
end
8'b00100110: //38
begin
y1<=8'b01111001;
y2<=8'b01111111;
end
8'b00100111: //39
begin
y1<=8'b01111001;
y2<=8'b01111011;
end
8'b00101000: //40
begin
y1<=8'b00110011;
y2<=8'b01111110;
end
8'b00101001: //41
begin
y1<=8'b00110011;
y2<=8'b00110000;
end
8'b00101010: //42
begin
y1<=8'b00110011;
y2<=8'b01101101;
end
8'b00101011: //43
begin
y1<=8'b00110011;
y2<=8'b01111001;
end
8'b00101100: //44
begin
y1<=8'b00110011;
y2<=8'b00110011;
end
8'b00101101: //45
begin
y1<=8'b00110011;
y2<=8'b01011011;
end
8'b00101110: //46
begin
y1<=8'b00110011;
y2<=8'b01011111;
end
8'b00101111: //48
begin
y1<=8'b00110011;
y2<=8'b01110000;
end
8'b00110000: //48
begin
y1<=8'b00110011;
y2<=8'b01111111;
end
8'b00110001: //49
begin
y1<=8'b00110011;
y2<=8'b01111011;
end
8'b00110010: //50
begin
y1<=8'b01011011;
y2<=8'b01111110;
end
8'b00110011: //51
begin
y1<=8'b01011011;
y2<=8'b00110000;
end
8'b00110100: //52
begin
y1<=8'b01011011;
y2<=8'b01101101;
end
8'b00110101: //53
begin
y1<=8'b01011011;
y2<=8'b01111001;
end
8'b00110110: //54
begin
y1<=8'b01011011;
y2<=8'b00110011;
end
8'b00110111: //55
begin
y1<=8'b01011011;
y2<=8'b01011011;
end
8'b00111000: //56
begin
y1<=8'b01011011;
y2<=8'b01011111;
end
8'b00111001: //58
begin
y1<=8'b01011011;
y2<=8'b01110000;
end
8'b00111010: //58
begin
y1<=8'b01011011;
y2<=8'b01111111;
end
8'b00111011: //59
begin
y1<=8'b01011011;
y2<=8'b01111011;
//flag1<=1'b1;
end
default:
begin
y1<= 8'b01111110;
y2<= 8'b01111110;
end
endcase
end
endmodule
C) BINARY TO SEVEN SEGMENT
// Binary to seven segment for HOURS conversion
module sevhrs113(y1,y2,ip);
output [7:0]y1,y2;
input [7:0]ip;
reg [7:0]y1,y2;
always@(ip)
begin
case(ip)
8'b00000000: //00
begin
y1<=8'b01111110; //msb
y2<=8'b01111110; // lsb
//flag1=1'b0;
end
8'b00000001: //01
begin
y1<=8'b01111110;
y2<=8'b00110000;
end
8'b00000010: //02
begin
y1<=8'b01111110;
y2<=8'b01101101;
end
8'b00000011: //03
begin
y1 <= 8'b01111110;
y2 <= 8'b01111001;
end
8'b00000100: //04
begin
y1 <= 8'b01111110;
y2 <= 8'b00110011;
end
8'b00000101: //05
begin
y1 <= 8'b01111110;
y2 <= 8'b01011011;
end
8'b00000110: //06
begin
y1 <= 8'b01111110;
y2 <= 8'b01011111;
end
8'b00000111: //08
begin
y1 <= 8'b01111110;
y2 <= 8'b01110000;
end
8'b00001000: //08
begin
y1 <= 8'b01111110;
y2 <= 8'b01111111;
end
8'b00001001: //09
begin
y1 <= 8'b01111110;
y2 <= 8'b01111011;
end
8'b00001010: //10
begin
y1 <= 8'b00110000;
y2 <= 8'b01111110;
end
8'b00001011: //11
begin
y1<=8'b00110000;
y2<=8'b00110000;
end
8'b00001100: //12
begin
y1<=8'b00110000;
y2<=8'b01101101;
end
8'b00001101: // 13
begin
y1<=8'b00110000;
y2<=8'b01111001;
end
8'b00001110: //14
begin
y1<=8'b00110000;
y2<=8'b00110011;
end
8'b00001111: //15
begin
y1<=8'b00110000;
y2<=8'b01011011;
end
8'b00010000: //16
begin
y1<=8'b00110000;
y2<=8'b01011111;
end
8'b00010001: //18
begin
y1<=8'b00110000;
y2<=8'b01110000;
end
8'b00010010: //18
begin
y1<=8'b00110000;
y2<=8'b01111111;
end
8'b00010011: //19
begin
y1<=8'b00110000;
y2<=8'b01111011;
end
8'b00010100: //20
begin
y1<=8'b01101101;
y2<=8'b01111110;
end
8'b00010101: //21
begin
y1<=8'b01101101;
y2<=8'b00110000;
end
8'b00010110: //22
begin
y1<=8'b01101101;
y2<=8'b01101101;
end
8'b00010111: //23
begin
y1<=8'b01101101;
y2<=8'b01111001;
end
default:
begin
y1<= 8'b01111110;
y2<= 8'b01111110;
end
endcase
end
endmodule
D) RTC TIMER TOP MODULE
module toprtc114(clk1,rst,minlsb,minmsb,hrslsb,hrsmsb);
input clk1;
input rst;
output [7:0]minlsb;
output [7:0]minmsb;
output [7:0]hrslsb;
output [7:0]hrsmsb;
wire [7:0]m1,m2;
wire [7:0]h1,h2;
wire [7:0]s2;
wire [7:0]s3;
wire [7:0]s4;
assign minlsb[7:0]=m2;
assign minmsb[7:0]=m1;
assign hrslsb[7:0]=h2;
assign hrsmsb[7:0]=h1;
rtc_controller one
(.start(clk1),.rst(rst),.minutes(s2),.hours(s3));//,.date(s4).flag2(f1));
sevhrs113 two(.y1(h1),.y2(h2),.ip(s3));
sevmin112 three(.y1(m1),.y2(m2),.ip(s2));
endmodule
E) LED ROLLER MODULE
module led_roll_117
(hrsmsb,hrslsb,minmsb,minlsb,clk,rst,dataout,en_tran1,en_tran2,en_tran3,en_tran4,clkout);
output clkout;
output [7:0]dataout;
output en_tran1;
output en_tran2;
output en_tran3;
output en_tran4;
input clk;
input rst;
input [7:0]hrsmsb;
input [7:0]hrslsb;
input [7:0]minmsb;
input [7:0]minlsb;
reg [7:0]dataout;
wire clkout;
reg en_tran1;
reg en_tran2;
reg en_tran3;
reg en_tran4;
parameter reset=3'b000,led1=3'b001, led2=3'b010, led3=3'b11, led4=3'b100;
reg [2:0]ps,ns;
assign clkout=clk;
always@(posedge clk or negedge rst)

begin
if(rst==1'b0)
begin
ps<=reset;
end
else
begin
ps<=ns;
end
end
always@(rst,ps,hrsmsb,hrslsb,minmsb,minlsb)
begin
case(ps)
reset: begin
dataout<=8'b00000000;
en_tran1<=1'b0;
en_tran2<=1'b0;
en_tran3<=1'b0;
en_tran4<=1'b0;
if(rst==1'b0)
ns<=reset;
else
ns<=led1;
end
led1: begin
dataout<=minlsb;
en_tran1<=1'b1;
en_tran2<=1'b0;
en_tran3<=1'b0;
en_tran4<=1'b0;
if(rst==1'b0)
ns<=reset;
else
ns<=led2;
end
led2: begin
dataout<=minmsb;
en_tran1<=1'b0;
en_tran2<=1'b1;
en_tran3<=1'b0;
en_tran4<=1'b0;
if(rst==1'b0)
ns<=reset;
else
ns<=led3;
end
led3: begin
dataout<=hrslsb;
en_tran1<=1'b0;
en_tran2<=1'b0;
en_tran3<=1'b1;
en_tran4<=1'b0;
if(rst==1'b0)
ns<=reset;
else
ns<=led4;
end
led4: begin
dataout<=hrsmsb;
en_tran1<=1'b0;
en_tran2<=1'b0;
en_tran3<=1'b0;
en_tran4<=1'b1;
if(rst==1'b0)
ns<=reset;
else
ns<=led1;
end
endcase
end
endmodule
F) TOP MODULE
module alltop119 (clk,rst,dataout,en_tran1,en_tran2,en_tran3,en_tran4,clkout);
output [7:0]dataout;
output en_tran1;
output en_tran2;
output en_tran3;
output en_tran4;
output clkout;
input clk;
input rst;
wire en_tran1;
wire en_tran2;
wire en_tran3;
wire en_tran4;
wire e1,e2,e3,e4;
wire u1,u4,u5,u6;
wire [7:0]m1,m2;
wire [7:0]h1,h2;
wire [7:0]u2; // mux to led roll
wire [1:0]u3;
assign en_tran1= e1;

assign u5=clk;
led_roll_117
q1(.hrsmsb(h1),.hrslsb(h2),.minmsb(m1),.minlsb(m2),.clk(u4),.rst(rst),.dataout(dataout),.en
_tran1(e1),.en_tran2(e2),.en_tran3(e3),.en_tran4(e4),.clkout(clkout));
toprtc114 q4(.clk1(u1),.rst(rst),.minlsb(m2),.minmsb(m1),.hrslsb(h2),.hrsmsb(h1));
rtclkd_115 q5(.co1hz(u1),.sck(u5),.rst(rst));
rtclkd_2 q6(.co10khz(u4),.sck(u5),.rst(rst));
endmodule
G) 1Hz CLOCK DIVIDER MODULE
module rtclkd_115(co1hz,sck,rst);
output co1hz;
input sck,rst;
wire co1hz;
reg f1,f2,f3;
integer n,p,r;
assign co1hz=f3;
always@(posedge sck or negedge rst)

begin
if(!rst)
begin
n<=0;
end
else
begin
if(n<=750)
begin
n<=n+1;
f1<=1'b0;
end
else
begin
if(n>750 && n<=1500)
begin
f1<=1'b1;
n<=n+1;
end
else
begin
f1<=1'b0;
n<=0;
end
end
end
end

begin
if(!rst)
begin
p<=0;
end
else
begin
if(p<=500)
begin
p<=p+1;
f2<=1'b0;
end
else
begin
if(p>500 && p<=1000)
begin
f2<=1'b1;
p<=p+1;
end
else
begin
f2<=1'b0;
p<=0;
end
end
end
end

begin
if(rst==1'b0)
begin
r<=0;
end
else
begin
if(r<=5)
begin
r<=r+1;
f3<=1'b0;
end
else
begin
if(r>5 && r<=10)
begin
f3<=1'b1;
r<=r+1;
end
else
begin
f3<=1'b0;
r<=0;
end
end
end
end
endmodule
H) 10KHz CLOCK DIVIDER
module rtclkd_2(co10khz,sck,rst);
output co10khz;
input sck,rst;
wire co10khz;
reg f1,f2,f3;
integer n,p,r;
assign co10khz=f1;
always@(posedge sck or negedge rst)

begin
if(!rst)
begin
n<=0;
end
else
begin
if(n<=750)
begin
n<=n+1;
f1<=1'b0;
end
else
begin
if(n>750 && n<=1500)
begin
f1<=1'b1;
n<=n+1;
end
else
begin
f1<=1'b0;
n<=0;
end
end
end
end
endmodule
EXECUTION
a) Connect the 3-pin power cord and the communication cable to the Spartan II board and
b) Connect the RTC Add-On Card to the 40 pin External berg present in the FPGA trainer
kit through FRC.
c) Go to the FPGA/CPLD Platform and initialize the serial port settings and download the
Hex file of Real time clock generated using Synthesis tool to the FPGA .
d) Check whether the DONE Led of the Spartan II board glows high if not again redo the
downloading procedure.
e) After checking the DONE Led give the clock input (S1-1) to high.
g) Verify the seconds and minutes on the Real Time Clock expansion card .
*Note: Please refer next page for Pin Assignments of Expansion Card with Spartan II
FPGA
PIN ASSIGNMENTS
"clk" LOC = "p77"
"clkout" LOC = "p174"
"dataout<0>" LOC = "p162"

"en_tran1" LOC = "p188"
"rst" LOC = "p60"
Note: The Variable names are the one used in the coding section.
RESULT:
Thus we have designed and verified the Real Time Clock design with
the help of EDA tools, Add on Cards and Spartan II FPGA board.
PROGRAM FOR 8-BIT SIGNED MULTIPLIER
AIM:
Design and simulation of 8 bit signed multiplier.

SOFTWARE REQUIREMENTS:
Simulation Tool &
Synthesis Tool : Xilinx Project Navigator 9.1
DESCRIPTION:
Signed multiplier
– The signed multiplier is a construction of shifter and adder structures. Since it is simply
composed of n bit adders that are connected in series.
– The below block diagram of an 8 bit pipelined multiplier. This circuit produces the
product of two 8 bit numbers after a delay of several clock ticks. The use of registers
between the ranks of adders makes it possible to input a new multiplier and multiplicand on
every clock tick and get a product on every clock tick. This kind of pipelined operation is
commonly used in high performance systems.
PROGRAM:
module ms(multiplicant, multiplier, prod);

input [7:0] multiplicant;
input [7:0] multiplier;
output [15:0] prod;
wire [15:0] shift1,shift2,shift3,shift4,shift5,shift6,shift7,shift8;
wire [15:0] add1,add2,add3,add4,add5,add6,add7,add8;
wire [15:0] prod_s;
assign shift1 = {8'b0,multiplicant};
assign shift2 = {7'b0,multiplicant,1'b0};
assign add1 = (multiplier[0] == 1'b1)? shift1 : 16'b0;
assign prod_s = add1+add2+add3+add4+add5+add6+add7+add8;
assign prod = prod_s;

endmodule
OUTPUT:
RESULT:
Thus the 8-bit signed multiplier was designed and its output was verified.

INTRODUCTION

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INTRODUCTION

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JAYARAM COLLEGE OF ENGINEERING & TECHNOLOGY

Pagalavadi, Trichirappalli – 621014.

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGG

Certified that this the bonafide record of practicals done Mr/Ms……………………………… of

Course code :………………………………….

Course name :…………………………………

Date:……………………….. H.O.D STAFF IN CHARGE

Submitted for the Anna university Practical Examination held on ………………….

EXTERNAL EXAMINER INTERNAL EXAMINER

STUDY OF SIMULATION USING VERILOG

STUDY OF SYNTHESIS TOOL

STUDY OF PLACE AND ROUTE AND

HALF ADDER USING VERILOG AND

FULL ADDER USING VERILOG MODULE

FULL SUBTRACTOR USING VERILOG

MULTIPLEXER USING VERILOG AND

DEMULTIPLEXER USING VERILOGHDL

D-FLIP FLOP USING VERILOG AND

J.K FLIP FLOP USING VERILOG

ENCODER USING VERILOG AND

4.I SERIAL IN SERIAL OUT SHIFT REGISTER

SERIAL IN PARALLEL OUT SHIFT

STUDY OF SIMULATION USING TOOLS

The acronym for EDA-electronics design automation tools.

Types of EDA tools in VLSI field are:

The process of imitating a real phenomenon with a set of mathematical formulas.

STUDY OF SYSNTHESIS USING TOOLS

Types of synthesis tool:

1. Xilinx project navigator-xilinx inc

2. Altera max plus-altera inc

4. Leonardo spectrum-mentor graphics

Introduction to project navigator(ISE)

Integrated software environment(ISE) is the Xilinx design software suite.

HDL(VHDL, verilog HDL)

Schematic design files

Converting higher level of abstraction to lower level of abstraction

Higher level-HDL language

Lower level-Equivalent gate level implementation of HDL language

PLACE, ROUTE AND BACK ANNOTATION FOR FPGA

Place and route

To study the simulation process using XILINX ISE 9.Li tool

 In the New project wizard select the following specifications.

Family spartan2 (select required family)

Device XC2S150(select required device)

Package PQ208 (select required package)

Top level source type HDL

System tool XST(VHDL/Verilog)

Program language Verilog (select required language)

 Then click Next consecutively until the coding screen appears

 Then click finish

 After that go to the Source and select Behavioural Simulation.

STEP 1: Follow steps 1 to 5 as same in VERILOG MODULE procedure.

STEP 5: Select Symbol design in source menu

STEP 7: Select Wire for connecting purpose as like here.

STEP 13: Follow steps 12 to 22 as same in VERILOG MODULE procedure.

Thus the simulation of VERILOG MODULE and SCHEMATIC PROCESS

STUDY OF SYNTHESIS TOOL

To study she synthesis process using XILINX ISE 9.1i tool.

Synthesis is an automatic method of converting a higher level abstraction to a lower

The analyzed design is synthesized to a library of components, typically gates, latch or

Schematic procedure. Then select Synthesis\Implementation in the

click the View Synthesis Report for more details.