FPGA IMPLEMENTATION OF

QPSK MODULATOR AND DEMODULATOR

Date : 06.05.09

Author : A.SURESH

Version : 2.0

1
 CHAPTER 1

AIM

The aim of the project is to design a QPSK (Quadrature Phase Shift Keying.) Modulator and
Demodulator in real. In this project we design and develop a transmitter and receiver module of a
MODEM using QPSK technique for wire and wireless networks data transmission. Generally the
Modulator at the transmitter side converts the incoming Digital information into Analog using
Carrier waves and it is transmitted through any communication medium. At receiver end
Demodulator plays its role by extracting the digital information from the incoming carrier wave.
The transmitter operates in synchronization with the receiver. The transmitter comprises of The
Shifter Unit that gets the 8 bit data, which is to be transmitted, separates that into Odd and Even
samples and segregates it as four Di bits. The Di bits are now to be given to the respective Wave
generator units. The Multiplexer unit serves as the output unit of the Modulator Section. It gives
the eight bit samples as its output. This Unit’s selection line continuously gets the input from the
shifter unit (DI-bits) and the selection line selects the corresponding wave generator unit to the
DAC to see the change of Phase shift. The demodulator consists of the Multiplier, Adder and
comparator block the first sample in each signal message is first multiplied to the first reference
signal and then added which in turn is given to comparator to find which message is in phase
with reference signal.

The VHDL coding has been written with ModelSim software and the synthesis is done using
Xilinx Project Navigator in the FPGA using the SPARTAN II Demo Board.

2
 CHAPTER 2
INTRODUCTION TO QPSK

Phase-shift keying (PSK) is a digital modulation process, which involves changing the
phase of the transmitted waveform, where each finite phase changes represent digital data.
Three common versions of PSK are binary or BPSK (M=2), quadrature or QPSK (M=4), and
8ØPSK (M=8).

Where M = 2N number of allowable phase states.

N = the number of bits needed to quantize M.

In QPSK, two orthogonal PSK signals are transmitted within the same bandwidth. Due to the
orthogonal characteristics, the signals do not interfere with each other and aid the transmission of
2 bits of data at a time.

In QPSK Modulated Wave shifts between four phases, 90° apart to create a “00”, “01” “10” or
“11”. In our project we will be using sine, cosine, inverse-sine, inverse-cosine wave. The QPSK
waveform is shown in Fig 1.1.Then this modulated wave multiplexed and then transmitted
through the channel as a analog signal. In the receiver the signal is demultiplexed and then
demodulated using so the data is retrieved.

+Y
01

00

-X +X
10

11

-Y

Fig 1 Constellation Di-bits Representation

3
 Fig 2 QPSK Waveform

Application

 QPSK is widely used in both military and commercial communication systems for
telemetry applications.

 QPSK is also very popular in high performance applications such as satellite links.

4
 CHAPTER 3

BLOCK DIAGRAM OF QPSK TRANSMITTER

Connectors:

5
3.1 BLOCKS OF QPSK

• Splitter Unit
• Address generation unit for shifter unit
• Control unit
• Multiplier unit
• Digital To Analog Interfacing Unit

3.2 QPSK Modulator

In this method, the Modulated Wave shifts between four phases each 90° apart for the Di
bits “00”, “01” “10” or “11” creating sine ,cosine ,inverse-sine and inverse-cosine
respectively .

3.2.1. Splitter Unit:

The data to be transmitted is given to the modulator input and the shifter unit gets the 32 bit
data. This data is then segregated as four Di-bits (00, 01, 10, and 11). The segregation is
based on selection input of the splitter block. The Di-bits are given to the respective Wave
Generation Unit. The selection Input of the Splitter block is controlled by the Address
Generator block. The Splitter also acts as Enable for the Multiplexer Unit of the Modulator.
Fig 3 shows Schematic diagram of Splitter

Fig 3 Schematic diagram of Splitter

6
 3.2.2. Address Generator:

AND Operation is carried out for Clock and Status signals. Status signal is the output of the
Flag signal. The output of the AND gate is given as Enable to the Address Generator, which
has Reset as the other input. The output from this unit is given as input to the Splitter. Fig 3.4
shows the Block diagram of Address Generator.

Fig 4 Address Generator

3.2.3. Control Unit:

The main aim of the Control Unit is to activate (or) deactivate the Wave Generation Unit. It
consists of four 3-Input AND gates. Among the three Inputs, one I/P will be connected to the
global Reset. The other two-control Inputs are connected with the output of Splitter block.
The selection output will select the kind of waveform to be generated. From the samples we
got from the c- code for suitable wave we will be designing an FS with 32-states to represent
the respective wave. In each state we will be forcing each of these wave samples to the
output. A handshaking signal named ‘Flag’ which will be kept low 31- States, at the last state
it is made high. This flag signal from the entire four wave generator is being OR ed and then
it is been given as a input to the enable of the Address Generator. The Flag signal which
controls the Enable pin from the entire wave generation block is ORED and then connected
to the Enable Pin of the Address Generator Block.

7
a) Sine Wave Generator

This unit generates the samples of eight-bit width continuously. When these samples are
plotted, it can be constructed into a Sine wave, which starts at zero, the sine wave is
generated for the binary Di bits 00.Fig 5 gives a Sine Wave

b) Cosine Wave Generator

This unit generates the samples of eight-bit width continuously. When these samples are
plotted, it can be constructed into a Cosine wave, which starts from Positive Maximum. The
Di bits in cosine are 01. Fig 6 shows a Cosine Wave

c) Inverse Sine Wave Generator

This unit generates the samples of eight-bit width continuously. When these samples are
plotted, it can be constructed into an Inverse Sine wave, which starts at Zero. The Di binary
bits that generate Inverse sine is 10. Fig 7 shows an Inverse Sine Wave

d) Inverse Cosine Wave Generator

This unit generates the samples of eight-bit width continuously. When these samples are
plotted, it can be constructed into an Inverse Cosine wave, which starts from Negative
Maximum. Di bits in Inverse cosine are 11. Fig 3.8 shows an Inverse Cosine Wave

8
Fig 5 Sine Wave Fig 6 Cosine Wave

9
 Fig 7 Inverse-Sine Wave Fig 8 Inverse-Cosine Wave

Samples for Sine Wave Generator Unit:

The samples for the sine wave is generated using the equation

X (n) = sin wt

Where w – Angular Frequency (2Πfm)

10
fm = message frequency

t = N ts

N = number of samples, ts = sampling time

Where fs – Sampling Frequency (1/ts )

No of samples per cycle:

fs Samples / sec = 8000 = 32 samples/cycles

fm cycles / sec 250

C-Code is implemented to generate the various samples using the equations

X (n) = sin 2п fm . N (for sine wave)

fs

X (n) = cosine 2п fm . N (for cosine wave)

fs

X (n) = inverse sine 2п fm .N (for Inv-sine wave)

fs

X (n) = inverse cosine 2п fm . N (for Inv-cosine wave)

fs

11
 Table 1 Wave Generations

Waveform Sine Wave Cosine Wave Inv-sine Wave Inv-cos

Wave

Sample 1 00 7f 00 80

Sample 2 5a 5a a5 a5

Sample 3 7f 00 80 00

Sample 4 5a a5 a5 5a

Sample 5 00 80 00 7f

Sample 6 a5 a5 5a 5a

Sample 7 80 00 7f 00

Sample 8 a5 5a 5a a5

Table 2 Samples Of Generated waves

3.2.4 Multiplexer Unit:

The Multiplexer unit serves as the output unit of the modulator section. It gives the input
samples from the wave generation unit as its input. This unit’s selection line continuously
12
gets the input from the shifter unit flag, this initiates the multiplexer to select which input
from the wave generator .The selected input is then given to the input the digital to analog
converter .The multiplexer used here is a 4:1 multiplexer so four inputs are given as the
input, the input is of 8 bit length .There is only one output of 8 bit length .The selection line
is of two bit.

3.2.5 Digital to Analog Converter (DAC):

The 8-bit digital data from the Multiplexer Unit to Analog Data is done using Digital to
Analog Converter. The DAC unit consists of a d-flip flop and an AND gate. The inputs the
flip-flop are the reset and clock. The given data and the output of d-flip flop are given to the
AND gate. Only when both reset and data are present there is an output from digital to
analog converter. The output thus got is sent through a transmitting channel. Fig 9 shows the
Analog to Digital Converter.

Fig 9 Digital to Analog Converter

13
 CHAPTER 4

DESIGN OF QPSK RECEIVER

Blocks Involved

Modulated output is received at the receiver end, where demodulation of the signal occurs.
The blocks involved at the Demodulator section are

• ADC Interfacing block

• Multiplier block
• Comparator block
• Counter block

Fig 10 QPSK Receiver block

4.1. ANALOG TO DIGITAL CONVERTOR

14
The ADC performs the reverse operation of the DAC already used .The ADC chip is needed
to be activated when the chip select signal is enabled. Thus when its activated the activated
the output of ADC is digital sequence of the analog input received.

Fig 11 Analog Digital Converter

4.2. MULTIPLIER

Fig 12 Multiplier

15
The 64-bit output signal from the ADC is given as the input to the sine wave, cosine wave,
inverse sine wave and inverse cosine wave multiplier respectively. These multipliers perform
the function of multiplying these values with the inbuilt hexadecimal values. Thus we get 8-
bit values as output which is given to the sine, cosine, inverse sine and inverse cosine adder.
Thus the output we get from the multiplier block is a 16-bit signal.

4.3. COMPARATOR

Fig 13 Comparator block

The comparator compares the samples of the incoming 8 bit first sample of the wave with
that of the samples of the wave pre-generated to it as Sine, Cosine, Inverse sine and Inverse
cosine. If the values are satisfied for a particular wave, then the comparator sends the data as
its output. This output is needed to be maintained for next 8 clocking samples as the output
has already been determined and next input is at the eighth clock pulse. Hence a delay circuit
is created and this demodulated output for each wave is maintained at the output port. This
output for each input is obtained at a two port and it can be configured to obtain output at
different ports for specific purpose. The delay circuit waits for every 8th clock pulse of the
sampling frequency and sends the output to the demodulator‘s output port accordingly.

16
4.4. COUNTER

It has a global clock and global reset as input signals. The main input signal is
the 2 bit output from comparator. The 8 bit signal which is thus obtained is stored in the
temporary register. The 8-bit sequence is then pushed out.

Fig 14 Counter Block

17
 CHAPTER 5

IMPLEMENTATION IN REAL TIME

SOFTWARE DESCRIPTION

1) Transmitter Section

Fig 15 Hierarchy for Transmitter Section

Fig 16 Hierarchy for Receiver Section

18
VERIFICATION:

STEPS INVOLVED: [FOR TRANSMITTER SECTION]

1. Compile the .V (Verilog) files in the order mentioned above.

2. Simulate the Test bench top_qpsk_tb.v (Transmitter)

3. You can get the FIG.20 in the Modelsim window. Expand all the Hierarchy levels as shown in
that figure.

4. Now select dut: top_qpsk_tb in the same figure. Right click and Add to wave. Run for 700
ns.The output of the Modulator is obtained which is shown in the FIG.20.

Fig 20: Simulation Output of Transmitter Section

19
STEPS INVOLVED: [FOR RECEIVER SECTION]

1. Compile the .V (Verilog) files in the order mentioned above.

2. Simulate the Test bench top_qpsk_rx_tb.v

3. You can get the FIG.21 in the Modelsim window. Expand all the Hierarchy levels as shown in
that figure.

4. Now select dut: top_qpsk_rx_tb in the same figure. Right click and Add to wave. Run for
700 ns.The output of the Modulator is obtained which is shown in the FIG.21.

Fig 21 : Simulation Output Of Receiver Module

20
Implementation
Connect the FPGA Trainer kit using RS-232 cable with PC, Check for SSSSSS.. in
theTerminal Mode of SANDS IDE.

For Analyzing Transmitter Output follow the steps listed below :

Step 1:
View the Terminal Window

21
Step 2 :

Check whether sssss… coming in Terminal window,if you are not getting then check
your Baud Rate,COM Port connections.

22
Step 3:

Download the HEX file of DSSS Transmitter / DSSS Receiver

Click Operations Spartan II  Program

Then select the Hex to be configured.

Step 4:

Once the configuration of Spartan II is completed you will get a message as “FPGA
CONFIGURED” in SANDS IDE as shown in the below figure :
23
Step 5:

Check whether the DONE pin glows in the kit. If not, configure the FPGA once again.

Step 6:

Give the 8-bit Input to the FPGA using DIP-Switches available in the trainer kit [IN1 – IN 8].

Step 7:

Connect the CRO probes one end to the output of the kit and the other end to ground.

Step 8:

Enable the clock input by switching ON the clock pin 1of S1 in the kit.

24
Step 9:

Now you can view the phase shifted output of DSSS Transmitter section in the CRO.

For Analyzing Receiver Output follow the steps listed below:

Step 1:

Download the HEX file according to the procedures given above for Transmitter section
[From Step 1 to Step 5].

Step 2:

Enable the clock input by switching ON the clock pin 1of S1 in the kit.

Step 3:

Now you can see the Analog to Digital information Output can be viewed at the Output Led
from OP-1 to OP-8.

25
 CHAPTER 6

CONCLUSION & FUTURE ENHANCEMENT

QPSK Modulation and Demodulation can be applied in any field where we want to modulate the
data into another form for security purpose. It is mainly used in military application where we
have to be safe in letting out our datas.We can use this in any other purposes where we have to
keep our data safe in order to prevent hackers to know our secrets.

The conclusion is that we have got the output for QPSK Modulation in real time but not for
Demodulation. If we get the output for demodulation then it will really be a wonderful job
because if we get the output in real time we can use it for product development.

We were not able to get the real time output for demodulation because of the loop back problem.
In future if we are able to solve it we will be able to show the output for demodulation also. If we
show the output for demodulation then we can use the combined MODEM for any other real
time purpose.

26
Bill of Materials:

Component Package Specifications Make Quantity

Spartan II Kit SANDS 1

Power cord, SANDS Each 1

Communication
Cable

HO
W TO OPERATE

2) Enter the program in the VHDL and save it and then compile it.
3) Connect the kit spartan2.
4) Connect the power supply(5v) to the kit.
5) Then switch on the power supply.
6) Then click the pc term to run the program and see the waveform.
7) Then go to the IS E software and synthesis the program.
8) Connect the kit with JTAG.
9) Then the program will download to the kit and arithmetic operation
will perform.
10)The kit contains three ports . There will be Port B ,port C, Port D.

27
 11)The inputs are given to these ports the output will be depending
upon the operation.

TROUBLE SHOOTING:

PROBLEM IDENTIFICATION HOW TO SOLVE?

Power Supply Led is not Led will be in Off condition 1.Check the Power Chord
Glow Given to your KIT.

2.Check the Having the

Voltage of 1.5 to 3.5 .

3.Change The Power

supply

Unspecified error in Mapping error or 1.Check the UCF File

mapping due to port pins Translational error Whether having Input or
output pin (Its because of
Port pins are Dual side)

Kit is not Working Power Led will be in Off 1.Check the Power Chord
condition Given to your KIT.

2.Change The Power

supply

APPENDIX
28
 A) Codings Of Transmitter Section:

1) Top Level Of Transmitter :

//TopModule

module top_qpsk(
input sys_clk1 ,
input sys_rst ,
input [7:0]message ,
output cs,
output [7:0]dac_data
//output [7:0]modulated_op
);

wire f1,f2,f3,f4;
wire en;
wire [1:0]to_mux_sel;
wire [1:0]w;
wire [7:0]op1,op2,op3,op4;
wire [7:0]modulated_op;

wire and_sin,and_cos,and_inv_cos,and_inv_sin;
wire sys_clk;

assign and_sin = (sys_rst & ~w[1] & ~w[0]);

assign and_cos = (sys_rst & ~w[1] & w[0]);
assign and_inv_cos = (sys_rst & w[1] & w[0]);
assign and_inv_sin = (sys_rst & w[1] & ~w[0]);

assign en = (f1 | f2 | f3 | f4);

cos_wave1 a1(.clk(sys_clk),.rst(and_cos),.out2(op2),.fg1(f1));

inv_cos_wave1 a2(.clk(sys_clk),.rst(and_inv_cos),.out2(op4),.fg1(f2));

inv_sin_wave1 a3(.clk(sys_clk),.rst(and_inv_sin),.out2(op3),.fg1(f3));

sine_wave1 a4(.clk(sys_clk),.rst(and_sin),.out1(op1),.fg2(f4));

clock_div a8(.clockoutput(sys_clk),.clock(sys_clk1),.rst(sys_rst));

dac_intr
a9(.clk(sys_clk),.rst(sys_rst),.data_in(modulated_op),.cs(cs),.data(dac_data)
);

counter a5(
.cnt_clk(sys_clk) ,
.cnt_rst(sys_rst) ,
.en1(en),
.cnt_out(to_mux_sel)
);

mux_8_1 a6(
.ip_value(message) ,
29
 .sel(to_mux_sel) ,
.op_bit(w)
);

op_sel_mux a7(
.sin_sample(op1) ,
.cos_sample(op2),
.Inv_sin_sample(op3) ,
.Inv_cos_sample(op4) ,
.sample_sel(w),
.op_sample(modulated_op)
);

endmodule

2) Coding For Address Generator :

//Address Generator

module counter(
input cnt_clk ,
input cnt_rst ,
input en1,
output reg [1:0]cnt_out
);

always@(posedge cnt_clk or negedge cnt_rst)

if(!cnt_rst)
cnt_out <= 2'd0;
else if(en1==1'b1)
cnt_out <= cnt_out + 2'd1;

endmodule

3)Coding For Splitter Unit :

//8:1 Mux Design

module mux_8_1(
input [7:0]ip_value ,
input [1:0]sel ,
output reg [1:0]op_bit
);

always @(sel,ip_value)
begin
case(sel)

2'b00:op_bit <= ip_value[1:0];

2'b01:op_bit <= ip_value[3:2];
2'b10:op_bit <= ip_value[5:4];
2'b11:op_bit <= ip_value[7:6];
default : op_bit <= 2'bzz;

30
 endcase
end

endmodule

4)Coding For Output Selection MUX Unit

//8:1 Mux Design

module mux_8_1(
input [7:0]ip_value ,
input [1:0]sel ,
output reg [1:0]op_bit
);

always @(sel,ip_value)
begin
case(sel)

2'b00:op_bit <= ip_value[1:0];

2'b01:op_bit <= ip_value[3:2];
2'b10:op_bit <= ip_value[5:4];
2'b11:op_bit <= ip_value[7:6];
default : op_bit <= 2'bzz;

endcase
end

endmodule

5) FSM to Generate SINE wave

//Module to Generate Sine Wave

module sine_wave1(clk,rst,out1,fg2);
input clk,rst;
output [7:0]out1;
output fg2;
reg [7:0]out1;
reg fg2;

parameter reset='d00, s0='d01, s1='d02, s2='d03, s3='d04, s4='d05, s5='d06,

s6='d07, s7='d08, s8='d09, s9='d10,

s10='d11,s11='d12,s12='d13,s13='d14,s14='d15,s15='d16,s16='d17,s17='d18,s18='
d19,s19='d20,

s20='d21,s21='d22,s22='d23,s23='d24,s24='d25,s25='d26,s26='d27,s27='d28,s28='
d29,s29='d30,

s30='d31,s31='d32;

31
reg [5:0]ps,ns;

//wire r1;
//clock_div t1(.clockoutput(r1),.clock(clk),.rst(rst));

always@(posedge clk,negedge rst)

begin
if(!rst)
begin
ps<=s0;

end

else
begin
ps<=ns;

end

end

always@(ps,rst)
begin
case(ps)

s0: begin
out1<= 8'h00;
if(!rst)
ns<= s0; // make this change in all
else
begin
ns<=s1;
fg2<=1'b0;
end
end

s1: begin
out1<= 8'h0c;
if(!rst)
ns<= s0;
else
begin
ns<=s2;
fg2<=1'b0;
end
end

s2: begin
out1<= 8'h18;
if(!rst)

32
 ns<= s0;
else
begin
ns<=s3;
fg2<=1'b0;
end
end

s3: begin
out1<= 8'h23;
if(!rst)
ns<= s0;
else
begin
ns<=s4;
fg2<=1'b0;
end
end
s4: begin
out1<= 8'h2d;
if(!rst)
ns<= s0;
else
begin
ns<=s5;
fg2<=1'b0;
end
end

s5: begin
out1<= 8'h35;
if(!rst)
ns<= s0;
else
begin
ns<=s6;
fg2<=1'b0;
end
end

s6: begin
out1<= 8'h3b;
if(!rst)
ns<= s0;
else
begin
ns<=s7;
fg2<=1'b0;
end
end

s7: begin
out1<= 8'h3e;
if(!rst)
ns<= s0;
else

33
 begin
fg2<=1'b0;
ns<=s8;
end
end
s8: begin
out1<= 8'h3f;
if(!rst)
ns<= s0;
else
begin
ns<=s9;
fg2<=1'b0;
end
end

s9: begin
out1<= 8'h3e;
if(!rst)
ns<= s0;
else
begin
ns<=s10;
fg2<=1'b0;
end
end

s10: begin
out1<= 8'h3b;
if(!rst)
ns<= s0;
else
begin
ns<=s11;
fg2<=1'b0;
end
end

s11: begin
out1<= 8'h35;
if(!rst)
ns<= s0;
else
begin
ns<=s12;
fg2<=1'b0;
end
end
s12: begin
out1<= 8'h2d;
if(!rst)
ns<= s0;
else
begin
ns<=s13;
fg2<=1'b0;

34
 end
end

s13: begin
out1<= 8'h23;
if(!rst)
ns<= s0;
else
begin
ns<=s14;
fg2<=1'b0;
end
end

s14: begin
out1<= 8'h18;
if(!rst)
ns<= s0;
else
begin
ns<=s15;
fg2<=1'b0;
end
end

s15: begin
out1<= 8'h0c;
if(!rst)
ns<= s0;
else
begin
ns<=s16;
fg2<=1'b0;
end
end
s16: begin
out1<= 8'h00;
if(!rst)
ns<= s0;
else
begin
ns<=s17;
fg2<=1'b0;
end
end

s17: begin
out1<= 8'hf3;
if(!rst)
ns<= s0;
else
begin
ns<=s18;
fg2<=1'b0;
end
end

35
 s18: begin
out1<= 8'he7;
if(!rst)
ns<= s0;
else
begin
ns<=s19;
fg2<=1'b0;
end
end

s19: begin
out1<= 8'hdc;
if(!rst)
ns<= s0;
else
begin
ns<=s20;
fg2<=1'b0;
end
end
s20: begin
out1<= 8'hd2;
if(!rst)
ns<= s0;
else
begin
ns<=s21;
fg2<=1'b0;
end
end

s21: begin
out1<= 8'hca;
if(!rst)
ns<= s0;
else
begin
ns<=s22;
fg2<=1'b0;
end
end

s22: begin
out1<= 8'hc4;
if(!rst)
ns<= s0;
else
begin
ns<=s23;
fg2<=1'b0;
end
end

s23: begin

36
 out1<=8'hc1;
if(!rst)
ns<= s0;
else
begin
ns<=s24;
fg2<=1'b0;
end
end
s24: begin
out1<= 8'hc0;
if(!rst)
ns<= s0;
else
begin
ns<=s25;
fg2<=1'b0;
end
end

s25: begin
out1<= 8'hc1;
if(!rst)
ns<= s0;
else
begin
ns<=s26;
fg2<=1'b0;
end
end

s26: begin
out1<= 8'hc4;
if(!rst)
ns<= s0;
else
begin
ns<=s27;
fg2<=1'b0;
end
end

s27: begin
out1<= 8'hca;
if(!rst)
ns<= s0;
else
begin
ns<=s28;
fg2<=1'b0;
end
end
s28: begin
out1<= 8'hd2;
if(!rst)
ns<= s0;

37
 else
begin
ns<=s29;
fg2<=1'b0;
end
end

s29: begin
out1<= 8'hdc;
if(!rst)
ns<= s0;
else
begin
ns<=s30;
fg2<=1'b0;
end
end

s30: begin
out1<= 8'he7;
if(!rst)
ns<= s0;
else
begin
ns<=s31;
fg2<=1'b0;
end
end

s31: begin
out1<= 8'hf3;
if(!rst)
ns<= s0;
else
begin
ns<=s0;
fg2<=1'b1;
end
end

default: begin
out1<= 8'h00;
if(!rst)
ns<= s0;
else
begin
ns<=s0;
fg2<=1'b0;
end
end

endcase
end

endmodule

38
6)FSM to Generate COSINE wave :

module cos_wave1(clk,rst,out2,fg1);
input clk,rst;
output [7:0]out2;
output fg1;
reg [7:0]out2;
reg fg1;
parameter reset='d00, s0='d01, s1='d02, s2='d03, s3='d04, s4='d05, s5='d06,
s6='d07, s7='d08, s8='d09, s9='d10,

s10='d11,s11='d12,s12='d13,s13='d14,s14='d15,s15='d16,s16='d17,s17='d18,s18='
d19,s19='d20,

s20='d21,s21='d22,s22='d23,s23='d24,s24='d25,s25='d26,s26='d27,s27='d28,s28='
d29,s29='d30,

s30='d31,s31='d32;
reg [5:0]ps,ns;

//wire r1;
//clock_div t1(.clockoutput(r1),.clock(clk),.rst(rst));

always@(posedge clk,negedge rst)

begin
if(!rst)
begin
ps<=s0;

end

else
begin
ps<=ns;

end

end

always@(ps,rst)
begin
case(ps)

s0: begin

39
 out2<= 8'h3f;
if(!rst)
ns<= s0;
else
begin
ns<=s1;
fg1<=1'b0;
end
end

s1: begin
out2<= 8'h3e;
if(!rst)
ns<= s0;
else
begin
ns<=s2;
fg1<=1'b0;
end
end

s2: begin
out2<= 8'h3b;
if(!rst)
ns<= s0;
else
begin
ns<=s3;
fg1<=1'b0;
end
end

s3: begin
out2<= 8'h35;
if(!rst)
ns<= s0;
else
begin
ns<=s4;
fg1<=1'b0;
end
end
s4: begin
out2<= 8'h2d;
if(!rst)
ns<= s0;
else
begin
ns<=s5;
fg1<=1'b0;
end
end

s5: begin
out2<= 8'h23;
if(!rst)

40
 ns<= s0;
else
begin
ns<=s6;
fg1<=1'b0;
end
end

s6: begin
out2<= 8'h18;
if(!rst)
ns<= s0;
else
begin
ns<=s7;
fg1<=1'b0;
end
end

s7: begin
out2<= 8'h0c;
if(!rst)
ns<= s0;
else
begin
fg1<=1'b0;
ns<=s8;
end
end
s8: begin
out2<= 8'h00;
if(!rst)
ns<= s0;
else
begin
ns<=s9;
fg1<=1'b0;
end
end

s9: begin
out2<= 8'hf3;
if(!rst)
ns<= s0;
else
begin
ns<=s10;
fg1<=1'b0;
end
end

s10: begin
out2<= 8'he7;
if(!rst)
ns<= s0;
else

41
 begin
ns<=s11;
fg1<=1'b0;
end
end

s11: begin
out2<= 8'hdc;
if(!rst)
ns<= s0;
else
begin
ns<=s12;
fg1<=1'b0;
end
end
s12: begin
out2<= 8'hd2;
if(!rst)
ns<= s0;
else
begin
ns<=s13;
fg1<=1'b0;
end
end

s13: begin
out2<= 8'hca;
if(!rst)
ns<= s0;
else
begin
ns<=s14;
fg1<=1'b0;
end
end

s14: begin
out2<= 8'hc4;
if(!rst)
ns<= s0;
else
begin
ns<=s15;
fg1<=1'b0;
end
end

s15: begin
out2<= 8'hc1;
if(!rst)
ns<= s0;
else
begin
ns<=s16;

42
 fg1<=1'b0;
end
end
s16: begin
out2<= 8'hc0;
if(!rst)
ns<= s0;
else
begin
ns<=s17;
fg1<=1'b0;
end
end

s17: begin
out2<= 8'hc1;
if(!rst)
ns<= s0;
else
begin
ns<=s18;
fg1<=1'b0;
end
end

s18: begin
out2<= 8'hc4;
if(!rst)
ns<= s0;
else
begin
ns<=s19;
fg1<=1'b0;
end
end

s19: begin
out2<= 8'hca;
if(!rst)
ns<= s0;
else
begin
ns<=s20;
fg1<=1'b0;
end
end
s20: begin
out2<= 8'hd2;
if(!rst)
ns<= s0;
else
begin
ns<=s21;
fg1<=1'b0;
end
end

43
s21: begin
out2<= 8'hdc;
if(!rst)
ns<= s0;
else
begin
ns<=s22;
fg1<=1'b0;
end
end

s22: begin
out2<= 8'he7;
if(!rst)
ns<= s0;
else
begin
ns<=s23;
fg1<=1'b0;
end
end

s23: begin
out2<=8'hf3;
if(!rst)
ns<= s0;
else
begin
ns<=s24;
fg1<=1'b0;
end
end
s24: begin
out2<= 8'h00;
if(!rst)
ns<= s0;
else
begin
ns<=s25;
fg1<=1'b0;
end
end

s25: begin
out2<= 8'h0c;
if(!rst)
ns<= s0;
else
begin
ns<=s26;
fg1<=1'b0;
end
end

s26: begin

44
 out2<= 8'h18;
if(!rst)
ns<= s0;
else
begin
ns<=s27;
fg1<=1'b0;
end
end

s27: begin
out2<= 8'h23;
if(!rst)
ns<= s0;
else
begin
ns<=s28;
fg1<=1'b0;
end
end
s28: begin
out2<= 8'h2d;
if(!rst)
ns<= s0;
else
begin
ns<=s29;
fg1<=1'b0;
end
end

s29: begin
out2<= 8'h35;
if(!rst)
ns<= s0;
else
begin
ns<=s30;
fg1<=1'b0;
end
end

s30: begin
out2<= 8'h3b;
if(!rst)
ns<= s0;
else
begin
ns<=s31;
fg1<=1'b0;
end
end

s31: begin
out2<= 8'h3e;
if(!rst)

45
 ns<= s0;
else
begin
ns<=s0;
fg1<=1'b1;
end
end

default: begin
out2<= 8'h3f;
if(!rst)
ns<= s0;
else
begin
ns<=s0;
fg1<=1'b0;
end
end

endcase
end

endmodule

7)FSM to Generate Inverse Sine Wave :

module inv_sin_wave1(clk,rst,out2,fg1);
input clk,rst;
output [7:0]out2;
output fg1;
reg [7:0]out2;
reg fg1;
parameter reset='d00, s0='d01, s1='d02, s2='d03, s3='d04, s4='d05, s5='d06,
s6='d07, s7='d08, s8='d09, s9='d10,

s10='d11,s11='d12,s12='d13,s13='d14,s14='d15,s15='d16,s16='d17,s17='d18,s18='
d19,s19='d20,

s20='d21,s21='d22,s22='d23,s23='d24,s24='d25,s25='d26,s26='d27,s27='d28,s28='
d29,s29='d30,

s30='d31,s31='d32;
reg [5:0]ps,ns;

//wire r1;
//clock_div t1(.clockoutput(r1),.clock(clk),.rst(rst));

always@(posedge clk,negedge rst)

begin
if(!rst)
begin
ps<=s0;

46
 end

else
begin
ps<=ns;

end

end

always@(ps,rst)
begin
case(ps)

s0: begin
out2<= 8'h00;
if(!rst)
ns<= s0;
else
begin
ns<=s1;
fg1<=1'b0;
end
end

s1: begin
out2<= 8'hF3;
if(!rst)
ns<= s0;
else
begin
ns<=s2;
fg1<=1'b0;
end
end

s2: begin
out2<= 8'hE7;
if(!rst)
ns<= s0;
else
begin
ns<=s3;
fg1<=1'b0;
end
end

s3: begin
out2<= 8'hDC;
if(!rst)
ns<= s0;

47
 else
begin
ns<=s4;
fg1<=1'b0;
end
end
s4: begin
out2<= 8'hD2;
if(!rst)
ns<= s0;
else
begin
ns<=s5;
fg1<=1'b0;
end
end

s5: begin
out2<= 8'hCA;
if(!rst)
ns<= s0;
else
begin
ns<=s6;
fg1<=1'b0;
end
end

s6: begin
out2<= 8'hC4;
if(!rst)
ns<= s0;
else
begin
ns<=s7;
fg1<=1'b0;
end
end

s7: begin
out2<= 8'hC1;
if(!rst)
ns<= s0;
else
begin
fg1<=1'b0;
ns<=s8;
end
end
s8: begin
out2<= 8'hC0;
if(!rst)
ns<= s0;
else
begin
ns<=s9;

48
 fg1<=1'b0;
end
end

s9: begin
out2<= 8'hC1;
if(!rst)
ns<= s0;
else
begin
ns<=s10;
fg1<=1'b0;
end
end

s10: begin
out2<= 8'hC4;
if(!rst)
ns<= s0;
else
begin
ns<=s11;
fg1<=1'b0;
end
end

s11: begin
out2<= 8'hCA;
if(!rst)
ns<= s0;
else
begin
ns<=s12;
fg1<=1'b0;
end
end
s12: begin
out2<= 8'hD2;
if(!rst)
ns<= s0;
else
begin
ns<=s13;
fg1<=1'b0;
end
end

s13: begin
out2<= 8'hDC;
if(!rst)
ns<= s0;
else
begin
ns<=s14;
fg1<=1'b0;
end

49
 end

s14: begin
out2<= 8'hE7;
if(!rst)
ns<= s0;
else
begin
ns<=s15;
fg1<=1'b0;
end
end

s15: begin
out2<= 8'hF3;
if(!rst)
ns<= s0;
else
begin
ns<=s16;
fg1<=1'b0;
end
end
s16: begin
out2<= 8'h00;
if(!rst)
ns<= s0;
else
begin
ns<=s17;
fg1<=1'b0;
end
end

s17: begin
out2<= 8'h0C;
if(!rst)
ns<= s0;
else
begin
ns<=s18;
fg1<=1'b0;
end
end

s18: begin
out2<= 8'h18;
if(!rst)
ns<= s0;
else
begin
ns<=s19;
fg1<=1'b0;
end
end

50
s19: begin
out2<= 8'h23;
if(!rst)
ns<= s0;
else
begin
ns<=s20;
fg1<=1'b0;
end
end
s20: begin
out2<= 8'h2D;
if(!rst)
ns<= s0;
else
begin
ns<=s21;
fg1<=1'b0;
end
end

s21: begin
out2<= 8'h35;
if(!rst)
ns<= s0;
else
begin
ns<=s22;
fg1<=1'b0;
end
end

s22: begin
out2<= 8'h3B;
if(!rst)
ns<= s0;
else
begin
ns<=s23;
fg1<=1'b0;
end
end

s23: begin
out2<=8'h3E;
if(!rst)
ns<= s0;
else
begin
ns<=s24;
fg1<=1'b0;
end
end
s24: begin
out2<= 8'h3F;
if(!rst)

51
 ns<= s0;
else
begin
ns<=s25;
fg1<=1'b0;
end
end

s25: begin
out2<= 8'h3E;
if(!rst)
ns<= s0;
else
begin
ns<=s26;
fg1<=1'b0;
end
end

s26: begin
out2<= 8'h3B;
if(!rst)
ns<= s0;
else
begin
ns<=s27;
fg1<=1'b0;
end
end

s27: begin
out2<= 8'h35;
if(!rst)
ns<= s0;
else
begin
ns<=s28;
fg1<=1'b0;
end
end
s28: begin
out2<= 8'h2d;
if(!rst)
ns<= s0;
else
begin
ns<=s29;
fg1<=1'b0;
end
end

s29: begin
out2<= 8'h23;
if(!rst)
ns<= s0;
else

52
 begin
ns<=s30;
fg1<=1'b0;
end
end

s30: begin
out2<= 8'h18;
if(!rst)
ns<= s0;
else
begin
ns<=s31;
fg1<=1'b0;
end
end

s31: begin
out2<= 8'h0C;
if(!rst)
ns<= s0;
else
begin
ns<=s0;
fg1<=1'b1;
end
end

default: begin
out2<= 8'h00;
if(!rst)
ns<= s0;
else
begin
ns<=s0;
fg1<=1'b0;
end
end

endcase
end

endmodule

8)FSM to Generate Inverse Cosine Wave :

module inv_cos_wave1(clk,rst,out2,fg1);
input clk,rst;
output [7:0]out2;
output fg1;
reg [7:0]out2;
reg fg1;
parameter reset='d00, s0='d01, s1='d02, s2='d03, s3='d04, s4='d05, s5='d06,
s6='d07, s7='d08, s8='d09, s9='d10,

53
s10='d11,s11='d12,s12='d13,s13='d14,s14='d15,s15='d16,s16='d17,s17='d18,s18='
d19,s19='d20,

s20='d21,s21='d22,s22='d23,s23='d24,s24='d25,s25='d26,s26='d27,s27='d28,s28='
d29,s29='d30,

s30='d31,s31='d32;
reg [5:0]ps,ns;

//wire r1;
//clock_div t1(.clockoutput(r1),.clock(clk),.rst(rst));

always@(posedge clk,negedge rst)

begin
if(!rst)
begin
ps<=s0;

end

else
begin
ps<=ns;

end

end

always@(ps,rst)
begin
case(ps)

s0: begin
out2<= 8'hc1;
if(!rst)
ns<= s0;
else
begin
ns<=s1;
fg1<=1'b0;
end
end

s1: begin
out2<= 8'hc0;
if(!rst)
ns<= s0;
else
begin

54
 ns<=s2;
fg1<=1'b0;
end
end

s2: begin
out2<= 8'hc1;
if(!rst)
ns<= s0;
else
begin
ns<=s3;
fg1<=1'b0;
end
end

s3: begin
out2<= 8'hC4;
if(!rst)
ns<= s0;
else
begin
ns<=s4;
fg1<=1'b0;
end
end
s4: begin
out2<= 8'hCA;
if(!rst)
ns<= s0;
else
begin
ns<=s5;
fg1<=1'b0;
end
end

s5: begin
out2<= 8'hD2;
if(!rst)
ns<= s0;
else
begin
ns<=s6;
fg1<=1'b0;
end
end

s6: begin
out2<= 8'hDC;
if(!rst)
ns<= s0;
else
begin
ns<=s7;
fg1<=1'b0;

55
 end
end

s7: begin
out2<= 8'hE7;
if(!rst)
ns<= s0;
else
begin
fg1<=1'b0;
ns<=s8;
end
end
s8: begin
out2<= 8'hF3;
if(!rst)
ns<= s0;
else
begin
ns<=s9;
fg1<=1'b0;
end
end

s9: begin
out2<= 8'h00;
if(!rst)
ns<= s0;
else
begin
ns<=s10;
fg1<=1'b0;
end
end

s10: begin
out2<= 8'h0C;
if(!rst)
ns<= s0;
else
begin
ns<=s11;
fg1<=1'b0;
end
end

s11: begin
out2<= 8'h18;
if(!rst)
ns<= s0;
else
begin
ns<=s12;
fg1<=1'b0;
end
end

56
 s12: begin
out2<= 8'h23;
if(!rst)
ns<= s0;
else
begin
ns<=s13;
fg1<=1'b0;
end
end

s13: begin
out2<= 8'h2D;
if(!rst)
ns<= s0;
else
begin
ns<=s14;
fg1<=1'b0;
end
end

s14: begin
out2<= 8'h35;
if(!rst)
ns<= s0;
else
begin
ns<=s15;
fg1<=1'b0;
end
end

s15: begin
out2<= 8'h3B;
if(!rst)
ns<= s0;
else
begin
ns<=s16;
fg1<=1'b0;
end
end
s16: begin
out2<= 8'h3E;
if(!rst)
ns<= s0;
else
begin
ns<=s17;
fg1<=1'b0;
end
end

s17: begin
out2<= 8'h3F;

57
 if(!rst)
ns<= s0;
else
begin
ns<=s18;
fg1<=1'b0;
end
end

s18: begin
out2<= 8'h3E;
if(!rst)
ns<= s0;
else
begin
ns<=s19;
fg1<=1'b0;
end
end

s19: begin
out2<= 8'h3B;
if(!rst)
ns<= s0;
else
begin
ns<=s20;
fg1<=1'b0;
end
end
s20: begin
out2<= 8'h35;
if(!rst)
ns<= s0;
else
begin
ns<=s21;
fg1<=1'b0;
end
end

s21: begin
out2<= 8'h2D;
if(!rst)
ns<= s0;
else
begin
ns<=s22;
fg1<=1'b0;
end
end

s22: begin
out2<= 8'h23;
if(!rst)
ns<= s0;

58
 else
begin
ns<=s23;
fg1<=1'b0;
end
end

s23: begin
out2<=8'h18;
if(!rst)
ns<= s0;
else
begin
ns<=s24;
fg1<=1'b0;
end
end
s24: begin
out2<= 8'h0C;
if(!rst)
ns<= s0;
else
begin
ns<=s25;
fg1<=1'b0;
end
end

s25: begin
out2<= 8'h00;
if(!rst)
ns<= s0;
else
begin
ns<=s26;
fg1<=1'b0;
end
end

s26: begin
out2<= 8'hF3;
if(!rst)
ns<= s0;
else
begin
ns<=s27;
fg1<=1'b0;
end
end

s27: begin
out2<= 8'hE7;
if(!rst)
ns<= s0;
else
begin

59
 ns<=s28;
fg1<=1'b0;
end
end
s28: begin
out2<= 8'hDc;
if(!rst)
ns<= s0;
else
begin
ns<=s29;
fg1<=1'b0;
end
end

s29: begin
out2<= 8'hD2;
if(!rst)
ns<= s0;
else
begin
ns<=s30;
fg1<=1'b0;
end
end

s30: begin
out2<= 8'hCA;
if(!rst)
ns<= s0;
else
begin
ns<=s31;
fg1<=1'b0;
end
end

s31: begin
out2<= 8'hC4;
if(!rst)
ns<= s0;
else
begin
ns<=s0;
fg1<=1'b1;
end
end

default: begin
out2<= 8'hc1;
if(!rst)
ns<= s0;
else
begin
ns<=s0;
fg1<=1'b0;

60
 end
end

endcase
end

endmodule

9) Coding for DAC Interface

module dac_intr(clk,rst,data_in,cs,data);

input clk;
input rst;
input [7:0]data_in;
output cs;
output [7:0]data;

wire [7:0]data;
//reg [7:0]data;
reg cs;

reg [7:0]data_sig;

parameter a=1'b0,b=1'b1;
reg ps,ns;

//assign data=data_sig+8'h80;

//assign data=data_sig+8'h80;

assign data ={~(data_sig[7]),data_sig[6:0]};

always@(posedge clk or negedge rst)
begin
if (rst==1'b0)
ps<=a;
else
ps<=ns;

61
 end

always@(ps or data_in or rst)

begin
case(ps)
a:
begin
data_sig<=8'b00000000;
cs <=1'b0;
if(rst ==1'b0)
ns <= a;
else
ns <= b;
end

b:
begin
data_sig <= data_in;
cs <=1'b1;
if(rst ==1'b0)
ns <= a;
else
ns <= b;
end

endcase
end
endmodule

B) CODINGS FOR RECEIVER SECTION

1)Top Level Module for Receiver Section :

//Toplevel for all the blocks

module top_qpsk_rx(
input sys_clk1,
input sys_rst,
output [7:0]final_data
);

wire [63:0]int_samp;
wire [16:0]int_sine;
wire [16:0]int_cos;
wire [16:0]int_inv_sine;
wire [16:0]int_inv_cos;
wire [1:0]value;
wire sys_clk;

clock_div a0(.clockoutput(sys_clk), .clock(sys_clk1),.rst(sys_rst));

from_adc a1(
.clk(sys_clk),
.rst(sys_rst),
.sample(int_samp)
62
 );

multiplier a2(
.ip_sample(int_samp),
.op_sine(int_sine),
.op_cos(int_cos),
.op_inv_sine(int_inv_sine),
.op_inv_cos(int_inv_cos)
);

comparator a3(
.from_sine(int_sine),
.from_cos(int_cos),
.from_inv_sine(int_inv_sine),
.from_inv_cos(int_inv_cos),
.out(value)
);

store a4(
.clock(sys_clk),
.nrst(sys_rst),
.from_comp(value),
.data_out(final_data)
);

endmodule

12) Coding for FROM_ADC Block

//Module to collect Data from ADC

module from_adc(
input clk,
input rst,
output reg [63:0]sample
);

reg [255:0]sample_store =
256'ha5005a7f5a00a580_5a7f5a00a580a500_5a00a580a5005a7f_a580a5005a7f5a00;
reg signed [2:0]cnt;
always@(posedge clk or negedge rst)
begin
if(rst==1'b0)
begin
sample <= 64'hzzzzzzzz;
cnt <= -3'd1;
end
else
begin
if(cnt != 3'd3)
cnt <= cnt + 3'd1;
else
cnt <= cnt;
end

end

63
always@(cnt or sample_store)
begin
case (cnt)
3'd0 : sample = sample_store[63:0];
3'd1 : sample = sample_store[127:64];
3'd2 : sample = sample_store[191:128];
3'd3 : sample = sample_store[255:192];
default:sample = 64'hzzzzzzzz;
endcase
end
endmodule

3)Coding For CORRELATOR block :

//Multiplier Module to multiply all the sample values

module multiplier(
input [63:0]ip_sample,
output reg [16:0]op_sine,
output reg [16:0]op_cos,
output reg [16:0]op_inv_sine,
output reg [16:0]op_inv_cos
);

reg [16:0]inter1;
reg [16:0]inter2;
reg [16:0]inter3;
reg [16:0]inter4;
reg [16:0]inter5;
reg [16:0]inter6;
reg [16:0]inter7;
reg [16:0]inter8;

reg [16:0]inter_cos1;
reg [16:0]inter_cos2;
reg [16:0]inter_cos3;
reg [16:0]inter_cos4;
reg [16:0]inter_cos5;
reg [16:0]inter_cos6;
reg [16:0]inter_cos7;
reg [16:0]inter_cos8;

reg [16:0]inter_inv_cos1;
reg [16:0]inter_inv_cos2;
reg [16:0]inter_inv_cos3;
reg [16:0]inter_inv_cos4;
reg [16:0]inter_inv_cos5;

64
reg [16:0]inter_inv_cos6;
reg [16:0]inter_inv_cos7;
reg [16:0]inter_inv_cos8;

reg [16:0]inter_inv_sine1;
reg [16:0]inter_inv_sine2;
reg [16:0]inter_inv_sine3;
reg [16:0]inter_inv_sine4;
reg [16:0]inter_inv_sine5;
reg [16:0]inter_inv_sine6;
reg [16:0]inter_inv_sine7;
reg [16:0]inter_inv_sine8;

//Multiplier + Adder section For SINE Wave

always@(ip_sample)
begin

inter1= ip_sample[63:56]* 8'ha5;

inter2= ip_sample[55:48]* 8'h80;
inter3= ip_sample[47:40]* 8'ha5;
inter4= ip_sample[39:32]* 8'h00;
inter5= ip_sample[31:24]* 8'h5a;
inter6= ip_sample[23:16]* 8'h7f;
inter7= ip_sample[15:8] * 8'h5a;
inter8= ip_sample[7:0] * 8'h00;

end

always@(inter1,inter2,inter3,inter4,inter5,inter6,inter7,inter8)
begin

op_sine=inter1+inter2+inter3+inter4+inter5+inter6+inter7+inter8;
end

//Multiplier + Adder section For COSINE Wave

always@(ip_sample)
begin

inter_cos1 = ip_sample[63:56]* 8'h5a;

inter_cos2 = ip_sample[55:48]* 8'h00;
inter_cos3 = ip_sample[47:40]* 8'ha5;
inter_cos4 = ip_sample[39:32]* 8'h80;
inter_cos5 = ip_sample[31:24]* 8'ha5;
inter_cos6 = ip_sample[23:16]* 8'h00;
inter_cos7 = ip_sample[15:8] * 8'h5a;
inter_cos8 = ip_sample[7:0] * 8'h7f;

end

always@(inter_cos1,inter_cos2,inter_cos3,inter_cos4,inter_cos5,inter_cos6,int
er_cos7,inter_cos8)
begin

65
op_cos =
inter_cos1+inter_cos2+inter_cos3+inter_cos4+inter_cos5+inter_cos6+inter_cos7+
inter_cos8;
end

//Multiplier + Adder section For INV_SINE Wave

always@(ip_sample)
begin

inter_inv_sine1 = ip_sample[63:56]* 8'h5a;

inter_inv_sine2 = ip_sample[55:48]* 8'h7f;
inter_inv_sine3 = ip_sample[47:40]* 8'h5a;
inter_inv_sine4 = ip_sample[39:32]* 8'h00;
inter_inv_sine5 = ip_sample[31:24]* 8'ha5;
inter_inv_sine6 = ip_sample[23:16]* 8'h80;
inter_inv_sine7 = ip_sample[15:8] * 8'ha5;
inter_inv_sine8 = ip_sample[7:0] * 8'h00;

end

always@(inter_inv_sine1,inter_inv_sine2,inter_inv_sine3,inter_inv_sine4,inter
_inv_sine5,inter_inv_sine6,inter_inv_sine7,inter_inv_sine8)
begin

op_inv_sine =
inter_inv_sine1+inter_inv_sine2+inter_inv_sine3+inter_inv_sine4+inter_inv_sin
e5+inter_inv_sine6+inter_inv_sine7+inter_inv_sine8;
end

//Multiplier + Adder section For INV_COSINE Wave

always@(ip_sample)
begin

inter_inv_cos1 = ip_sample[63:56]* 8'ha5;

inter_inv_cos2 = ip_sample[55:48]* 8'h00;
inter_inv_cos3 = ip_sample[47:40]* 8'h5a;
inter_inv_cos4 = ip_sample[39:32]* 8'h7f;
inter_inv_cos5 = ip_sample[31:24]* 8'h5a;
inter_inv_cos6 = ip_sample[23:16]* 8'h00;
inter_inv_cos7 = ip_sample[15:8] * 8'ha5;
inter_inv_cos8 = ip_sample[7:0] * 8'h80;

end

always@(inter_inv_cos1,inter_inv_cos2,inter_inv_cos3,inter_inv_cos4,inter_inv
_cos5,inter_inv_cos6,inter_inv_cos7,inter_inv_cos8)
begin

op_inv_cos =
inter_inv_cos1+inter_inv_cos2+inter_inv_cos3+inter_inv_cos4+inter_inv_cos5+in
ter_inv_cos6+inter_inv_cos7+inter_inv_cos8;
end

endmodule

66
4) Coding For Comparator block :
//To compare and take Decision Regarding the Output Wave

module comparator(
input [16:0]from_sine,
input [16:0]from_cos,
input [16:0]from_inv_sine,
input [16:0]from_inv_cos,
output reg [1:0]out
);

always@(from_sine or from_cos or from_inv_sine or from_inv_cos)

begin
if(from_sine== 17'b11001001011111011)
out = 2'b00;
else
if(from_cos== 17'b11001001011111011)
out = 2'b01;
else
if(from_inv_sine== 17'b11001001011111011)
out = 2'b10;
else
if(from_inv_cos== 17'b11001001011111011)
out = 2'b11;
end

endmodule

5) Module to collect the Data from the CORRELATOR Section

//To collect the dat's from comparator

module store(
input clock,
input nrst,
input [1:0]from_comp,
output reg [7:0]data_out
);

reg [2:0]cnt;
reg [7:0]temp;

always@(posedge clock or negedge nrst)

begin
if(nrst==1'b0)
begin
temp <= 8'hzz;
cnt <= -3'd1;
data_out <= 8'hzz;
end
else
begin
if(cnt != 3'd4)
67
 begin
cnt <= cnt + 3'd1;
temp <= {from_comp,temp[7:2]};
end
else
begin
cnt <= cnt;
data_out <= temp;
end
end

end
endmodule

6) Program for Clock Divider

//Codinf For Clock Divider

module clock_div(clockoutput, clock,rst);

output clockoutput ;
input clock;
input rst;

reg div_2 ; //2^1

reg div_4 ; //2^2
reg div_8 ; //2^3
reg div_16; //2^4
reg div_32; //2^5
reg div_64; //2^6
reg div_128; //2^7
reg div_256; //2^8
reg div_512; //2^9
reg div_1024; //2^10
reg div_2048; //2^11
reg div_4096; //2^12
reg div_8192 ; //2^13
reg div_16384 ; //2^14
reg div_32768 ;//2^15
reg div_65536 ;//2^16
reg div_131072 ;//2^17
reg div_262144 ; //2^18
reg div_524288 ; //2^19
reg div_1048576; //2^20
reg div_2097152;//2^21
68
reg div_4194304; //2^22
reg div_8388608;//2^23

always @(posedge clock or negedge rst)

if (!rst)
div_2 <= 1'b0;
else
div_2 <= ~ div_2;

always @(posedge div_2 or negedge rst)

if (!rst)
div_4 <= 1'b0;
else
div_4 <= ~ div_4;

always @(posedge div_4 or negedge rst)

if (!rst)
div_8 <= 1'b0;
else
div_8 <= ~ div_8;

always @(posedge div_8 or negedge rst)

if (!rst)
div_16 <= 1'b0;
else
div_16 <= ~ div_16;
always @(posedge div_16 or negedge rst)
if (!rst)
div_32 <= 1'b0;
else
div_32 <= ~ div_32;

always @(posedge div_32 or negedge rst)

if (!rst)
div_64 <= 1'b0;
else
div_64 <= ~ div_64;
always @(posedge div_64 or negedge rst)
if (!rst)
div_128 <= 1'b0;
else
div_128 <= ~ div_128;
always @(posedge div_128 or negedge rst)
if (!rst)
div_256 <= 1'b0;
else
div_256 <= ~ div_256;

always @(posedge div_256 or negedge rst)

if (!rst)
div_512 <= 1'b0;
else
div_512 <= ~ div_512;

always @(posedge div_512 or negedge rst)

if (!rst)

69
 div_1024 <= 1'b0;
else
div_1024 <= ~ div_1024;

always @(posedge div_1024 or negedge rst)

if (!rst)
div_2048 <= 1'b0;
else
div_2048 <= ~ div_2048;

always @(posedge div_2048 or negedge rst)

if (!rst)
div_4096 <= 1'b0;
else
div_4096 <= ~ div_4096;

always @(posedge div_4096 or negedge rst)

if (!rst)
div_8192 <= 1'b0;
else
div_8192 <= ~ div_8192;

always @(posedge div_8192 or negedge rst)

if (!rst)
div_16384 <= 1'b0;
else
div_16384 <= ~ div_16384;

always @(posedge div_16384 or negedge rst)

if (!rst)
div_32768 <= 1'b0;
else
div_32768 <= ~ div_32768;

always @(posedge div_32768 or negedge rst)

if (!rst)
div_65536 <= 1'b0;
else
div_65536 <= ~ div_65536;

always @(posedge div_65536 or negedge rst)

if (!rst)
div_131072 <= 1'b0;
else
div_131072<= ~ div_131072;
always @(posedge div_131072 or negedge rst)
if (!rst)
div_262144 <= 1'b0;
else
div_262144<= ~ div_262144;

always @(posedge div_262144 or negedge rst)

if (!rst)
div_524288 <= 1'b0;
else
div_524288<= ~ div_524288;

70
always @(posedge div_524288 or negedge rst)
if (!rst)
div_1048576 <= 1'b0;
else
div_1048576<= ~ div_1048576;

always @(posedge div_1048576 or negedge rst)

if (!rst)
div_2097152<= 1'b0;
else
div_2097152<= ~ div_2097152;

always @(posedge div_2097152 or negedge rst)

if (!rst)
div_4194304 <= 1'b0;
else
div_4194304<= ~ div_4194304;

always @(posedge div_4194304 or negedge rst)

if (!rst)
div_8388608 <= 1'b0;
else
div_8388608<= ~ div_8388608;

assign clockoutput = div_8388608;

endmodule

71
72