Vous êtes sur la page 1sur 3

National University of Science & Technology

College of Electrical & Mechanical Engineering

Department of Electrical Engineering

Subject: EE-320 Integrated Circuits

Catalog Description: Credit 3. Class 3.

Terminal characteristics of diode, BJT and MOSFETS; Pi-model and T-model of the BJT and
MOSFETS; MOSFET Differential pair with the resistive load; BJT Differential pair with the resistive
load, Gates; MOSFET Differential pair with the active load; BJT Differential pair with the active load;
two stage op-amp; frequency response of the MOSFET differential pair; 741 Op-Amp; Sampling of
analog signals; Signal quantization; DAC converter circuits; ADC converter circuits; Overview of digital
circuit design; Design and performance analysis of the CMOS inverter, transistor sizing; CMOS logic
gate circuits; transistor sizing; CMOS inverter in n-well process; n-well CMOS design rules; Layouts for
the CMOS inverter; clocking issues; two phase clock; cell design issues; CMOS logic structures; MOS
memory and decoders.

Prerequisite: EE-213 Electronics I

Text Books: 1. Microelectronic Circuits, 5th Edition, By Sedra/ Smith. Oxford University
2. Principles of CMOS VLSI Design, 2nd Edition, By Neil E. Weste & Kamran
Reference Books: 1. Digital Integrated Circuits, A Design Perspective, by Jan M. Rabaey, 1996.
2. Microelectronics, 2nd Ed, by Millman & Grabel, McGraw Hill 1998.

Course Objectives:
To provide students thorough understanding of:
1. Characterization of discrete devices, Diode, BJT and MOSFET, Op-Amp.
2. Analysis and characterization of active circuits.
3. Building blocks of Op-Amp and their characterization
4. Analog circuit optimization with the optimized device dimensions.
5. The operational principles of DAC and ADC circuits
6. Characterization and optimization of logic building blocks
7. Overview of logic synthesisation.
8. CMOS fabrication process.
9. Physical laying out process of the standard logic cells

Course Outcomes:
After completion of this course students should:
1. Understand operational principles of BJT differential pair circuits and capable of characterize its
behavior as amplifier, (DC and small signal).
2. Understand operational principles of MOSFET differential pair circuits and capable of characterize its
behavior as amplifier, (DC and small signal).
3. Be familiar with architect of a commercially available op-amp, its building blocks and capable of
characterize them.
4. Understand the architect of ADC and DAC circuits and capable of characterize their behaviors
5. Be familiar with the Very Large Scale Integration (VLSI) fabrication processes, constraints in
designing of ICs, building blocks (MOSFETS) and performance of CMOS inverters.
6. Overview of logic synthesis and implementation constraints.
7. Understand the layout designs of standard CMOS logic cells
8. Be familiar with physical layouts of CMOS memories and combinational logic cells (decoders,
multiplication, adders and shifters).

1. BJT Differential Amplifier, Biasing in BJT integrated Circuits, BJT Differential Amplifier with active
load Week 1-2
2. MOS Differential Amplifier Week 3
3. Multistage Amplifiers Week 4
4. The 741 Op-Amp, Gain & Frequency Response of 741 Op-Amp, DC Analysis & mall signal analysis
of Op-Amp Week 5
5. CMOS Op-Amp,
6. A/D & D/A Converter Circuits, Week 6
7. Overview of VLSI, CMOS fabrication & Design Rules, Week 7
8. MOS Transistor, Switch & Gate Logic Week 8
9. CMOS Gates, Week 9
10. Logic Optimization, Week 10
11. Data Flow & FSM, Clocking Issues, Two Phase Clocking Week 11
12. Logic Synthesis and Implementation Constraints Week 12
13. Cell Design Issues, Week 12
14. CMOS Logic Structures Week 13
15. MOS Memory, Decoder/Gate sizing Week 14
16. Basic Design Concepts Week 14
17. Physical laying out of Logic Circuits, CMOS memory, Decoder, Adders, Multiplication and shifters
Week 15
Evaluation Methods: Quizzes, Assignments, Sessional exams, Final exam.

Professional Component: Analysis and design of Integrated Circuits (Engineering Topics)

Grading Policy:
Quizzes/Assignments/Class Participation: 20%
Mid-term Exam: 40%
Final Exam: 40%
Prepared by: Dr. Mojeeb Bin Ihsan/ Burhan Khan
Schedule of Assignments
Fall Semester 2010

Assignment # 1

Ex 7.1, 7.2, 7.3

End Prob.: 7.1, 7.2
Due Date: 6-10-2010
Assignment # 2

Ex 7.4, 7.5, 7.6, 7.8

End Prob.: 7.3, 7.5, 7.11, 7.13
Due Date: 20-10-2010
Assignment # 3 bjt and active load

Ex 7.9, 7.11, 7.13

End Prob.: 7.50, 7.59, 7.63, 7.71, 7.79
Due Date: 3-11-2010
Assignment # 4 freq response and multistage

Ex 7.20, 7.22, 7.23

End Prob.: 7.82, 7.88, 7.90, 7.94, 7.101
Due Date: 06-11-2010
Assignment # 5 741 opamp

Ex 9.9, 9.10, 9.12, 9.13, 9.26, 9.29

End Prob.: 9.22, 9.45, 9.58, 9.61
Due Date: 15-10-2010